UC1827-1, UC1827-2 UC2827-1, UC2827-2 UC3827-1, UC3827-2 www.ti.com SLUS365A – APRIL 1999 – REVISED AUGUST 2005 BUCK CURRENT/VOLTAGE FED PUSH-PULL PWM CONTROLLERS FEATURES • • • • • • • • DESCRIPTION Ideal for Multiple Output and/or High Voltage Output Voltage Converters Up to 500 kHz Operation High Voltage, High Current Floating Driver for Buck Converter Stage UC3827-1 Current Fed Controller has Push-Pull Drivers with Overlapping Conduction Periods UC3827-2 Voltage Fed Controller has Push-Pull Drivers with Nonoverlapping Conduction Periods Average Current Mode, Peak Current Mode or Voltage Mode with Input Voltage Feedforward Control for Buck Power Stage Wide Bandwidth, Low Offset, Differential Current Sense Amplifier Precise Short Circuit Current Control The UC3827 family of controller devices provides an integrated control solution for cascaded buck and push-pull converters. These converters are known as current fed or voltage fed push-pull converters and are ideally suited for multiple output and/or high voltage output applications. In both current fed and voltage fed modes, the push-pull switches are driven at 50% nominal duty cycles and at one half the switching frequency of the buck stage. In the current fed mode, the two switches are driven with a specified over-lap period to prevent ringing and voltage stress on the devices. In the voltage fed mode, the two switches are driven with a specified gap time between the switches to prevent shorting the transformer across the energy storage capacitor and to prohibit excessive currents flowing through the devices. The converter's output voltage is regulated by pulse width modulation of the buck switch. The UC3827 contains complete protection and PWM control functions for the buck converter. Easy control of the floating switch is accomplished by the floating drive circuitry. The gate drive waveform is level shifted to support an input voltage up to 72 VDC. BLOCK DIAGRAM VEAOCEA+ 10 12 CEAO 6 RAMP 5 Voltage Error Amplifier 14 VEA− 16 CEA− 13 CSAO 7 CSA+ 8 CSA− 9 SS 4 SYNC 0.7 V Current Error Amplifier RD 18 RT 17 500 kHz MAX 23 GND 11 SS INHBT Q 1 V+ 2 BUCK 3 SRC 21 PGND 24 PUSH 22 PULL OSC UV CT REF S ILIM Comparator Current Sense Amplifier OSC VCC Flying Driver +3 V 19 15 PWM Comparator + VEA+ Q DELAY T Push/Pull Drivers Q REF & UVLO UVLO DELAY 20 DELAY Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1999–2005, Texas Instruments Incorporated UC1827-1, UC1827-2 UC2827-1, UC2827-2 UC3827-1, UC3827-2 www.ti.com SLUS365A – APRIL 1999 – REVISED AUGUST 2005 DESCRIPTION (CONTINUED) The UC3827 can be set up in traditional voltage mode control using input voltage feedforward technique or in current mode control. Using current mode control prevents potential core saturation of the push-pull transformer due to mismatches in timing and in component tolerances. With average current mode control, precise control of the inductor current feeding the push-pull stage is possible without the noise sensitivity associated with peak current mode control. The UC3827 average current mode loop can also be connected in parallel with the voltage regulation loop to assist only in fault conditions. Other valuable features of the UC3827 include bidirectional synchronization capability, user programmable overlap time (UC3827-1), user programmable gap time (UC3827-2), a high bandwidth differential current sense amplifier, and soft start circuitry. ORDERING INFORMATION (1) TA = TJ PUSH-PULL TOPOLOGY -55°C to 125°C -40°C to 85°C 0°C to 70°C (1) PACKAGES SOIC-24 PDIP-24 UC1827J-1 PLCC-28 Current Fed UC1827J-1 Voltage Fed UC1827J-2 UC1827J-2 Current Fed UC2827DW-1 UC2827N-1 - Voltage Fed UC2827DW-2 UC2827N-2 - Current Fed UC3827DW-1 UC3827N-1 UC3827Q-1 Voltage Fed UC3827DW-2 UC3827N-2 - The DW and Q packages are also available taped and reeled. Add a TR suffix to the device type (i.e., UC2827DWTR-1). DISSIPATION RATINGS PACKAGE (θJA) JUNCTION-TO-AMBIENT TEMPERATURE (°C/W) (θJC) JUNCTION-TO-WHAT? TEMPERATURE (°C/W) 24-pin (N) 60 (1) 30 24-pin (J) 70 to 90 28 (2) 28-pin (DW) 28-pin (QLCC) (1) (2) (3) 2 71 to 83 (3) 40-65 (1) 24 (3) 30 Specified θJA (junction-to-ambient) refers to devices mounted to 5-in2 FR4 PC board with 1 oz. copper where noted. When a resistance range is given, the lower values refer to a 5-in2 aluminum PC board. The test PWB is 0.062 inches thick and typically used 0.635 mm trace widths for power packages and 1.3 mm trace widths for non-power packages with a 100 × 100 mil probe land area at the end of each trace. Specified θJC (junction-to-what?) data values stated were derived from MIL-STD-1835B which states "The baseline values shown are worst case (mean + 2s) for a 60 x 60 mil microcircuit device silicon die and applicable for devices with die sizes up to 14400 mils2. For device sizes greater than 14400 mils2 use the following values; dual-in-line, 11 °C/W; flat pack, 10 °C/W; pin grid array, 10 °C/W pin grid array, 10 °C/W." Modeled data. If there is a value range given for θJA, the lower value refers to a 3 x 3 in., 1-oz, internal copper ground plane. The higher value refers to a 1 x 1 in. ground plane. All model data assumes only one trace for each non-fused lead. UC1827-1, UC1827-2 UC2827-1, UC2827-2 UC3827-1, UC3827-2 www.ti.com SLUS365A – APRIL 1999 – REVISED AUGUST 2005 ABSOLUTE MAXIMUM RATINGS (1) UC2827-1 UC2827-2 UC3827-1 UC3827-2 Supply voltage, VCC UNITS 20 CEAO, CEA+, CEA-, CSAO, CSA+, CSA-, CT, DELAY, PUSH, PULL, RAMP, RT, SS, SYNC, VEA+, VEAO, Input voltage range –0.3 to 5 V+ and BUCK SRC 90-VCC I/O continuous BUCK driver ±250 mA ±1 A I/O continuous ±200 mA I/O peak ±0.8 A I/O peak PUSH/PULL driver V 90 Storage temperature –65 to 150 Junction temperature –55 to 150 Lead temperature (soldering, 10 sec) 300 Voltages are referenced to ground. Currents are positive into, negative out of the specified terminal. Consult Packaging section of databook for thermal limitations and considerations of packages. CONNECTION DIAGRAMS PLCC-28 (Q PACKAGE) (TOP VIEW) DIL-24 (N or J, DW PACKAGES) (TOP VIEW) Q PACKAGE (TOP VIEW) V+ BUCK SRC SS RAMP CEAO CSAO CSA+ CSA− VEAO GND CEA+ 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 SRC BUCK NC V+ PUSH VCC PULL N, J OR DW PACKAGES (TOP VIEW) PUSH VCC PULL PGND DELAY SYNC CT RT VEA− REF VEA+ CEA− SS RAMP CEAO CSAO CSA+ CSA− VEAO 5 4 3 2 1 28 27 26 25 6 24 7 23 8 22 9 21 10 20 11 19 12 13 14 15 16 17 18 PGND NC NC DELAY SYNC CT RT GND CEA+ CEA− VEA+ REF NC VEA− (1) °C NC − No internal connection 3 UC1827-1, UC1827-2 UC2827-1, UC2827-2 UC3827-1, UC3827-2 www.ti.com SLUS365A – APRIL 1999 – REVISED AUGUST 2005 Terminal Functions TERMINAL I/O DESCRIPTION N or DW Q BUCK 2 3 O Output of the buck PWM controller. The BUCK output is a floating driver, optimized for controlling the gate of an N-channel MOSFET. The peak sink and source currents are 1 A. VCC undervoltage faults disables BUCK to an off condition (low). CEA+ 12 13 I Non-inverting input of the current error amplifier. CEA- 13 14 I Inverting input of the current error amplifier CEAO 6 7 O Output of the current error amplifier and the inverting input of the PWM comparator of the buck converter. CSA+ 8 9 I Noninverting input of the current sense amplifier. CSA– 9 10 I Inverting input of the current sense amplifier. CSAO 7 8 O Output of the current sense amplifier and the noninverting input of the current limit comparator. When the signal level on this pin exceeds the 3V threshold of the current limit comparator, the buck gate drive pulse is terminated. This feature is useful to implement cycle-by-cycle current limiting for the buck converter. CT 18 20 I Provides for the timing capacitor which is connected between CT and GND. The oscillator frequency is set by CT and a resistor RT, connected between pin RT and GND. The CT discharge current is approximately 40 x the bias current through the resistor connected to RT. A practical maximum value for the discharge current is 20 mA. The frequency of the oscillator is given by equation (1) DELAY 20 22 I A resistor to GND programs the overlap time of the PUSH and PULL outputs of the UC3827-1 and the dead time of the PUSH and PULL outputs of the UC3827-2. The minimum value of the resistor, RDELAY, is 18 kΩ. The delay or overlap time is given by equation (2) GND 11 12 - Ground reference for all sensitive setup components not related to driving the outputs. They include all timing, voltage sense, current sense, and bypass components. PGND 21 25 - Ground connection for the PUSH and PULL outputs. PGND must be connected to GND at a single point on the printed circuit board. This is imperative to prevent large, high frequency switching currents flowing through the ground metalization inside the device. PULL 22 26 O Ground referenced output to drive an N-channel MOSFET. The PULL and the PUSH outputs are driving the two switches of the push-pull converter with complementary signals at close to a 50% duty cycle. Any undervoltage faults will disable PULL to an off condition (low). PUSH 24 28 O Ground referenced output to drive an N-channel MOSFET. The PULL and the PUSH outputs are driving the two switches of the push-pull converter with complementary signals at close to a 50% duty cycle. Any undervoltage faults disables PUSH to an off condition (low). NAME RAMP 5 6 I The RAMP voltage, after a 700 mV internal level shift, is fed to the noninverting input of the buck PWM comparator. A resistor to VIN and a capacitor to GND provide an input voltage feedforward signal for the buck controller in voltage mode control. In peak current mode control, the RAMP pin receives the current signal of the buck converter. In an average current mode setup, the RAMP pin has a linearly increasing ramp signal. This waveform may be generated either by connecting RAMP directly to CT, or by connecting both a resistor from VCC to RAMP and a capacitor from RAMP to GND. REF 15 16 O The output of the +5V on board reference. Bypass this pin with a capacitor to GND. The reference is off when the chip is in undervoltage lockout mode.o RT 17 19 I A resistor to GND programs the charge current of the timing capacitor connected to CT. The charge current approximately equals that shown in equation (3). The charge current should be less than 500 µA to keep CT's discharge peak current less than 20 mA, which is CT's maximum practical discharge value. The discharge time, which sets the maximum duty cycle, is set internally and is influenced by the charge current. SRC 3 4 I The source connection for the floating buck switch. The voltage on the SRC pin can exceed VCC but must be lower than 90 V–VVCC. Also, during turn-off transients of the buck switch, the voltage at SRC can go to –2V. 0.77 (Hz) RRT CCT R t DELAY DELAY 109 (s) 200 2.5 V I RT RRT f OSC (1) (2) (3) 4 UC1827-1, UC1827-2 UC2827-1, UC2827-2 UC3827-1, UC3827-2 www.ti.com SLUS365A – APRIL 1999 – REVISED AUGUST 2005 Terminal Functions (continued) TERMINAL I/O DESCRIPTION N or DW Q SS 4 5 O 5Soft-start pin requires a capacitor to GND. During soft-start the output of the voltage error amplifier is clamped to the soft-start capacitor voltage which is slowly charged by an internal current source. In UVLO, SS is held low. SYNC 19 21 I A bidirectional pin for the oscillator., used to synchronize several chips to the fastest oscillator. Its input synchronization threshold is 1.4 V. The SYNC voltage is 3.6 V when the oscillator capacitor, CT, is discharged. Otherwise it is 0 V. If the recommended synchronization circuit is not used, a 1 kΩ or lower value resistor from SYNC to GND may be needed to increase the fall time of the signal at SYNC. VCC 23 27 I A voltage source connected to this pin supplies the power for the UC3827. It is recommended to bypass this pin to both GND and PGND ground connections with good quality high frequency capacitors VEA+ 14 15 I Non-inverting input of the voltage error amplifier VEA- 16 18 I Inverting input of the voltage error amplifier VEAO 10 11 O Output of the voltage error amplifier V+ 1 1 I Supply voltage for the buck output. The floating driver of the UC3827 uses the bootstrap technique which requires a reservoir capacitor to store the required energy for the on time of the buck switch. A diode must be connected from VCC to V+ to charge the reservoir capacitor. This diode must be able to withstand VIN. The reservoir capacitor must be connected between V+ and SRC. NAME ELECTRICAL CHARACTERISTICS Unless otherwise spsecified, VVCC = 15 V, VV+ = 14.3 V, CCT = 340 pF, RRT = 10 kΩ, RDELAY = 24.3 kΩ, VSRC = VGND = VBUCK= VPUSH = VPULL outputs no load, TJ = TA PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VCC UVLO, Turn-on 8.3 8.8 9.5 Hysteresis 0.9 1.2 1.5 V 1000 µA 32 45 mA 1 2 mA 0.5 3 µA 10 mV SUPPLY IVCC Supply current start IVCC Supply current run VVCC = 8 V IV+ buck high 0.2 V VOLTAGE ERROR AMPLIFIER IB VIO AVOL GBW (1) Gain bandwidth VOL Low-level output voltage IVEAO = 0 µA (No load) VOH High-level output voltage IVEAO = 0 µA (No load) 80 95 dB 1 4 MHz 2.85 0.3 0.5 V 3 3.20 V –1 –5 µA 5 mV CURRENT SENSE AMPLIFIER IB VIO AVOL GBW (1) Gain bandwidth VOL Low-level output voltage ICEAO = 0 µA (No load) VOH High-level output voltage ICEAO = 0 µA (No load) CMRR Common mode range (1) 80 110 dB 15 29 MHz 0.25 3 0.5 3.3 -0.3 V V 2 V CURRENT ERROR AMPLIFIER IB –1 VIO AVOL (1) 80 110 –5 µA 10 mV dB Ensured by design. Not production tested. 5 UC1827-1, UC1827-2 UC2827-1, UC2827-2 UC3827-1, UC3827-2 www.ti.com SLUS365A – APRIL 1999 – REVISED AUGUST 2005 ELECTRICAL CHARACTERISTICS (continued) Unless otherwise spsecified, VVCC = 15 V, VV+ = 14.3 V, CCT = 340 pF, RRT = 10 kΩ, RDELAY = 24.3 kΩ, VSRC = VGND = VBUCK= VPUSH = VPULL outputs no load, TJ = TA PARAMETER GBW (1) TEST CONDITIONS Gain bandwidth At 100 kHz, Measure Gain VOL ICEAO = 0 µA (No Load) VOH ICEAO = 0 µA (No Load) CMRR Common mode MIN 2 TYP 4.5 0.25 3.3 range (1) MAX MHz 0.5 3.5 -0.3 UNIT V V 5 V OSCILLATOR SECTION fOSC Frequency ICT(dsch) CT discharge current 180 3.5V at CT when CT removed 220 250 5 kHz mA PWM COMPARATOR DMAX Minimum duty cycle 200 kHz DMAX Maximum duty cycle 200 kHz 0% 85% 91% 95% BUCK OUTPUT STAGE tRISE Rise time 1 nF Load (2) 40 100 ns tFALL Fall tIme 1 nF, Load 30 80 ns 1.5 2.5 V 2 2.5 V 0.2 0.4 V 0.7 1.2 V VOH IBUCK = –15 mA , V+ High-level output voltage VOL –BUCK (3) IBUCK = –150 mA, V+ –BUCK (3) IBUCK = 15 mA (4) Low-level output voltage IBUCK = 150 mA (4) PUSH/PULL OUTPUT STAGES tRISE Rise time 1 nF load 50 100 ns tFALL Fall tIme 1 nF load 35 100 ns 100 250 400 ns 100 250 500 ns 2 3 V IPUSH/PULL = –100 mA, VCC – PUSH (7) 2.5 3 V IPUSH/PULL = 10 mA (7) 0.2 0.8 V 0.6 1.2 V 4.8 5 5.2 V –35 Overlap time Nonoverlapping time UCx827-1 1 nF (6) loads (5) UCx827-2 IPUSH/PULL = –10 mA, VCC – PUSH (7) VOH High-level output voltage VOL Low-level output voltage IPUSH/PULL = 100 mA (7) REFERENCE Reference voltage ISC Shor-circuit current VREF = 0V –50 –65 mA Line regulation 0.5V < VVCC < 20 V 5 20 mV Load regulation 0 mA < IIO < 10 mA 8 20 mV 250 500 mV –12 –25 µA SOFT START VOL Low-level output voltage saturation ISS Soft-start current (2) (3) (4) (5) (6) (7) 6 VVCC = 7 V –5 Measure the rise time from when BUCK crosses 1 V until it crosses 9 V. To force BUCK high, force VCSAO=2.5 V, VCEAO = 2.5 V, a 25-kΩ pulldown resistor from RAMP to ground, and VCT = 0.5 V. To force BUCK low, force VCSAO = 2.5 V, VCEAO = 2.5 V, a 10-kΩ pulldown resistor from RAMP to ground, and VCT = 3.5 V. The overlap time is measured from the point at which the rising edge of PUSH/PULL crosses 5 V until the falling edge of PULL/PUSH crosses 5V. The non-overlap time is measured from the point at which the falling edge of PUSH/PULL crosses 5 V until the rising edge of PULL/PUSH crosses 5 V. To toggle PUSH or PULL into a desired state, pulse CT from 0.5 V to 3.5 V. PUSH and PULL toggle on the rising edge of CT. UC1827-1, UC1827-2 UC2827-1, UC2827-2 UC3827-1, UC3827-2 www.ti.com SLUS365A – APRIL 1999 – REVISED AUGUST 2005 APPLICATION INFORMATION VREF RT 2.5 V – + RT CT OSCILLATOR VREF 1.4 V 2.5 V 2.9 V CT S R SYNC 0.5 V 10 k VDG−99086 Figure 1. Oscillator Block With External Connections CIRCUIT BLOCK DESCRIPTION PWM Oscillator The oscillator block diagram with external connections is shown in Equation 1. A resistor (RT) connected to pin RT sets the linear charge current: I RT 2.5 V RRT (1) The timing capacitor (CCT) is linearly charged with the charge current forcing the OSC pin to charge to a 3.4 V threshold. After exceeding this threshold, the RS flip-flop is set driving CLKSYN high and RDEAD low which discharges CCT. CT continues to discharge until it reaches a 0.5 V threshold and resets the RS flip-flop which repeats the charging sequence as shown in Figure 2 As shown in Figure 3, several oscillators are synchronized to the highest free running frequency by connecting 100 pF capacitors in series with each CLKSYN pin and connecting the other side of the capacitors together forming the CLKSYN bus. The CLKSYN bus is then pulled down to ground with a resistance of approximately 10k. Referring to Figure 1, the synchronization threshold is 1.4 V. The oscillator blanks any synchronization pulse that occurs when OSC is below 2.5 V. This allows units, once they discharge below 2.5 V, to continue through the current discharge and subsequent charge cycles whether or not other units on the CLKSYN bus are still synchronizing. This requires the frequency of all free running oscillators to be within 17% of each other to assure synchronization. 7 UC1827-1, UC1827-2 UC2827-1, UC2827-2 UC3827-1, UC3827-2 www.ti.com SLUS365A – APRIL 1999 – REVISED AUGUST 2005 APPLICATION INFORMATION (continued) VAO Current Command Charging Discharging OSC 2.9 V 0.5 V THRESHOLD 3.6 V 1.4 V Threshold CLKSYN 8.5 V OUT 0V VDG−99087 Figure 2. Oscillator and PWM Output Waveform OSC2 OSC3 SYNC SYNC SYNC 100 pF 100 pF 100 pF CLKSYN BUS OSC1 100 pF OSC10 SYNC 10 k VDG−99085 Figure 3. Oscillator Synchronization Connection Diagram REVISION HISTORY REVISION SLUS365A 8 DATE OF CHANGE 8/2005 DESCRIPTION Improved CMRR of CSA from ( 0 - 2 V) to ( -0.3 - 2 V) Improved CMRR of CEA from ( 0 - 5 V) to ( -0.3 - 5 V) PACKAGE OPTION ADDENDUM www.ti.com 17-Nov-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) UC1827J-1 OBSOLETE CDIP J 24 TBD Call TI Call TI UC1827L-1 OBSOLETE TO/SOT L 20 TBD Call TI Call TI UC2827DW-1 ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR UC2827DW-2 ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR UC2827DW-2G4 ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR UC2827DWTR-1 ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR UC2827DWTR-2 ACTIVE SOIC DW 24 2000 TBD CU NIPDAU Level-3-235C-168 HR UC2827N-1 ACTIVE PDIP N 24 15 TBD Call TI Level-NA-NA-NA Level-NA-NA-NA UC2827N-2 ACTIVE PDIP N 24 15 TBD Call TI UC3827DW-1 ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR UC3827DW-1G4 ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR UC3827DW-2 ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR UC3827DWTR-1 ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR UC3827DWTR-1G4 ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR UC3827DWTR-2 ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR UC3827DWTR-2G4 ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR UC3827N-1 ACTIVE PDIP N 24 15 TBD Call TI Level-NA-NA-NA UC3827N-2 ACTIVE PDIP N 24 15 TBD Call TI Level-NA-NA-NA (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 17-Nov-2005 provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 MECHANICAL DATA MCDI004A – JANUARY 1995 – REVISED NOVEMBER 1997 J (R-GDIP-T**) CERAMIC DUAL-IN-LINE PACKAGE 24 PINS SHOWN B 13 24 C 1 12 0.065 (1,65) 0.045 (1,14) Lens Protrusion (Lens Optional) 0.010 (0.25) MAX 0.175 (4,45) 0.140 (3,56) 0.090 (2,29) 0.060 (1,53) A Seating Plane 0.018 (0,46) MIN 24 PINS ** DIM ”A” ”B” ”C” NARR 0.125 (3,18) MIN 0.022 (0,56) 0.014 (0,36) 0.100 (2,54) 0.012 (0,30) 0.008 (0,20) 28 WIDE NARR 40 32 WIDE NARR WIDE NARR WIDE MAX 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) MIN 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) MAX 1.265(32,13) 1.265(32,13) 1.465(37,21) 1.465(37,21) 1.668(42,37) 1.668(42,37) 2.068(52,53) 2.068(52,53) MIN 1.235(31,37) 1.235(31,37) 1.435(36,45) 1.435(36,45) 1.632(41,45) 1.632(41,45) 2.032(51,61) 2.032(51,61) MAX 0.541(13,74) 0.598(15,19) 0.541(13,74) 0.598(15,19) 0.541(13,74) 0.598(15,19) 0.541(13,74) 0.598(15,19) MIN 0.514(13,06) 0.571(14,50) 0.514(13,06) 0.571(14,50) 0.514(13,06) 0.571(14,50) 0.514(13,06) 0.571(14,50) 4040084/C 10/97 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Window (lens) added to this group of packages (24-, 28-, 32-, 40-pin). This package can be hermetically sealed with a ceramic lid using glass frit. Index point is provided on cap for terminal identification. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MPDI006B – SEPTEMBER 2001 – REVISED APRIL 2002 N (R–PDIP–T24) PLASTIC DUAL–IN–LINE 1.222 (31,04) MAX 24 13 0.360 (9,14) MAX 1 12 0.070 (1,78) MAX 0.200 (5,08) MAX 0.425 (10,80) MAX 0.020 (0,51) MIN Seating Plane 0.125 (3,18) MIN 0.100 (2,54) 0’–15’ 0.021 (0,53) 0.015 (0,38) 0.010 (0,25) 0.010 (0,25) NOM 4040051–3/D 09/01 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS–010 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MPDI008 – OCTOBER 1994 N (R-PDIP-T**) PLASTIC DUAL-IN-LINE PACKAGE 24 PIN SHOWN A 24 13 0.560 (14,22) 0.520 (13,21) 1 12 0.060 (1,52) TYP 0.200 (5,08) MAX 0.610 (15,49) 0.590 (14,99) 0.020 (0,51) MIN Seating Plane 0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.125 (3,18) MIN 0.010 (0,25) M PINS ** 0°– 15° 0.010 (0,25) NOM 24 28 32 40 48 52 A MAX 1.270 (32,26) 1.450 (36,83) 1.650 (41,91) 2.090 (53,09) 2.450 (62,23) 2.650 (67,31) A MIN 1.230 (31,24) 1.410 (35,81) 1.610 (40,89) 2.040 (51,82) 2.390 (60,71) 2.590 (65,79) DIM 4040053 / B 04/95 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. 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