TI REG102NA-5/3K

REG102
REG
102
REG
102
SBVS024E – NOVEMBER 2000 – REVISED MARCH 2003
DMOS
250mA Low-Dropout Regulator
FEATURES
DESCRIPTION
● NEW DMOS TOPOLOGY:
Ultra Low Dropout Voltage:
150mV typ at 250mA
Output Capacitor not Required for Stability
● FAST TRANSIENT RESPONSE
● VERY LOW NOISE: 28µVrms
● HIGH ACCURACY: ±1.5% max
● HIGH EFFICIENCY:
IGND = 600µA at IOUT = 250mA
Not Enabled: IGND = 0.01µA
● 2.5V, 2.8V, 2.85V, 3.0V, 3.3V, AND 5.0V
ADJUSTABLE OUTPUT VERSIONS
● OTHER OUTPUT VOLTAGES AVAILABLE UPON
REQUEST
● FOLDBACK CURRENT LIMIT
● THERMAL PROTECTION
● SMALL SURFACE-MOUNT PACKAGES:
SOT23-5, SOT223-5, and SO-8
The REG102 is a family of low-noise, low-dropout linear
regulators with low ground pin current. The new DMOS
topology provides significant improvement over previous
designs, including low-dropout voltage (only 150mV typ at
full load), and better transient performance. In addition, no
output capacitor is required for stability, unlike conventional
low-dropout regulators that are difficult to compensate and
require expensive low ESR capacitors greater than 1µF.
Typical ground pin current is only 600µA (at IOUT = 250mA)
and drops to 10nA when not enabled. Unlike regulators with
PNP pass devices, quiescent current remains relatively constant over load variations and under dropout conditions.
The REG102 has very low output noise (typically 28µVrms
for VOUT = 3.3V with CNR = 0.01µF), making it ideal for use
in portable communications equipment. On-chip trimming
results in high output voltage accuracy. Accuracy is maintained over temperature, line, and load variations. Key parameters are tested over the specified temperature range
(–40°C to +85°C).
The REG102 is well protected—internal circuitry provides a
current limit that protects the load from damage; furthermore,
thermal protection circuitry keeps the chip from being damaged by excessive temperature. The REG102 is available in
SOT23-5, SOT223-5, and SO-8 packages.
APPLICATIONS
●
●
●
●
●
●
PORTABLE COMMUNICATION DEVICES
BATTERY-POWERED EQUIPMENT
PERSONAL DIGITAL ASSISTANTS
MODEMS
BAR-CODE SCANNERS
BACKUP POWER SUPPLIES
Enable
Enable
VOUT
VIN
+
0.1µF
NR
REG102
(Fixed Voltage
Versions)
+
COUT(1)
VIN
VOUT
+
REG102-A
+
COUT(1)
Adj
GND
NR = Noise Reduction
0.1µF
R1
GND
R2
NOTE: (1) Optional.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 2000-2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
www.ti.com
PIN CONFIGURATIONS
Top View
SOT23-5
VIN
1
GND
2
Enable
3
SO-8
SOT223-5
5
4
VOUT
Tab is GND
NR/Adjust(1)
1
2
3
4
VOUT(2)
1
8
VIN(3)
VOUT(2)
2
7
VIN(3)
NR/Adjust(1)
3
6
NC
GND
4
5
Enable
5
(N Package)
VIN
VOUT
GND
Enable
NR/Adjust(1)
(U Package)
(G Package)
NOTES: (1) For REG102A-A: voltage setting resistor pin.
All other models: noise reduction capacitor pin.
(2) Both pin 1 and pin 2 must be connected.
(3) Both pin 7 and pin 8 must be connected.
ABSOLUTE MAXIMUM RATINGS(1)
Supply Input Voltage, VIN ....................................................... –0.3V to 12V
Enable Input ............................................................................ –0.3V to VIN
Output Short-Circuit Duration ...................................................... Indefinite
Operating Temperature Range (TJ) ................................ –55°C to +125°C
Storage Temperature Range (TA) ................................... –65°C to +150°C
Lead Temperature (soldering, 3s) .................................................. +240°C
NOTE: (1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods may degrade
device reliability.
2
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
REG102
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SBVS024E
PACKAGE/ORDERING INFORMATION
PRODUCT
PACKAGE-LEAD
PACKAGE
DESIGNATOR(1)
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
5V Output
REG102
SOT23-5
DBV
R02B
"
"
"
SO-8
D
REG102U5
"
"
"
SOT223-5
DCQ
REG102G50
REG102NA-5/250
REG102NA-5/3K
REG102UA-5
REG102UA-5/2K5
REG102GA-5
REG102GA-5/2K5
Tape and Reel, 250
Tape and Reel, 3000
Rails, 100
Tape and Reel, 2500
Rails, 78
Tape and Reel, 2500
REG102NA-3.3/250
REG102NA-3.3/3K
REG102UA-3.3
REG102UA-3.3/2K5
REG102GA-3.3
REG102GA-3.3/2K5
Tape and Reel, 250
Tape and Reel, 3000
Rails, 100
Tape and Reel, 2500
Rails, 78
Tape and Reel, 2500
REG102NA-3/250
REG102NA-3/3K
REG102UA-3
REG102UA-3/2K5
REG102GA-3
REG102GA-3/2K5
Tape and Reel, 250
Tape and Reel, 3000
Rails, 100
Tape and Reel, 2500
Rails, 78
Tape and Reel, 2500
REG102NA-2.85/250
REG102NA-2.85/3K
REG102UA-2.85
REG102UA-2.85/2K5
REG102GA-2.85
REG102GA-2.85/2K5
Tape and Reel, 250
Tape and Reel, 3000
Rails, 100
Tape and Reel, 2500
Rails,78
Tape and Reel, 2500
REG102NA-2.8/250
REG102NA-2.8/3K
REG102UA-2.8
REG102UA-2.8/2K5
REG102GA-2.8
REG102GA-2.8/2K5
Tape and Reel, 250
Tape and Reel, 3000
Rails, 100
Tape and Reel, 2500
Rails, 78
Tape and Reel, 2500
REG102NA-2.5/250
REG102NA-2.5/3K
REG102UA-2.5
REG102UA-2.5/2K5
REG102GA-2.5
REG102GA-2.5/2K5
Tape and Reel, 250
Tape and Reel, 3000
Rails, 100
Tape and Reel, 2500
Rails, 78
Tape and Reel, 2500
REG102NA-A/250
REG102NA-A/3K
REG102UA-A
REG102UA-A/2K5
REG102GA-A
REG102GA-A/2K5
Tape and Reel, 250
Tape and Reel, 3000
Rails, 100
Tape and Reel, 2500
Rails, 78
Tape and Reel, 2500
"
REG102
"
REG102
"
"
"
"
3.3V Output
REG102
SOT23-5
DBV
R02C
"
"
"
"
SO-8
D
REG102U33
"
"
"
SOT223-5
DCQ
REG102G33
"
"
"
SOT23-5
DBV
R02G
"
"
"
SO-8
D
REG102U3
"
"
"
SOT223-5
DCQ
REG102G30
REG102
"
REG102
"
3V Output
REG102
"
REG102
"
REG102
"
"
"
"
2.85V Output
REG102
SOT23-5
DBV
R02N
"
"
"
"
SO-8
D
REG102285
"
"
"
SOT223-5
DCQ
REG102285
REG102
"
REG102
"
"
"
"
2.8V Output
REG102
SOT23-5
DBV
R02E
"
"
"
"
SO-8
D
REG102U28
"
"
"
SOT223-5
DCQ
REG102G28
REG102
"
REG102
"
"
"
"
2.5V Output
REG102
SOT23-5
DBV
R02D
"
"
"
"
SO-8
D
REG102U25
"
"
"
SOT223-5
DCQ
REG102G25
"
"
"
SOT23-5
DBV
R02A
"
"
"
SO-8
D
REG102UA
"
"
"
SOT223-5
DCQ
R102GA
"
"
"
REG102
"
REG102
"
Adjustable Output
REG102
"
REG102
"
REG102
"
NOTE: (1) For most current specifications and package information, refer to our web site at www.ti.com.
Many custom output voltage versions, from 2.5V to 5.1V in 50mV increments, are available upon request.
Minimum order quantities apply. Contact factory for details.
REG102
SBVS024E
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3
ELECTRICAL CHARACTERISTICS
Boldface limits apply over the specified temperature range, TJ = –40°C to +85°C.
At TJ = +25°C, VIN = VOUT + 1V (VOUT = 2.5V for REG102-A), VENABLE = 1.8V, IOUT = 5mA, CNR = 0.01µF, and COUT = 0.1µF(1), unless otherwise noted.
REG102NA
REG102GA
REG102UA
PARAMETER
OUTPUT VOLTAGE
Output Voltage Range
REG102-2.5
REG102-2.8
REG102-2.85
REG102-3.0
REG102-3.3
REG102-5
REG102-A
Reference Voltage
Adjust Pin Current
Accuracy
Over Temperature
vs Temperature
vs Line and Load
Over Temperature
DC DROPOUT VOLTAGE(2)
For all models
Over Temperature
VOLTAGE NOISE
f = 10Hz to 100kHz
Without CNR (all models)
With CNR (all fixed voltage models)
OUTPUT CURRENT
Current Limit(3)
Over Temperature
Short-Circuit Current Limit
CONDITION
MIN
2.5
2.8
2.85
3.0
3.3
5
2.5
dVOUT/dT
50
±0.8
IOUT = 5mA to 250mA, VIN = (VOUT + 0.4V) to 10V
VIN = (VOUT + 0.6V) to 10V
VDROP
TEMPERATURE RANGE
Specified Range
Operating Range
Storage Range
Thermal Resistance
SOT23-5 Surface-Mount
SO-8 Surface-Mount
SOT223-5 Surface-Mount
±2.8
IOUT = 5mA
IOUT = 250mA
IOUT = 250mA
4
150
10
220
270
mV
mV
mV
CNR = 0, COUT = 0
CNR = 0.01µF, COUT = 10µF
23µVrms/V • VOUT
7µVrms/V • VOUT
1
±1.5
±2.3
±2.0
Vn
ICL
340
300
ISC
VENABLE
IENABLE
400
150
mA
mA
mA
65
dB
1.8
–0.2
VENABLE = 1.8V to VIN, VIN = 1.8V to
VENABLE = 0V to 0.5V
COUT = 1.0µF, RLOAD = 13Ω
COUT = 1.0µF, RLOAD = 13Ω
6.5(4)
µVrms
µVrms
1
2
50
1.5
470
490
VIN
0.5
100
100
IGND
V
V
nA
nA
µs
ms
°C
°C
160
140
Enable Pin Low
INPUT VOLTAGE
Operating Input Voltage Range(5)
Specified Input Voltage Range
Over Temperature
UNITS
V
V
V
V
V
V
V
V
µA
%
%
ppm/°C
%
%
5.5
1.26
0.2
±0.5
VREF
IADJ
THERMAL SHUTDOWN
Junction Temperature
Shutdown
Reset from Shutdown
GROUND PIN CURRENT
Ground Pin Current
MAX
VOUT
RIPPLE REJECTION
f = 120Hz
ENABLE CONTROL
VENABLE High (output enabled)
VENABLE Low (output disabled)
IENABLE High (output enabled)
IENABLE Low (output disabled)
Output Disable Time
Output Enable Softstart Time
TYP
500
800
0.2
µA
µA
µA
1.8
VOUT + 0.4
VOUT + 0.6
10
10
10
V
V
V
–40
–55
–65
+85
+125
+150
°C
°C
°C
IOUT = 5mA
IOUT = 250mA
VENABLE ≤ 0.5V
400
600
0.01
VIN
VIN > 1.8V
VIN > 1.8V
TJ
TJ
TA
θJA
θJA
θJC
θJA
Junction-to-Ambient
Junction-to-Ambient
Junction-to-Case
Junction-to-Ambient
200
150
15
See Figure 8
°C/W
°C/W
°C/W
°C/W
NOTES: (1) The REG102 does not require a minimum output capacitor for stability, however, transient response can be improved with proper capacitor selection.
(2) Dropout voltage is defined as the input voltage minus the output voltage that produces a 2% change in the output voltage from the value at VIN = VOUT + 1V
at fixed load. (3) Current limit is the output current that produces a 10% change in output voltage from VIN = VOUT + 1V and IOUT = 5mA. (4) For VENABLE > 6.5V,
see typical characteristic IENABLE vs VENABLE. (5) The REG102 no longer regulates when VIN < VOUT + VDROP (MAX). In dropout, the impedance from VIN to VOUT is
typically less than 1Ω at TJ = +25°C.
4
REG102
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SBVS024E
TYPICAL CHARACTERISTICS
For all models, at TJ = +25°C and VENABLE = 1.8V, unless otherwise noted.
LOAD REGULATION vs TEMPERATURE
(VIN = VOUT + 1V)
0.80
0%
0.60
–0.1%
Output Voltage Change (%)
Output Voltage Change (%)
OUTPUT VOLTAGE CHANGE vs IOUT
(VIN = VOUT + 1V, Output Voltage % Change
Refered to IOUT = 125mA at +25°C)
0.40
+25°C
0.20
+125°C
0
–0.20
–0.40
–55°C
–0.60
–0.2%
–0.4%
25
50
75
100
125
150
175 200
5mA < IOUT < 250mA
–0.5%
–0.6%
–0.80
0
25mA < IOUT < 250mA
–0.3%
–0.7%
–50
225 250
–25
0
25
LINE REGULATION
(Refered to VIN = VOUT + 1V at IOUT = 125mA)
75
100
125
LINE REGULATION vs TEMPERATURE
0
20
All Fixed Output
Voltage Versions
15
10
IOUT = 250mA
Output Voltage Change (%)
Output Voltage Change (mV)
50
Temperature (°C)
IOUT (mA)
IOUT = 5mA
5
IOUT = 125mA
0
–5
–10
–15
–0.05
–0.10
–0.20
–0.25
(VOUT + 0.4V) < VIN < 10V
IOUT = 250mA
–20
0
1
2
3
4
5
(VOUT + 1V) < VIN < 10V
–0.15
6
7
–0.30
–50
8
–25
0
25
50
75
100
125
Temperature (°C)
VIN – VOUT (V)
DC DROPOUT VOLTAGE vs TEMPERATURE
DC DROPOUT VOLTAGE vs IOUT
250
250
200
DC Dropout Voltage (mV)
DC Dropout Voltage (mV)
IOUT = 250mA
+125°C
150
+25°C
100
–55°C
50
50
100
150
200
250
100
50
–25
0
25
50
75
100
125
Temperature (°C)
IOUT (mA)
REG102
SBVS024E
150
0
–50
0
0
200
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5
TYPICAL CHARACTERISTICS (Cont.)
For all models, at TJ = +25°C and VENABLE = 1.8V, unless otherwise noted.
OUTPUT VOLTAGE DRIFT HISTOGRAM
OUTPUT VOLTAGE ACCURACY HISTOGRAM
30
18
16
Percentage of Units (%)
Percentage of Units (%)
25
14
12
10
8
6
4
20
15
10
5
2
0
0
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
90
95
100
1.0
0.8
0.6
0.4
0.2
0.0
–0.2
–0.4
–0.6
–0.8
–1.0
0
Error (%)
VOUT Drift (ppm/°C)
OUTPUT VOLTAGE vs TEMPERATURE
(Output Voltage % Change Refered
to IOUT = 125mA at +25°C)
GROUND PIN CURRENT, NOT ENABLED
vs TEMPERATURE
1µ
0.80
VENABLE = 0.5V
VIN = VOUT + 1V
0.40
100n
IOUT = 5mA
IOUT = 125mA
0.20
IGND (A)
Output Voltage Change (%)
0.60
0
–0.20
–0.40
IOUT = 250mA
10n
1n
–0.60
–0.80
–1.00
–50
–25
0
25
50
75
100
100p
–50
125
–25
0
750
700
725
VOUT = 5.0V
400
VOUT = 2.5V
IGND (µA)
IGND (µA)
VOUT = 3.3V
100
125
VOUT = 5V
IOUT = 250mA
675
VOUT = 3.3V
650
625
200
600
100
575
VOUT = 2.5V
550
0
0
25
50
75
100
125
150 175 200
–50
225 250
–25
0
25
50
75
100
125
Temperature (°C)
IOUT (mA)
6
75
700
500
300
50
GROUND PIN CURRENT vs TEMPERATURE
GROUND PIN CURRENT vs IOUT
800
600
25
Temperature (°C)
Temperature (°C)
REG102
www.ti.com
SBVS024E
TYPICAL CHARACTERISTICS (Cont.)
For all models, at TJ = +25°C and VENABLE = 1.8V, unless otherwise noted.
RIPPLE REJECTION vs FREQUENCY
RIPPLE REJECTION vs (VIN – VOUT)
80
30
IOUT = 2mA
25
IOUT = 2mA
COUT = 10µF
60
50
Ripple Rejection (dB)
Ripple Rejection (dB)
70
IOUT = 100mA
COUT = 10µF
IOUT = 100mA
40
30
20
COUT = 0µF
10
20
15
10
Frequency = 100kHz
COUT = 10µF
VOUT = 3.3V
IOUT = 100mA
5
0
0
10
100
1k
10k
100k
1M
10M
1.0
0.9
0.8
0.7
Frequency (Hz)
REG102-5.0
100
Noise Voltage (µVrms)
Noise Voltage (µVrms)
40
REG102-3.3
30
20
REG102-2.5
COUT = 0.01µF
10Hz < BW < 100kHz
0.1
0.2
0.1
0
REG102-5.0
90
REG102-3.3
80
70
60
50
REG102-2.5
40
COUT = 0µF
10Hz < BW < 100kHz
30
20
1
1
10
10
NOISE SPECTRAL DENSITY
1
COUT = 1µF
COUT = 0µF
eN (µV/√Hz)
IOUT = 100mA
CNR = 0µF
IOUT = 100mA
CNR = 0.01µF
1
COUT = 1µF
0.1
COUT = 0µF
COUT = 10µF
0.01
COUT = 10µF
0.01
10
100
1k
10k
100k
10
Frequency (Hz)
100
1k
10k
100k
Frequency (Hz)
REG102
SBVS024E
10k
1k
NOISE SPECTRAL DENSITY
10
0.1
100
CNR (pF)
COUT (µF)
eN (µV/√Hz)
0.3
110
50
10
0.4
RMS NOISE VOLTAGE vs CNR
RMS NOISE VOLTAGE vs COUT
0
0.5
VIN – VOUT (V)
60
10
0.6
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7
TYPICAL CHARACTERISTICS
(Cont.)
For all models, at TJ = +25°C and VENABLE = 1.8V, unless otherwise noted.
CURRENT LIMIT vs TEMPERATURE
CURRENT LIMIT FOLDBACK
3.5
450
3.0
400
VIN = VOUT + 1V
ICL = Current Limit
350
ICL
IOUT (mA)
2.0
1.5
1.0
250
ISC = Short-Circuit Current
200
ISC
0.5
150
0
50
100
150
200
250
300
350
400
100
–50
450
–25
0
25
50
100
Temperature (°C)
LOAD TRANSIENT RESPONSE
LINE TRANSIENT RESPONSE
REG102-3.3
VIN = 4.3V
200mV/div
COUT = 0µF
VOUT
COUT = 10µF
125
REG102-3.3
IOUT = 250mA
COUT = 0
VOUT
COUT = 10µF
VOUT
VOUT
IOUT
250mA
5.3V
VIN
4.3V
25mA
10µs/div
50µs/div
TURN-ON
TURN-OFF
1V/div
COUT = 10µF
RLOAD = 13Ω
REG102-3.3
VIN = VOUT + 1V
CNR = 0.01µF
VOUT
1V/div
COUT = 0µF
RLOAD = 13Ω
COUT = 10µF
RLOAD = 13Ω
COUT = 1.0µF
RLOAD = 13Ω
COUT = 0µF
RLOAD = 660Ω
VENABLE
1V/div
1V/div
COUT = 0µF
RLOAD = 660Ω
VOUT
VENABLE
REG102-3.3
250µs/div
8
75
Output Current (mA)
50mV/div
0
200mV/div
300
50mV/div
Output Voltage (V)
REG102-3.3
2.5
200µs/div
REG102
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SBVS024E
TYPICAL CHARACTERISTICS
(Cont.)
For all models, at TJ = +25°C and VENABLE = 1.8V, unless otherwise noted.
POWER UP/POWER DOWN
IENABLE vs VENABLE
10µ
VOUT = 3.0V
RLOAD = 12Ω
500mV/div
IENABLE (A)
1.0µ
100n
T = +25°C
T = +125°C
10n
T = –55°C
1n
6
7
8
9
1s/div
10
VENABLE (V)
ADJUST PIN CURRENT vs TEMPERATURE
RMS NOISE VOLTAGE vs CADJ
0.350
80
VOUT = 3.3V
0.300
COUT = 0.1µF
10Hz < frequency < 100kHz
70
0.250
IADJ (µA)
VN (rms)
60
50
40
0.200
0.150
0.100
30
0.050
0
20
10
200mV/div
100
1k
10k
100k
–50
25mA
50
75
100
LINE TRANSIENT-ADJUSTABLE VERSION
COUT = 0
VOUT
50mV/div
COUT = 10µF
COUT = 0
125
VOUT
COUT = 10µF
VOUT
VOUT
VIN = 4.3V
5.3V
VOUT = 3.3V
IOUT
REG102
SBVS024E
25
LOAD TRANSIENT-ADJUSTABLE VERSION
REG102–A
250mA
0
Temperature (°C)
50mV/div
200mV/div
–25
CADJ (pF)
www.ti.com
REG102–A
IOUT = 250mA
CFB = 0.01µF
VOUT = 3.3V
VIN
4.3V
9
BASIC OPERATION
The REG102 series of LDO (low dropout) linear regulators
offers a wide selection of fixed output voltage versions and
an adjustable output version as well. The REG102 belongs
to a family of new generation LDO regulators that use a
DMOS pass transistor to achieve ultra low-dropout performance and freedom from output capacitor constraints. Ground
pin current remains under 1mA over all line, load, and
temperature conditions. All versions have thermal and overcurrent protection, including foldback current limit.
The REG102 does not require an output capacitor for regulator
stability and is stable over most output currents and with almost
any value and type of output capacitor up to 10µF or more. For
applications where the regulator output current drops below
several milliamps, stability can be enhanced by adding a 1kΩ
to 2kΩ load resistor, using capacitance values smaller than
10µF, or keeping the effective series resistance greater than
0.05Ω including the capacitor ESR and parasitic resistance in
printed circuit board traces, solder joints, and sockets.
Enable
VIN
REG102
In
GND
0.1µF
VOUT
Out
NR
COUT
CNR
0.01µF
Optional
FIGURE 1. Fixed Voltage Nominal Circuit for the REG102.
the regulator from damage under all load conditions. A
characteristic of VOUT versus IOUT is given in Figure 3 and in
the Typical Characteristics section.
Although an input capacitor is not required, it is a good
standard analog design practice to connect a 0.1µF low ESR
capacitor across the input supply voltage. This is recommended to counteract reactive input sources and improve
ripple rejection by reducing input voltage ripple.
CURRENT LIMIT FOLDBACK
3.5
3
Output Voltage (V)
REG102-3.3
Figure 1 shows the basic circuit connections for the fixed
voltage models. Figure 2 gives the connections for the adjustable output version (REG102A) and example resistor values for
some commonly used output voltages. Values for other voltages can be calculated from the equation shown in Figure 2.
2.5
ICL
2
1.5
1
ISC
0.5
0
INTERNAL CURRENT LIMIT
0
The REG102 internal current limit has a typical value of
400mA. A foldback feature limits the short-circuit current to a
typical short-circuit value of 150mA, which helps to protect
50
100
150
200
250
300
350
400
450
Output Current (mA)
FIGURE 3. Foldback Current Limit of the REG102-3.3 at 25°C.
Enable
5
2
VIN
VOUT
1
REG102
4
0.1µF
IADJ
3 Gnd
R1
CFB
0.01µF
COUT
EXAMPLE RESISTOR VALUES
VOUT (V)
R1 (Ω)(1)
R2 (Ω)(1)
2.5
11.3k
1.13k
11.5k
1.15k
3.0
15.8k
1.58k
11.5k
1.15k
3.3
18.7k
1.87k
11.5k
1.15k
5.0
34.0k
3.40k
11.5k
1.15k
Load
Adj
R2
Optional
NOTE: (1) Resistors are standard 1% values.
Pin numbers for the SOT-223 package.
VOUT = (1 + R1/R2) • 1.26V
To reduce current through divider, increase resistor
values (see table at right).
As the impedance of the resistor divider increases,
IADJ (~200nA) may introduce an error.
CFB improves noise and transient response.
FIGURE 2. Adjustable Voltage Circuit for the REG102A.
10
REG102
www.ti.com
SBVS024E
ENABLE
OUTPUT NOISE
A precision bandgap reference is used to generate the
internal reference voltage, VREF. This reference is the dominant noise source within the REG102 and generates approximately 29µVrms in the 10Hz to 100kHz bandwidth at the
reference output. The regulator control loop gains up the
reference noise, so that the noise voltage of the regulator is
approximately given by:
VN = 29µVrms
V
R1 + R2
= 29µVrms • OUT
R2
VREF
(1)
As the value of VREF is 1.26V, this relationship reduces to:
VN = 23
µVrms
• VOUT
V
(2)
Connecting a capacitor, CNR, from the Noise Reduction (NR)
pin to ground forms a low-pass filter for the voltage reference. Adding CNR (as shown in Figure 4) forms a low-pass
filter for the voltage reference. For CNR = 10nF, the total noise
in the 10Hz to 100kHz bandwidth is reduced by approximately a factor of 2.8 for VOUT = 3.3V. This noise reduction
effect is shown in Figure 5 and as RMS Noise Voltage vs CNR
in the Typical Characteristcs section.
RMS NOISE VOLTAGE vs CNR
110
100
Noise Voltage (Vrms)
The Enable pin is active high and compatible with standard
TTL-CMOS levels. Inputs below 0.5V (max) turn the regulator off and all circuitry is disabled. Under this condition,
ground pin current drops to approximately 10nA. When not
used, the Enable pin can be connected to VIN. When a pullup resistor is used, and operation below 1.8V is required, use
pull-up resistor values below 50kΩ.
90
REG102-5.0
80
REG102-3.3
70
60
REG102-2.5
50
40
COUT = 0µF
10Hz < BW < 100kHz
30
20
0.1
10
100
1k
10k
CNR (pF)
FIGURE 5. Output Noise versus Noise Reduction Capacitor.
Noise can be further reduced by carefully choosing an output
capacitor, COUT. Best overall noise performance is achieved
with very low (< 0.22µF) or very high (> 2.2µF) values of COUT
(see the RMS Noise Voltage vs COUT typical characteristic).
The REG102 uses an internal charge pump to develop an
internal supply voltage sufficient to drive the gate of the
DMOS pass element above VIN. The charge-pump switching
noise (nominal switching frequency = 2MHz) is not measurable at the output of the regulator over most values of IOUT
and COUT.
The REG102 adjustable version does not have the noisereduction pin available; however, the adjust pin is the summing junction of the error amplifier. A capacitor, CFB, connected from the output to the adjust pin can reduce both the
output noise and the peak error from a load transient (see the
typical characteristics for output noise performance).
VIN
NR
(fixed output
versions only)
Low-Noise
Charge Pump
CNR
(optional)
VREF
(1.26V)
DMOS
Output
VOUT
Over-Current
Over Temp
Protection
Enable
R1
R2
Adj
(adjustable
versions)
REG102
NOTE: R1 and R2 are internal
on fixed output versions.
FIGURE 4. Block Diagram.
REG102
SBVS024E
www.ti.com
11
DROPOUT VOLTAGE
The REG102 uses an N-channel DMOS as the pass element.
When (VIN – VOUT) is less than the drop-out voltage (VDROP),
the DMOS pass device behaves like a resistor; therefore, for
low values of (VIN – VOUT), the regulator input-to-output
resistance is the RdsON of the DMOS pass element (typically
600mΩ). For static (DC) loads, the REG102 typically maintains regulation down to a (VIN – VOUT) voltage drop of 150mV
at full rated output current. In Figure 6, the bottom line (DC
dropout) shows the minimum VIN to VOUT voltage drop required to prevent dropout under DC load conditions.
For large step changes in load current, the REG102 requires
a larger voltage drop across it to avoid degraded transient
response. The boundary of this transient drop-out region is
shown as the top line in Figure 6 and values of VIN to VOUT
voltage drop above this line insure normal transient response.
DROPOUT VOLTAGE vs IOUT
350
Dropout Voltage (mV)
300
250
0mA to IOUT Transient
200
150
DC
100
50
0
0
50
100
150
200
250
IOUT (mA)
FIGURE 6. Transient and DC Dropout.
In the transient dropout region between DC and Transient,
transient response recovery time increases. The time required
to recover from a load transient is a function of both the
magnitude and rate of the step change in load current and the
available headroom VIN to VOUT voltage drop. Under worst-
12
case conditions (full-scale load change with (VIN – VOUT)
voltage drop close to DC dropout levels), the REG102 can
take several hundred microseconds to re-enter the specified
window of regulation.
TRANSIENT RESPONSE
The REG102 response to transient line and load conditions
improves at lower output voltages. The addition of a capacitor
(nominal value 0.47µF) from the output pin to ground can
improve the transient response. In the adjustable version, the
addition of a capacitor, CFB (nominal value 10nF), from the
output to the adjust pin can also improve the transient
response.
THERMAL PROTECTION
Power dissipated within the REG102 can cause the junction
temperature to rise. The REG102 has thermal shutdown
circuitry that protects the regulator from damage which disables the output when the junction temperature reaches
approximately 160°C, allowing the device to cool. When the
junction temperature cools to approximately 140°C, the output circuitry is again enabled. Depending on various conditions, the thermal protection circuit can cycle on and off. This
limits the dissipation of the regulator, but can have an
undesirable effect on the load.
Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate heat
sink. For reliable operation, junction temperature must be
limited to 125°C, maximum. To estimate the margin of safety
in a complete design (including heat sink), increase the
ambient temperature until the thermal protection is triggered;
use worst-case loads and signal conditions. For good reliability, thermal protection should trigger more than 35°C above
the maximum expected ambient condition of the application.
This produces a worst-case junction temperature of 125°C at
the highest expected ambient temperature and worst-case
load.
The internal protection circuitry of the REG102 is designed to
protect against overload conditions and is not intended to
replace proper heat sinking. Continuously running the REG102
into thermal shutdown will degrade reliability.
REG102
www.ti.com
SBVS024E
PD = (VIN – VOUT ) • IOUT
POWER DISSIPATION
The REG102 is available in three different package configurations. The ability to remove heat from the die is different for
each package type and, therefore, presents different considerations in the printed circuit-board layout. The PCB area
around the device that is free of other components moves the
heat from the device to the ambient air. Although it is difficult
to impossible to quantify all of the variables in a thermal
design of this type, performance data for several simplified
configurations are shown in Figure 7. In all cases, the PCB
copper area is bare copper (free of solder resist mask), not
solder plated, and are for 1-ounce copper. Using heavier
copper will increase the effectiveness in moving the heat
from the device. In those examples where there is copper on
both sides of the PCB, no connection has been provided
between the two sides. The addition of plated through holes
will improve the heat sink effectiveness.
Power dissipation depends on input voltage, load conditions,
and duty cycle and is equal to the product of the average
output current times the voltage across the output element,
VIN to VOUT voltage drop.
(3)
Power dissipation can be minimized by using the lowest
possible input voltage necessary to assure the required
output voltage.
REGULATOR MOUNTING
The tab of the SOT-223 package is electrically connected to
ground. For best thermal performance, this tab must be
soldered directly to a circuit-board copper area. Increasing
the copper area improves heat dissipation, as shown in
Figure 8.
Although the tab of the SOT-223 is electrical ground, it is not
intended to carry current. The copper pad that acts as a heat
sink should be isolated from the rest of the circuit to prevent
current flow through the device from the tab to the ground
pin. Solder pad footprint recommendations for the various
REG102 devices are presented in Application Bulletin Solder
Pad Recommendations for Surface-Mount Devices
(SBFA015), available from the Texas Instruments web site
(www.ti.com).
DEVICE DISSIPATION vs TEMPERATURE
Power Dissipation (Watts)
2.5
CONDITIONS
#1
#2
#3
#4
2
CONDITION
1
2
3
4
1.5
PACKAGE
SOT-223
SOT-223
SO-8
SOT-23
PCB AREA
4in2 Top Side Only
0.5in2 Top Side Only
—
—
THETA J-A
53°C/W
110°C/W
150°C/W
200°C/W
1
0.5
0
0
25
50
75
100
125
Ambient Temperature (°C)
FIGURE 7. Maximum Power Dissipation versus Ambient Temperature for the Various Packages and PCB Heat Sink Configurations.
THERMAL RESISTANCE vs PCB COPPER AREA
Thermal Resistance, θJA (°C/W)
180
Circuit-Board Copper Area
REG102
Surface-Mount Package
1 oz. copper
160
140
120
100
80
60
40
20
REG102
SOT-223 Surface-Mount Package
0
0
1
2
3
4
5
Copper Area (inches2)
FIGURE 8. Thermal Resistance versus PCB Area for the Five Lead SOT-223.
REG102
SBVS024E
www.ti.com
13
PACKAGE DRAWINGS
DBV (R-PDSO-G5)
PLASTIC SMALL-OUTLINE
0,50
0,30
0,95
5
0,20 M
4
1,70
1,50
1
0,15 NOM
3,00
2,60
3
Gage Plane
3,00
2,80
0,25
0° – 8°
0,55
0,35
Seating Plane
1,45
0,95
0,05 MIN
0,10
4073253-4/G 01/02
NOTES: A.
B.
C.
D.
14
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion.
Falls within JEDEC MO-178
REG102
www.ti.com
SBVS024E
PACKAGE DRAWINGS (Cont.)
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
8 PINS SHOWN
0.020 (0,51)
0.014 (0,35)
0.050 (1,27)
8
0.010 (0,25)
5
0.008 (0,20) NOM
0.244 (6,20)
0.228 (5,80)
0.157 (4,00)
0.150 (3,81)
Gage Plane
1
4
0.010 (0,25)
0°– 8°
A
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.010 (0,25)
0.004 (0,10)
0.069 (1,75) MAX
PINS **
0.004 (0,10)
8
14
16
A MAX
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
A MIN
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
DIM
4040047/E 09/01
NOTES: A.
B.
C.
D.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
Falls within JEDEC MS-012
REG102
SBVS024E
www.ti.com
15
PACKAGE DRAWINGS (Cont.)
DCQ (R-PDSO-G6)
B
PLASTIC SMALL-OUTLINE
0.258 (6,55)
0.254 (6,45) D
0.120 (3,05)
0.116 (2,95)
0.004 (0,10) M C B
A
Gage
Plane
H
6X
C
0.003 (0,08)
0.004 (0,10)
0.286 (7,26)
0.001 (0,02)
0.270 (6,86)
0.004 (0,10) M C A
0.045 (1,14)
0.036 (0,91)
0.140 (3,55)
0.136 (3,45)
D
4X
0.050(1,27)
0.010(0,25)
Seating
Plane
5X 0.020 (0,51)
E
F
0.016 (0,41)
0.004 (0,10) M C B
0.200(5,08)
0.013 (0,32)
0.009 (0,24)
0.071 (1,80)
MAX
F
0.036 (0,91)
0.034 (0,87)
0.065 (1,65)
0.061 (1,55)
0°–8°
4202109/A 03/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Controlling dimension in inches
D. Body length and width dimensions are determined at
the outermost extremes of the plastic body exclusive
of mold flash, tie bar burrs, gate burrs, and interlead
flash, but including any mismatch between the top and
the bottom of the plastic body.
E. Lead width dimension does not include dambar
protrusion.
F. Lead width and thickness dimensions apply to solder
plated leads.
G. Interlead flash allow 0.008 inch max.
H. Gate burr/protrusion max. 0.006 inch.
16
I. Datums A and B are to be determined at Datum H.
J. Package dimensions per JEDEC outline drawing TO–261,
issue B, dated Feb. 1999.
This variation is not yet included.
REG102
www.ti.com
SBVS024E
PACKAGE OPTION ADDENDUM
www.ti.com
8-Nov-2004
PACKAGING INFORMATION
ORDERABLE DEVICE
STATUS(1)
PACKAGE TYPE
PACKAGE DRAWING
PINS
PACKAGE QTY
REG102GA-2.5
ACTIVE
SOP
DCQ
6
78
REG102GA-2.5/2K5
ACTIVE
SOP
DCQ
6
2500
REG102GA-2.8
ACTIVE
SOP
DCQ
6
78
REG102GA-2.8/2K5
ACTIVE
SOP
DCQ
6
2500
REG102GA-2.85
ACTIVE
SOP
DCQ
6
78
REG102GA-2.85/2K5
ACTIVE
SOP
DCQ
6
2500
REG102GA-3
ACTIVE
SOP
DCQ
6
78
REG102GA-3.3
ACTIVE
SOP
DCQ
6
78
REG102GA-3.3/2K5
ACTIVE
SOP
DCQ
6
2500
REG102GA-3/2K5
ACTIVE
SOP
DCQ
6
2500
REG102GA-5
ACTIVE
SOP
DCQ
6
78
REG102GA-5/2K5
ACTIVE
SOP
DCQ
6
2500
REG102GA-A
NRND
SOP
DCQ
6
78
2500
REG102GA-A/2K5
NRND
SOP
DCQ
6
REG102NA-2.5/250
ACTIVE
SOP
DBV
5
250
REG102NA-2.5/3K
ACTIVE
SOP
DBV
5
3000
REG102NA-2.8/250
ACTIVE
SOP
DBV
5
250
3000
REG102NA-2.8/3K
ACTIVE
SOP
DBV
5
REG102NA-2.85/250
ACTIVE
SOP
DBV
5
250
REG102NA-2.85/3K
ACTIVE
SOP
DBV
5
3000
REG102NA-3.3/250
ACTIVE
SOP
DBV
5
250
REG102NA-3.3/3K
ACTIVE
SOP
DBV
5
3000
REG102NA-3/250
ACTIVE
SOP
DBV
5
250
3000
REG102NA-3/3K
ACTIVE
SOP
DBV
5
REG102NA-5/250
ACTIVE
SOP
DBV
5
250
REG102NA-5/3K
ACTIVE
SOP
DBV
5
3000
REG102NA-A/250
NRND
SOP
DBV
5
250
REG102NA-A/3K
NRND
SOP
DBV
5
3000
REG102UA-2.5
ACTIVE
SOIC
D
8
100
REG102UA-2.5/2K5
ACTIVE
SOIC
D
8
2500
REG102UA-2.8
ACTIVE
SOIC
D
8
100
REG102UA-2.8/2K5
ACTIVE
SOIC
D
8
2500
REG102UA-2.85
ACTIVE
SOIC
D
8
100
REG102UA-2.85/2K5
ACTIVE
SOIC
D
8
2500
REG102UA-3
ACTIVE
SOIC
D
8
100
REG102UA-3.3
ACTIVE
SOIC
D
8
100
REG102UA-3.3/2K5
ACTIVE
SOIC
D
8
2500
REG102UA-3/2K5
ACTIVE
SOIC
D
8
2500
REG102UA-5
ACTIVE
SOIC
D
8
100
REG102UA-5/2K5
ACTIVE
SOIC
D
8
2500
REG102UA-A
NRND
SOIC
D
8
100
REG102UA-A/2K5
NRND
SOIC
D
8
2500
PACKAGE OPTION ADDENDUM
www.ti.com
8-Nov-2004
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
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