TI TPS54373PWP

Typical Size
6,4 mm X 6,6 mm
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SLVS455A − JANUARY 2003 − REVISED JUNE 2003
FEATURES
D 60-mΩ MOSFET Switches for High Efficiency
D
D
D
D
D
D
at 3-A Continuous Output Source or Sink
Current
Disabled Current Sinking During Start-Up
Adjustable Output Voltage Down to 0.9 V
With 1.0% Accuracy
Wide PWM Frequency:
Fixed 350 kHz, 550 kHz or
Adjustable 280 kHz to 700 kHz
Synchronizable to 700 kHz
Load Protected by Peak Current Limit and
Thermal Shutdown
Integrated Solution Reduces Board Area and
Component Count
APPLICATIONS
D Low-Voltage, High-Density Distributed Power
D
D
D
Systems
Point of Load Regulation for High
Performance DSPs, FPGAs, ASICs and
Microprocessors
Broadband, Networking and Optical
Communications Infrastructure
Power PC Series Processors
DESCRIPTION
As a member of the SWIFT family of dc/dc regulators,
the TPS54373 low-input voltage high-output current
synchronous buck PWM converter integrates all
required active components. Included on the substrate
with the listed features are a true, high performance,
voltage error amplifier that enables maximum
performance and flexibility in choosing the output filter
L and C components; an under-voltage-lockout circuit
to prevent start-up until the input voltage reaches 3 V;
an internally or externally set slow-start circuit to limit
in-rush currents; and a power good output useful for
processor/logic reset, fault signaling, and supply
sequencing.
For reliable power up in output precharge applications,
the TPS54373 is designed to only source current during
start-up.
The TPS54373 is available in a thermally enhanced
20-pin TSSOP (PWP) PowerPAD package, which
eliminates bulky heatsinks. TI provides evaluation
modules and the SWIFT designer software tool to aid
in quickly achieving high-performance power supply
designs to meet aggressive equipment development
cycles.
START UP WAVEFORM
TYPICAL APPLICATION
*
*
I/O Supply
RL = 1 Ω
Core Supply
VIN
PH
TPS54373
BOOT
VBIAS VSENSE
AGND COMP
VI = 3.3 V
1 V/div
PGND
VO = 1.8 V
* Optional
5.0 ms/div
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD and SWIFT are trademarks of Texas Instruments.
!"#$ % &'!!($ #% )'*+&#$ ,#$(- !,'&$%
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Copyright  2003, Texas Instruments Incorporated
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
TA
−40°C to 85°C
OUTPUT VOLTAGE
Adjustable down to 0.9 V
PACKAGE
Plastic HTSSOP (PWP)(1)
PART NUMBER
TPS54373PWP
(1) The PWP package is also available taped and reeled. Add an R suffix to the device type (i.e., TPS54373PWPR). See the application section of
the data sheet for PowerPAD drawing and layout information.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
TPS54373
Input voltage range, VI
VIN, SS/ENA, SYNC
−0.3 V to 7 V
RT
−0.3 V to 6 V
VSENSE
−0.3 V to 4V
BOOT
Output voltage range, VO
Source current, IO
−0.3 V to 17 V
VBIAS, COMP, PWRGD
−0.3 V to 7 V
PH
−0.6 V to 10 V
PH
Internally limited
COMP, VBIAS
6 mA
PH
Sink current, IS
Voltage differential
6A
COMP
6 mA
SS/ENA, PWRGD
10 mA
±0.3 V
AGND to PGND
Operating virtual junction temperature range, TJ
−40°C to 125°C
Storage temperature, Tstg
−65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
300°C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
MIN
Input voltage, VI
Operating junction temperature, TJ
NOM
MAX
UNIT
3
6
V
−40
125
°C
DISSIPATION RATINGS(1)(2)
PACKAGE
THERMAL IMPEDANCE
JUNCTION-TO-AMBIENT
TA = 25°C
POWER RATING
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
20 Pin PWP with solder
26 °C/W
3.85 W(3)
2.12 W
1.54 W
20 Pin PWP without solder
57.5 °C/W
1.73 W
0.96 W
0.69 W
(1) For more information on the PWP package, refer to TI technical brief, literature number SLMA002.
(2) Test board conditions:
1. 3” x 3”, 2 layers, thickness: 0.062”
2. 1.5 oz. copper traces located on the top of the PCB
3. 1.5 oz. copper ground plane on the bottom of the PCB
4. 10 thermal vias (see “Recommended Land Pattern” in applications section of this data sheet)
(3) Maximum power dissipation may be limited by over current protection.
2
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SLVS455A − JANUARY 2003 − REVISED JUNE 2003
ELECTRICAL CHARACTERISTICS
TJ = −40°C to 125°C, VI = 3 V to 6 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE, VIN
Input voltage range, VIN
I(Q)
Quiescent current
3.0
6.0
fs = 350 kHz, SYNC ≤ 0.8 V, RT open,
PH pin open
6.2
9.6
fs = 550 kHz, SYNC ≥ 2.5 V, RT open,
PH pin open
8.4
12.8
1
1.4
2.95
3.0
Shutdown, SS/ENA = 0 V
V
mA
UNDER VOLTAGE LOCK OUT
Start threshold voltage, UVLO
V
Stop threshold voltage, UVLO
2.70
2.80
V
Hysteresis voltage, UVLO
0.14
0.16
V
2.5
µs
Rising and falling edge deglitch, UVLO(1)
BIAS VOLTAGE
Output voltage, VBIAS
I(VBIAS) = 0
2.70
2.80
Output current, VBIAS (2)
2.90
V
100
µA
CUMULATIVE REFERENCE
Vref
Accuracy
REGULATION
Line regulation(1)(3)
Load regulation(1)(3)
0.882
0.891
0.900
IL = 1.5 A,fs = 350 kHz, TJ = 85°C
IL = 1.5 A,fs = 550 kHz, TJ = 85°C
IL = 0 A to 3 A, fs = 350 kHz, TJ = 85°C
0.07
IL = 0 A to 3 A, fs = 550 kHz, TJ = 85°C
0.03
0.07
0.03
V
%/V
%/A
OSCILLATOR
Internally set—free running frequency
Externally set—free running frequency range
High level threshold, SYNC
SYNC ≤ 0.8 V,
RT open
280
350
420
SYNC ≥ 2.5 V,
RT open
440
550
660
RT = 180 kΩ (1% resistor to AGND)(1)
252
280
308
RT = 100 kΩ (1% resistor to AGND)
RT = 68 kΩ (1% resistor to AGND)(1)
460
500
540
663
700
762
2.5
0.8
50
Ramp amplitude (peak-to-peak)(1)
Minimum controllable on time(1)
Maximum duty cycle
V
ns
330
Ramp valley(1)
kHz
V
Low level threshold, SYNC
Pulse duration, external synchronization, SYNC(1)
Frequency range, SYNC(1)
kHz
700
kHz
0.75
V
1
V
200
ns
90%
(1) Specified by design
(2) Static resistive loads only
(3) Specified by the circuit used in Figure 10
3
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ELECTRICAL CHARACTERISTICS (continued)
TJ = −40°C to 125°C, VI = 3 V to 6 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
90
110
3
5
MAX
UNIT
ERROR AMPLIFIER
Error amplifier open loop voltage gain
1 kΩ COMP to AGND(1)
Error amplifier unity gain bandwidth
Error amplifier common mode input voltage range
Parallel 10 kΩ, 160 pF COMP to AGND(1)
Powered by internal LDO(1)
Input bias current, VSENSE
VSENSE = Vref
Output voltage slew rate (symmetric), COMP(1)
0
VBIAS
60
1.0
dB
MHz
250
1.4
V
nA
V/µs
PWM COMPARATOR
PWM comparator propagation delay time,
PWM comparator input to PH pin (excluding
deadtime)
10-mV overdrive(1)
70
85
ns
1.20
1.40
V
SLOW-START/ENABLE
Enable threshold voltage, SS/ENA
0.82
Enable hysteresis voltage, SS/ENA
Falling edge deglitch, SS/ENA(1)
0.03
V
µs
2.5
Internal slow-start time
Charge current, SS/ENA
SS/ENA = 0 V
Discharge current, SS/ENA
SS/ENA = 0.2 V, VI = 2.7 V
2.6
3.35
4.1
ms
3
5
8
µA
1.5
2.3
4.0
mA
POWER GOOD
Power good threshold voltage
VSENSE falling
90
Power good hysteresis voltage(1)
Power good falling edge deglitch(1)
Output saturation voltage, PWRGD
Leakage current, PWRGD
I(sink) = 2.5 mA
VI = 5.5 V
3
%Vref
%Vref
35
µs
0.18
0.3
V
1
µA
CURRENT LIMIT
Current limit trip point
VI = 3 V Output shorted(1)
VI = 6 V Output shorted(1)
4
6.5
4.5
7.5
Current limit leading edge blanking time(1)
Current limit total response time(1)
A
100
ns
200
ns
THERMAL SHUTDOWN
Thermal shutdown trip point(1)
Thermal shutdown hysteresis(1)
135
150
165
°C
°C
10
OUTPUT POWER MOSFETS
rDS(on)
Power MOSFET switches
VI = 6 V(4)
VI = 3 V(4)
(1) Specified by design
(2) Static resistive loads only
(3) Specified by the circuit used in Figure 10
(4) Matched MOSFETs low-side rDS(on) production tested, high-side rDS(on) specified by design
4
59
88
85
136
mΩ
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PWP PACKAGE
(TOP VIEW)
AGND
VSENSE
COMP
PWRGD
BOOT
PH
PH
PH
PH
PH
1
2
3
4
5
6
7
8
9
10
20
19
18
17
THERMAL 16
PAD
15
14
13
12
11
RT
SYNC
SS/ENA
VBIAS
VIN
VIN
VIN
PGND
PGND
PGND
TERMINAL FUNCTIONS
TERMINAL
NAME
NO.
DESCRIPTION
AGND
1
Analog ground. Return for compensation network/output divider, slow-start capacitor, VBIAS capacitor, RT resistor and
SYNC pin. Connect PowerPAD to AGND.
BOOT
5
Bootstrap output. 0.022-µF to 0.1-µF low-ESR capacitor connected from BOOT to PH generates floating drive for the
high-side FET driver.
COMP
3
Error amplifier output. Connect frequency compensation network from COMP to VSENSE
PGND
11−13
Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large copper areas
to the input and output supply returns, and negative terminals of the input and output capacitors. A single point connection
to AGND is recommended.
PH
6−10
Phase output. Junction of the internal high-side and low-side power MOSFETs, and output inductor.
PWRGD
4
Power good open drain output. High when VSENSE ≥ 90% Vref, otherwise PWRGD is low. Note that output is low when
SS/ENA is low, or the internal shutdown signal is active.
RT
20
Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency. When using the
SYNC pin, set the RT value for a frequency at or slightly lower than the external oscillator frequency.
SS/ENA
18
Slow-start/enable input/output. Dual function pin which provides logic input to enable/disable device operation and
capacitor input to externally set the start-up time.
SYNC
19
Synchronization input. Dual function pin which provides logic input to synchronize to an external oscillator or pin select
between two internally set switching frequencies. When used to synchronize to an external signal, a resistor must be
connected to the RT pin.
VBIAS
17
Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND pin with a high
quality, low-ESR 0.1-µF to 1.0-µF ceramic capacitor.
14−16
Input supply for the power MOSFET switches and internal bias regulator. Bypass VIN pins to PGND pins close to device
package with a high quality, low-ESR 10-µF ceramic capacitor.
VIN
VSENSE
2
Error amplifier inverting input. Connect to output voltage through compensation network/output divider.
5
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SLVS455A − JANUARY 2003 − REVISED JUNE 2003
INTERNAL BLOCK DIAGRAM
VBIAS
AGND
VIN
Enable
Comparator
SS/ENA
Falling
Edge
Deglitch
1.2 V
Hysteresis: 0.03 V
2.5 µs
VIN UVLO
Comparator
VIN
2.95 V
Hysteresis: 0.16
V
ILIM
Comparator
Thermal
Shutdown
150°C
100 ns
SHUTDOWN
BOOT
2.5 µs
60 mΩ
Start-Up
Driver
Suppression
SS_DIS
PH
+
−
R Q
Error
Amplifier
Reference
VREF = 0.891 V
VIN
Leading
Edge
Blanking
Falling
and
Rising
Edge
Deglitch
Internal/External
Slow-start
(Internal Slow-Start Time = 3.35 ms)
REG
VBIAS
SHUTDOWN
S
PWM
Comparator
LOUT
CO
Adaptive Dead-Time
and
Control Logic
VIN
60 mΩ
PGND
OSC
Powergood
Comparator
PWRGD
VSENSE
Falling
Edge
Deglitch
0.90 Vref
TPS54373
Hysteresis: 0.03 Vref
VSENSE
6
COMP
RT
SYNC
SHUTDOWN
35 µs
VO
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SLVS455A − JANUARY 2003 − REVISED JUNE 2003
TYPICAL CHARACTERISTICS
DRAIN-SOURCE ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
100
IO = 3 A
80
60
40
20
VI = 5 V
0
25
85
IO = 3 A
80
60
40
20
0
−40
0
−40
125
TJ − Junction Temperature − °C
0
25
125
600
RT = 100 k
500
400
RT = 180 k
300
0.893
0.891
0.889
0.887
−40
−80
−100
−120
40
Gain
20
−140
−160
0
−180
−20
−200
10 k 100 k 1 M 10 M
0
10
100
1k
f − Frequency − Hz
Figure 7
Internal Slow-Start Time − ms
−20
−60
60
0.8910
0.8890
f = 350 kHz
0.8870
0
25
85
3
125
4
5
VI − Input Voltage − V
6
Figure 6
INTERNAL SLOW-START TIME
vs
JUNCTION TEMPERATURE
Phase − Degrees
RL= 10 kΩ,
CL = 160 pF,
TA = 25°C
125
0.8930
Figure 5
0
140
85
TA = 85°C
TJ − Junction Temperature − °C
ERROR AMPLIFIER
OPEN LOOP RESPONSE
25
0.8850
0.885
−40
125
Figure 4
Phase
0
0.8950
TJ − Junction Temperature − °C
80
250
−40
DEVICE POWER LOSSES
vs
LOAD CURRENT
3.80
2.25
3.65
2
Device Power Losses − W
85
100
350
OUTPUT VOLTAGE REGULATION
vs
INPUT VOLTAGE
VO − Output Voltage Regulation − V
Vref − Voltage Reference − V
700
120
SYNC ≤ 0.8 V
Figure 3
0.895
25
450
TJ − Junction Temperature − °C
RT = 68 k
0
SYNC ≥ 2.5 V
550
VOLTAGE REFERENCE
vs
JUNCTION TEMPERATURE
800
200
−40
650
Figure 2
EXTERNALLY SET OSCILLATOR
FREQUENCY
vs
JUNCTION TEMPERATURE
f − Externally Set Oscillator Frequency − kHz
85
750
TJ − Junction Temperature − °C
Figure 1
Gain − dB
f − Internally Set Oscillator Frequency − kHz
100
Drain-Source On-State Resistance − Ω
Drain-Source On-State Resistance − Ω
120
VI = 3.3 V
INTERNALLY SET OSCILLATOR
FREQUENCY
vs
JUNCTION TEMPERATURE
DRAIN-SOURCE ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
3.50
3.35
3.20
3.05
TJ − 125°C
fs = 700 kHz
1.75
1.5
VI = 3.3 V
1.25
1
VI = 5 V
0.75
0.5
2.90
0.25
2.75
−40
0
25
85
TJ − Junction Temperature − °C
Figure 8
125
0
0
1
2
3
IL − Load Current − A
4
Figure 9
7
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APPLICATION INFORMATION
Figure 10 shows the schematic diagram for a typical
TPS54373 application. The TPS54373 (U1) can provide
up to 3 A of output current at a nominal output voltage of
0.9 V to 3.3 V, and for this application, the output voltage
is set at 2.5 V and the input voltage is 3.3 V. For proper
operation, the PowerPAD underneath the integrated
circuit TPS54373 must be soldered properly to the
printed-circuit board.
U1
TPS54373
R6
20
RT
71.5 kΩ
VIN
VIN
19
SYNCH
C6
18
0.047 µF
C3
17
1 µF
10 kΩ
R5
4
VIN
R1
C1
1000 pF
R2
4.87
kΩ
C2
3
C4
C12
10 µF
10 µF
VIN
3.3 V
PWRGD
PH
COMP
PH
PH
100 pF
PH
2
14
C10
VBIAS
2200 pF
487 Ω
15
SS/ENA
PH
R3
10 kΩ
VIN
16
VSENSE BOOT
10
9
8
7
6
1 A, 200 V
D1
C9
5
0.047 µF
R4
9.76 kΩ
PGND
1
AGND
PGND
13
12
1 A, 200 V
D2
11
PGND
PwrPad
VOUT
1.8 V
R7
C13
C5
C7
C8
0.1 µF
22 µF
22 µF
22 µF
L1
1.0 µH
2.4 Ω
C11
3300 pF
Figure 10. Application Circuit
COMPONENT SELECTION
The values for the components used in this design
example are selected for low output ripple and small PCB
area. Ceramic capacitors are utilized in the output filter
circuit. A small size, small value output inductor is also
used. Compensation network components are chosen to
maximize closed loop bandwidth and provide good
transient response characteristics. Additional design
information is available at www.ti.com.
INPUT VOLTAGE
The input voltage is a nominal 3.3 VDC. The input filter
(C12) is a 10-µF ceramic capacitor (Taiyo Yuden). C10,
also a 10-µF ceramic capacitor (Taiyo Yuden) that
provides high frequency decoupling of the TPS54373 from
8
the input supply, must be located as close as possible to
the device. Ripple current is carried in both C10 and C12,
and the return path to PGND should avoid the current
circulating in the output capacitors C5, C7, C8 and C13.
FEEDBACK CIRCUIT
The values for these components are selected to provide
fast transient response times. R1, R2, R3, R4, C1, C2, and
C4 forms the loop-compensation network for the circuit.
For this design, a Type 3 topology is used. The transfer
function of the feedback network is chosen to provide
maximum closed loop gain available with open loop
characteristics of the internal error amplifier. Closed loop
crossover frequency is typically between 80 kHz at 3.3 V
input.
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SLVS455A − JANUARY 2003 − REVISED JUNE 2003
OPERATING FREQUENCY
In the application circuit, the RT pin is grounded through a
71.5-kΩ resistor (R6) to select the operating frequency of
700 kHz. To set a different frequency, place a 68-kΩ to
180-kΩ resistor between RT (pin 28) and analog ground or
leave RT floating to select the default of 350 kHz. The
resistance can be approximated using the following
equation:
R+
500 kHz
Switching Frequency
100 [kW]
(1)
OUTPUT FILTER
The output filter is composed of a 0.65-µH inductor (L1)
and 3 x 22-µF capacitors (C5, C7 and C8). The inductor is
a low dc resistance (0.010 Ω) type, Vishay
IHLP-2525CZ-01 1.0 µH. The capacitors used are 22-µF,
6.3-V ceramic types with X5R dielectric. An additional high
frequency bypass capacitor, C13 is also used.
PRECHARGE CIRCUIT
VIN precharges the output of the application circuit
through series diodes (D1 and D2) during start-up. As
the input voltage increases at start-up, the output is
precharged to VIN minus the forward bias voltage of the
two diodes. When the internal reference has ramped up
to a value greater than the voltage fed back to the
VSENSE pin, the output of the internal error amplifier
begins to increase. When this output reaches the
maximum ramp amplitude, the output of the PWM
comparator reaches 100 percent duty cycle and the
internal logic enables the high-side FET driver and
switching begins. The output tracks the internal
reference until the preset output voltage is reached.
Under no circumstances should the precharge voltage
be allowed to increase above the preset output value.
GROUNDING AND POWERPAD LAYOUT
The TPS54373 has two internal grounds (analog and
power). Inside the TPS54373, the analog ground ties to all
of the noise sensitive signals, while the power ground ties
to the noisier power signals. The PowerPAD must be tied
directly to AGND. Noise injected between the two grounds
can degrade the performance of the TPS54373,
particularly at higher output currents. However, ground
noise on an analog ground plane can also cause problems
with some of the control and bias signals. For these
reasons, separate analog and power ground areas are
recommended. The analog ground area should be tied to
the power ground area directly at the IC to reduce noise
between the two grounds. The only components that
should tie directly to the power ground area are the input
capacitor, the output capacitor, the input voltage
decoupling capacitor, and the PGND pins of the
TPS54373. The power ground areas as well as the
PowerPAD mounting area should be tied to any internal
ground planes using multiple vias. The layout of the
TPS54373 evaluation module is representative of a
recommended layout for a 2-layer board. Documentation
for the TPS54373 evaluation module can be found on the
Texas Instruments web site under the TPS54373 product
folder.
LAYOUT CONSIDERATIONS FOR THERMAL
PERFORMANCE
For operation at full rated load current, the analog ground
plane must provide adequate heat dissipating area. A 3
inch by 3 inch plane of 1 ounce copper is recommended,
though not mandatory, depending on ambient temperature
and airflow. Most applications have larger areas of internal
ground plane available, and the PowerPAD should be
connected to the largest area available. Additional areas
on the top or bottom layers also help dissipate heat, and
any area available should be used when 3 A or greater
operation is desired. Connection from the exposed area of
the PowerPAD to the analog ground plane layer should be
made using 0.013 inch diameter vias to avoid solder
wicking through the vias. Six vias should be in the
PowerPAD area with four additional vias located under the
device package. The size of the vias under the package,
but not in the exposed thermal pad area, can be increased
to 0.018. Additional vias beyond the ten recommended
that enhance thermal performance should be included in
areas not under the device package.
9
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SLVS455A − JANUARY 2003 − REVISED JUNE 2003
Minimum Recommended Thermal Vias: 6 × .013 dia.
Inside Powerpad Area 4 × .018 dia. Under Device as Shown.
Additional .018 dia. Vias May be Used if Top Side Analog
Ground Area is Extended.
6 PL ∅ 0.0130
4 PL ∅ 0.0180
Connect Pin 1 to Analog Ground Plane
in This Area for Optimum Performance
ÓÓÓ
ÓÓÓ
ÓÓÓ
ÓÓÓ
ÓÓÓ
ÓÓÓ
0.0227
0.0600
0.2560 0.2454
0.0400
0.0400
0.0600
Minimum Recommended Top
Side Analog Ground Area
0.0150
0.06
0.1010
0.0256
0.1700
0.1340
0.0620
0.0400
Minimum Recommended Exposed
Copper Area For Powerpad. 5mm
Stencils may Require 10 Percent
Larger Area
Figure 11. Recommended Land Pattern for 20-Pin PWP PowerPAD
PERFORMANCE GRAPHS
Data shown is for the circuit in Figure 10 with precharge disabled (D1 and D2 removed) except for slow-start timing
of Figure 19. All data is for VI = 3.3 V, VO = 2.5 V, fs = 700 kHz and TA = 25°C, unless otherwise specified.
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
EFFICIENCY
vs
OUTPUT CURRENT
100
OUTPUT VOLTAGE
vs
INPUT VOLTAGE
1.83
1.83
1.82
1.82
Efficiency − %
VO − Output Voltage − V
VI = 3.3 V, VO = 2.5 V
90
85
80
VI = 5 V, VO = 2.5 V
75
70
65
60
VO − Output Voltage − V
95
1.81
VI = 3.3 V
1.8
1.79
VI = 5 V
1.78
1.81
IO = 0 A
1.8
1.79
IO = 1.5 A
IO = 3 A
1.78
55
1.77
50
0
0.5
1
1.5
2
2.5
IO − Output Current − A
Figure 12
10
3
3.5
1.77
0
0.5
1
1.5
2
2.5
IO − Output Current − A
Figure 13
3
3.5
3
3.5
4
4.5
5
VI − Input Voltage − V
Figure 14
5.5
6
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SLVS455A − JANUARY 2003 − REVISED JUNE 2003
AMBIENT TEMPERATURE
vs
LOAD CURRENT
LOOP RESPONSE
150
40
120
Phase
Gain − dB
30
90
20
60
Gain
10
30
0
0
115
95
85
55
−60
−30
−90
35
−120
1M
25
10 k
100 k
Safe Operating Area(1)
65
−30
1k
VI = 3.3 V
75
−20
100
VI = 5 V
105
−10
−40
Output Ripple Voltage − 10 mV/div
50
OUTPUT RIPPLE VOLTAGE
125
T A − Ambient Temperature − ° C
180
Phase − Degrees
60
45
0
f − Frequency − Hz
1
2
3
IL − Load Current − A
Time − 1 µs/div
4
Figure 16
Figure 15
(1) Safe operating area is applicable to the test board conditions in the Dissipation Ratings
LOAD TRANSIENT RESPONSE
Figure 17
SLOW-START TIMING
I = 0.75 A to 2.25 A
RL = 1 Ω
1 A/div
1 V/div
20 mV/div
VI = 3.3 V
VO = 1.8 V
1.0 µs/div
5.0 ms/div
Figure 18
Figure 19
DETAILED DESCRIPTION
DISABLED SINKING DURING START-UP
(DSDS)
The DSDS feature enables minimal voltage drooping of
output precharge capacitors at start-up. The TPS54373 is
designed to disable the low-side MOSFET to prevent
sinking current from a precharge output capacitor during
start-up. Once the high-side MOSFET has been turned on
to the maximum duty cycle limit, the low-side MOSFET is
allowed to switch. Once the maximum duty cycle condition
is met, the converter functions as a sourcing converter until
the SS/ENA is pulled low.
UNDERVOLTAGE LOCK OUT (UVLO)
The TPS54373 incorporates an under voltage lockout
circuit to keep the device disabled when the input voltage
(VIN) is insufficient. During power up, internal circuits are
held inactive until VIN exceeds the nominal UVLO
threshold voltage of 2.95 V. Once the UVLO start threshold
is reached, device start-up begins. The device operates
until VIN falls below the nominal UVLO stop threshold of
2.8 V. Hysteresis in the UVLO comparator and a 2.5-µs
rising and falling edge deglitch circuit reduce the likelihood
of shutting the device down due to noise on VIN.
SLOW-START/ENABLE (SS/ENA)
The slow-start/enable pin provides two functions. First, the
pin acts as an enable (shutdown) control by keeping the
device turned off until the voltage exceeds the start
threshold voltage of approximately 1.2 V. When SS/ENA
exceeds the enable threshold, device start-up begins. The
reference voltage fed to the error amplifier is linearly
ramped up from 0 V to 0.891 V in 3.35 ms. Similarly, the
converter output voltage reaches regulation in
approximately 3.35 ms. Voltage hysteresis and a 2.5-µs
falling edge deglitch circuit reduce the likelihood of
triggering the enable due to noise.
The second function of the SS/ENA pin provides an
external means of extending the slow-start time with a
low-value capacitor connected between SS/ENA and
AGND.
Adding a capacitor to the SS/ENA pin has two effects on
start-up. First, a delay occurs between release of the
SS/ENA pin and start-up of the output. The delay is
11
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SLVS455A − JANUARY 2003 − REVISED JUNE 2003
proportional to the slow-start capacitor value and lasts
until the SS/ENA pin reaches the enable threshold. The
start-up delay is approximately:
t +C
d
(SS)
(2)
1.2 V
5 mA
Second, as the output becomes active, a brief ramp-up at
the internal slow-start rate may be observed before the
externally set slow-start rate takes control and the output
rises at a rate proportional to the slow-start capacitor. The
slow-start time set by the capacitor is approximately:
t
(SS)
+C
(SS)
(3)
0.7 V
5 mA
The actual slow-start time is likely to be less than the above
approximation due to the brief ramp-up at the internal rate.
The low side MOSFET is off during the slow-start
sequence.
External synchronization of the PWM ramp is possible
over the frequency range of 330 kHz to 700 kHz by driving
a synchronization signal into SYNC and connecting a
resistor from RT to AGND. Choose a resistor between the
RT and AGND which sets the free running frequency to
80% of the synchronization signal. The following table
summarizes the frequency selection configurations:
SWITCHING
FREQUENCY
SYNC PIN
RT PIN
350 kHz, internally
set
Float or AGND
Float
550 kHz, internally
set
≥ 2.5 V
Float
Externally set 280
kHz to 700 kHz
Float
R = 180 kΩ to 68 kΩ
Externally
synchronized
frequency
Synchronization
signal
R = RT value for 80%
of external synchronization frequency
VBIAS REGULATOR (VBIAS)
ERROR AMPLIFIER
The VBIAS regulator provides internal analog and digital
blocks with a stable supply voltage over variations in
junction temperature and input voltage. A high quality,
low-ESR, ceramic bypass capacitor is required on the
VBIAS pin. X7R or X5R grade dielectrics are
recommended because their values are more stable over
temperature. The bypass capacitor must be placed close
to the VBIAS pin and returned to AGND.
The high performance, wide bandwidth, voltage error
amplifier sets the TPS54373 apart from most dc/dc
converters. The user is given the flexibility to use a wide
range of output L and C filter components to suit the
particular application needs. Type 2 or type 3
compensation can be employed using external
compensation components.
External loading on VBIAS is allowed, with the caution that
internal circuits require a minimum VBIAS of 2.70 V, and
external loads on VBIAS with ac or digital switching noise
may degrade performance. The VBIAS pin may be useful
as a reference voltage for external circuits.
Signals from the error amplifier output, oscillator, and
current limit circuit are processed by the PWM control
logic. Referring to the internal block diagram, the control
logic includes the PWM comparator, OR gate, PWM latch,
and portions of the adaptive dead-time and control logic
block. During steady-state operation below the current
limit threshold, the PWM comparator output and oscillator
pulse train alternately reset and set the PWM latch. Once
the PWM latch is reset, the low-side FET remains on for a
minimum duration set by the oscillator pulse width. During
this period, the PWM ramp discharges rapidly to its valley
voltage. When the ramp begins to charge back up, the
low-side FET turns off and high-side FET turns on. As the
PWM ramp voltage exceeds the error amplifier output
voltage, the PWM comparator resets the latch, thus
turning off the high-side FET and turning on the low-side
FET. The low-side FET remains on until the next oscillator
pulse discharges the PWM ramp.
During transient conditions, the error amplifier output
could be below the PWM ramp valley voltage or above the
PWM peak voltage. If the error amplifier is high, the PWM
latch is never reset, and the high-side FET remains on until
the oscillator pulse signals the control logic to turn the
high-side FET off and the low-side FET on. The device
operates at its maximum duty cycle until the output voltage
rises to the regulation set-point, setting VSENSE to
approximately the same voltage as VREF. If the error
amplifier output is low, the PWM latch is continually reset
VOLTAGE REFERENCE
The voltage reference system produces a precise Vref
signal by scaling the output of a temperature stable
bandgap circuit. During manufacture, the bandgap and
scaling circuits are trimmed to produce 0.891 V at the
output of the error amplifier, with the amplifier connected
as a voltage follower. The trim procedure adds to the high
precision regulation of the TPS54373, since it cancels
offset errors in the scale and error amplifier circuits.
OSCILLATOR AND PWM RAMP
The oscillator frequency can be set to internally fixed
values of 350 kHz or 550 kHz using the SYNC pin as a
static digital input. If a different frequency of operation is
required for the application, the oscillator frequency can be
externally adjusted from 280 to 700 kHz by connecting a
resistor between the RT pin and AGND and floating the
SYNC pin. The switching frequency is approximated by
the following equation, where R is the resistance from RT
to AGND:
Switching Frequency + 100 kW
R
12
500 [kHz]
(4)
PWM CONTROL
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SLVS455A − JANUARY 2003 − REVISED JUNE 2003
and the high-side FET does not turn on. The low-side FET
remains on until the VSENSE voltage decreases to a
range that allows the PWM comparator to change states.
The TPS54373 is capable of sinking current continuously
until the output reaches the regulation set-point.
If the current limit comparator trips for longer than 100 ns,
the PWM latch resets before the PWM ramp exceeds the
error amplifier output. The high-side FET turns off and
low-side FET turns on to decrease the energy in the output
inductor and consequently the output current. This
process is repeated each cycle in which the current limit
comparator is tripped.
DEAD-TIME CONTROL AND MOSFET
DRIVERS
Adaptive dead-time control prevents shoot-through
current from flowing in both N-channel power MOSFETs
during the switching transitions by actively controlling the
turnon times of the MOSFET drivers. The high-side driver
does not turn on until the voltage at the gate of the low-side
FET is below 2 V. While the low-side driver does not turn
on until the voltage at the gate of the high-side MOSFET
is below 2 V.
The high-side and low-side drivers are designed with
300-mA source and sink capability to quickly drive the
power MOSFETs gates. The low-side driver is supplied
from VIN, while the high-side drive is supplied from the
BOOT pin. A bootstrap circuit uses an external BOOT
capacitor and an internal 2.5-Ω bootstrap switch
connected between the VIN and BOOT pins. The
integrated bootstrap switch improves drive efficiency and
reduces external component count.
OVERCURRENT PROTECTION
The cycle-by-cycle current limiting is achieved by sensing
the current flowing through the high-side MOSFET and
comparing this signal to a preset overcurrent threshold.
The high side MOSFET is turned off within 200 ns of
reaching the current limit threshold. A 100-ns leading edge
blanking circuit prevents current limit false tripping.
Current limit detection occurs only when current flows from
VIN to PH when sourcing current to the output filter. Load
protection during current sink operation is provided by
thermal shutdown.
THERMAL SHUTDOWN
The device uses the thermal shutdown to turn off the power
MOSFETs and disable the controller if the junction
temperature exceeds 150°C. The device is released from
shutdown automatically when the junction temperature
decreases to 10°C below the thermal shutdown trip point,
and starts up under control of the slow-start circuit.
Thermal shutdown provides protection when an overload
condition is sustained for several milliseconds. With a
persistent fault condition, the device cycles continuously;
starting up by control of the soft-start circuit, heating up due
to the fault condition, and then shutting down upon
reaching the thermal shutdown trip point. This sequence
repeats until the fault condition is removed.
POWER-GOOD (PWRGD)
The power good circuit monitors for under voltage
conditions on VSENSE. If the voltage on VSENSE is 10%
below the reference voltage, the open-drain PWRGD
output is pulled low. PWRGD is also pulled low if VIN is
less than the UVLO threshold or SS/ENA is low, or a
thermal shutdown occurs. When VIN ≥ UVLO threshold,
SS/ENA ≥ enable threshold, and VSENSE > 90% of Vref,
the open drain output of the PWRGD pin is high. A
hysteresis voltage equal to 3% of Vref and a 35 µs falling
edge deglitch circuit prevent tripping of the power good
comparator due to high frequency noise.
13
34434
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SLVS455A − JANUARY 2003 − REVISED JUNE 2003
PWP (R−PDSO−G20)
14
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