ONSEMI MC100LVE111FNR2

MC100LVE111
3.3VECL 1:9 Differential
Clock Driver
The MC100LVE111 is a low skew 1−to−9 differential driver,
designed with clock distribution in mind. The MC100LVE111’s
function and performance are similar to the popular MC100E111, with
the added feature of low voltage operation. It accepts one signal input,
which can be either differential or single−ended if the VBB output is
used. The signal is fanned out to 9 identical differential outputs.
The LVE111 is specifically designed, modeled and produced with
low skew as the key goal. Optimal design and layout serve to minimize
gate to gate skew within a device, and empirical modeling is used to
determine process control limits that ensure consistent t pd
distributions from lot to lot. The net result is a dependable, guaranteed
low skew device.
To ensure that the tight skew specification is met it is necessary that
both sides of the differential output are terminated into 50 W, even if
only one side is being used. In most applications, all nine differential
pairs will be used and therefore terminated. In the case where fewer
than nine pairs are used, it is necessary to terminate at least the output
pairs on the same package side as the pair(s) being used on that side, in
order to maintain minimum skew. Failure to do this will result in small
degradations of propagation delay (on the order of 10−20 ps) of the
output(s) being used which, while not being catastrophic to most
designs, will mean a loss of skew margin.
The MC100LVE111, as with most other ECL devices, can be
operated from a positive VCC supply in PECL mode. This allows the
LVE111 to be used for high performance clock distribution in +3.3 V
systems. Designers can take advantage of the LVE111’s performance
to distribute low skew clocks across the backplane or the board. In a
PECL environment, series or Thevenin line terminations are typically
used as they require no additional power supplies. For systems
incorporating GTL, parallel termination offers the lowest power by
taking advantage of the 1.2 V supply as a terminating voltage. For
more information on using PECL, designers should refer to
Application Note AN1406/D.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single−ended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB
and VCC via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
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MARKING
DIAGRAM*
1 28
MC100LVE111G
AWLYYWW
PLCC−28
FN SUFFIX
CASE 776
A
WL
YY
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
*For additional information on our Pb−Free strategy
and soldering details, please download the
ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
Features
•
•
•
•
•
•
•
•
200 ps Part−to−Part Skew
50 ps Output−to−Output Skew
The 100 Series Contains Temperature Compensation
PECL Mode Operating Range: VCC = 3.0 V to 3.8 V with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V with VEE = −3.0 V to −3.8 V
Internal Input Pulldown Resistors
Q Output will Default LOW with Inputs Open or at VEE
Pb−Free Packages are Available*
© Semiconductor Components Industries, LLC, 2006
November, 2006 − Rev. 7
1
Publication Order Number:
MC100LVE111/D
MC100LVE111
Q0
Q0
Q1 VCCO Q1
Q2
Q2
25
24
23
20
19
22
21
VEE
26
18
Q3
NC
27
17
Q3
IN
28
16
Q4
15
VCCO
VCC
28−Lead PLCC
(Top View)
1
IN
2
14
Q4
VBB
3
13
Q5
NC
4
12
Q5
5
6
7
8
9
Q8
Q8
Q7 VCCO Q7
10
11
Q6
Q6
Warning: All VCC, VCCO, and VEE pins must be externally connected
to Power Supply to guarantee proper operation.
Figure 1. Pinout (Top View) and Logic Diagram
Q0
Table 1. PIN DESCRIPTION
Q0
Pin
Q1
IN, IN
Q0, Q0−Q8, Q8
VBB
VCC, VCCO
VEE
NC
Q1
Q2
Q2
Q3
Q3
IN
Q4
IN
Q4
Q5
Q5
Q6
Q6
Q7
Q7
Q8
Q8
VBB
Figure 2. Logic Symbol
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2
Function
ECL Differential Input Pair
ECL Differential Outputs
Reference Voltage Output
Positive Supply
Negative Supply
No Connect
MC100LVE111
Table 2. ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 kW
Internal Input Pullup Resistor
ESD Protection
N/A
Human Body Model
Machine Model
> 2 kV
> 200 V
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Flammability Rating
Level 1
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
Transistor Count
250
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 3. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
VCC
PECL Mode Power Supply
VEE = 0 V
8 to 0
V
VEE
NECL Mode Power Supply
VCC = 0 V
−8 to 0
V
VI
PECL Mode Input Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
6 to 0
−6 to 0
V
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
IBB
VBB Sink/Source
± 0.5
mA
TA
Operating Temperature Range
−40 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
PLCC−28
PLCC−28
63.5
43.5
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
Standard Board
PLCC−28
22 to 26 ± 5%
°C/W
Tsol
Wave Solder
<2 to 3 sec @ 248°C
<2 to 3 sec @ 260°C
265
265
°C
Pb
Pb−Free
VI VCC
VI VEE
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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MC100LVE111
Table 4. LVPECL DC CHARACTERISTICS VCC = 3.3 V; VEE = 0 V (Note 2)
−40°C
Symbol
Characteristic
Min
25°C
Typ
Max
55
66
Min
85°C
Typ
Max
55
66
Min
Typ
Max
Unit
65
78
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 3)
2215
2345
2420
2275
2345
2420
2275
2345
2420
mV
VOL
Output LOW Voltage (Note 3)
1490
1595
1680
1490
1595
1680
1490
1595
1680
mV
VIH
Input HIGH Voltage (Single−Ended)
2135
2420
2135
2420
2135
2420
mV
VIL
Input LOW Voltage (Single−Ended)
1490
1825
1490
1825
1490
1825
mV
VBB
Output Voltage Reference
1.92
2.04
1.92
2.04
1.92
2.04
V
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 4)
1.8
2.9
1.8
2.9
1.8
2.9
V
IIH
Input HIGH Current
150
mA
IIL
Input LOW Current
150
150
0.5
0.5
0.5
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
2. Input and output parameters vary 1:1 with VCC. VEE can vary ±0.3 V.
3. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.
4. VIHCMR min varies 1:1 with VEE, maximum varies 1:1 with VCC. VIHCMR is defined as the range within which the VIH level may vary, with the
device still meeting the propagation delay specification. The VIL level must be such that the peak to peak voltage is less than 1.0 V and greater
than or equal to VPP(min).
Table 5. LVNECL DC CHARACTERISTICS VCC = 0 V; VEE = −3.3 V (Note 5)
−40°C
Symbol
Characteristic
Min
25°C
Typ
Max
55
66
Min
85°C
Typ
Max
55
66
Min
Typ
Max
Unit
65
78
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 6)
−1085
−955
−880
−1025
−955
−880
−1025
−955
−880
mV
VOL
Output LOW Voltage (Note 6)
−1810
−1705
−1620
−1810
−1705
−1620
−1810
−1705
−1620
mV
VIH
Input HIGH Voltage (Single−Ended)
−1165
−880
−1165
−880
−1165
−880
mV
VIL
Input LOW Voltage (Single−Ended)
−1810
−1475
−1810
−1475
−1810
−1475
mV
VBB
Output Voltage Reference
−1.38
−1.26
−1.38
−1.26
−1.38
−1.26
V
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 7)
−1.5
−0.4
−1.5
−0.4
−1.5
−0.4
V
IIH
Input HIGH Current
150
mA
IIL
Input LOW Current
150
0.5
150
0.5
0.5
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Input and output parameters vary 1:1 with VCC. VEE can vary ±0.3 V.
6. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.
7. VIHCMR min varies 1:1 with VEE, maximum varies 1:1 with VCC. VIHCMR is defined as the range within which the VIH level may vary, with the
device still meeting the propagation delay specification. The VIL level must be such that the peak to peak voltage is less than 1.0 V and greater
than or equal to VPP(min).
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4
MC100LVE111
Table 6. AC CHARACTERISTICS VCC = 3.3 V; VEE = 0 V or VCC = 0 V; VEE = −3.3 V (Note 8)
−40°C
Symbol
Characteristic
Min
Typ
25°C
Max
Min
> 1.5
Typ
85°C
Max
fmax
Maximum Toggle Frequency
tPLH
tPHL
Propagation Delay to Output
IN (Differential Configuration) (Note 9)
sIN (Single−Ended) (Note 10)
tskew
Within−Device Skew (Note 11)
Part−to−Part Skew
(Differential Configuration)
tJITTER
Cycle−to−Cycle Jitter
VPP
Input Swing (Note 12)
500
1000
500
1000
tr/tf
Output Rise/Fall Time (20%−80%)
200
600
200
600
Min
> 1.5
400
350
650
700
440
390
0.2
445
395
0.2
Unit
GHz
635
685
50
200
<1
Max
> 1.5
630
680
50
250
Typ
ps
50
200
ps
<1
ps
500
1000
mV
200
600
ps
<1
0.2
900
9
800
8
700
7
600
6
500
5
400
4
300
3
200
2
JITTER OUT ps (RMS)
VOUTpp (mV)
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
8. VEE can vary ±0.3 V.
9. The differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing point of the
differential output signals.
10. The single−ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of the output signal.
11. The within−device skew is defined as the worst case difference between any two similar delay paths within a single device.
12. VPP(min) is defined as the minimum input differential voltage which will cause no increase in the propagation delay. The VPP(min) is AC limited
for the E111 as a differential input as low as 50 mV will still produce full ECL levels at the output.
ÉÉ
ÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
(JITTER)
100
0
1
0
300
600
900
1200
1500
FREQUENCY (MHz)
Figure 3. Fmax/Jitter
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5
1800
2100
2400
MC100LVE111
Zo = 50 W
Q
D
Receiver
Device
Driver
Device
Q
D
Zo = 50 W
50 W
50 W
VTT
VTT = VCC − 2.0 V
Figure 4. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
ORDERING INFORMATION
Package
Shipping †
MC100LVE111FN
PLCC−28
37 Units / Rail
MC100LVE111FNG
PLCC−28
(Pb−Free)
37 Units / Rail
MC100LVE111FNR2
PLCC−28
500 / Tape & Reel
MC100LVE111FNR2G
PLCC−28
(Pb−Free)
500 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D
− ECL Clock Distribution Techniques
AN1406/D
− Designing with PECL (ECL at +5.0 V)
AN1503/D
− ECLinPSt I/O SPiCE Modeling Kit
AN1504/D
− Metastability and the ECLinPS Family
AN1568/D
− Interfacing Between LVDS and ECL
AN1672/D
− The ECL Translator Guide
AND8001/D
− Odd Number Counters Design
AND8002/D
− Marking and Date Codes
AND8020/D
− Termination of ECL Logic Devices
AND8066/D
− Interfacing with ECLinPS
AND8090/D
− AC Characteristics of ECL Devices
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MC100LVE111
PACKAGE DIMENSIONS
PLCC−28
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 776−02
ISSUE E
−N−
0.007 (0.180)
B
Y BRK
T L−M
M
0.007 (0.180)
U
M
N
S
T L−M
S
S
N
S
D
Z
−M−
−L−
W
28
D
X
V
1
A
0.007 (0.180)
R
0.007 (0.180)
C
M
M
T L−M
T L−M
S
S
N
S
N
S
0.007 (0.180)
H
N
S
S
G
J
0.004 (0.100)
−T− SEATING
T L−M
S
N
T L−M
S
N
S
K
PLANE
F
VIEW S
G1
M
K1
E
S
T L−M
S
VIEW D−D
Z
0.010 (0.250)
0.010 (0.250)
G1
VIEW S
S
NOTES:
1. DATUMS −L−, −M−, AND −N− DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS
PLASTIC BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM −T−, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE
MOLD FLASH. ALLOWABLE MOLD FLASH IS
0.010 (0.250) PER SIDE.
4. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO 0.012
(0.300). DIMENSIONS R AND U ARE
DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR
BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUDING ANY MISMATCH
BETWEEN THE TOP AND BOTTOM OF THE
PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037
(0.940). THE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMENSION TO BE
SMALLER THAN 0.025 (0.635).
DIM
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
G1
K1
INCHES
MIN
MAX
0.485
0.495
0.485
0.495
0.165
0.180
0.090
0.110
0.013
0.019
0.050 BSC
0.026
0.032
0.020
−−−
0.025
−−−
0.450
0.456
0.450
0.456
0.042
0.048
0.042
0.048
0.042
0.056
−−− 0.020
2_
10_
0.410
0.430
0.040
−−−
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7
MILLIMETERS
MIN
MAX
12.32
12.57
12.32
12.57
4.20
4.57
2.29
2.79
0.33
0.48
1.27 BSC
0.66
0.81
0.51
−−−
0.64
−−−
11.43
11.58
11.43
11.58
1.07
1.21
1.07
1.21
1.07
1.42
−−−
0.50
2_
10_
10.42
10.92
1.02
−−−
0.007 (0.180)
M
T L−M
S
N
S
MC100LVE111
ECLinPS is a trademark of Semiconductor Components INdustries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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MC100LVE111/D