TI TPS3103H20DBVR

TPS3103xxx
TPS3106xxx
TPS3110xxx
www.ti.com
SLVS363D – AUGUST 2001 – REVISED NOVEMBER 2006
UltraLow Supply-Current/Supply-Voltage Supervisory Circuits
FEATURES
•
•
•
•
•
•
•
•
DESCRIPTION
Precision Supply Voltage Supervision Range:
0.9 V, 1.2 V, 1.5 V, 1.6 V, 2 V, and 3.3 V
High Trip-Point Accuracy: 0.75%
Supply Current of 1.2 µA (typical)
RESET Defined With Input Voltages as Low as
0.4 V
Power-On Reset Generator With a Delay Time
of 130 ms
Push/Pull or Open-Drain RESET Outputs
SOT23-6 Package
Package Temperature Range: –40°C to +85°C
•
•
•
•
•
During power-on, RESET is asserted when the
supply voltage (VDD) becomes higher than 0.4 V.
Thereafter, the supervisory circuit monitors VDD and
keeps the RESET output active as long as VDD
remains below the threshold voltage (VIT). An internal
timer delays the return of the output to the inactive
state to ensure proper system reset. The delay time
starts after VDD has risen above VIT. When VDD drops
below VIT, the output becomes active again.
All the devices of this family have a fixed-sense
threshold voltage (VIT) set by an internal voltage
divider.
APPLICATIONS
•
The TPS310x and TPS311x families of supervisory
circuits provide circuit initialization and timing
supervision, primarily for DSP and processor-based
systems.
Applications Using Low-Power DSPs,
Microcontrollers, or Microprocessors
Portable- and Battery-Powered Equipment
Intelligent Instruments
Wireless Communication Systems
Industrial Equipment
Notebook/Desktop Computers
The TPS3103 and TPS3106 have an active-low,
open-drain RESET output. The TPS3110 has an
active-low push/pull RESET.
The product spectrum is designed for supply
voltages of 0.9 V up to 3.3 V. The circuits are
available in SOT23-6 packages. The TPS31xx family
is characterized for operation over a temperature
range of –40°C to +85°C.
TPS3106
DBV PACKAGE
(TOP VIEW)
TPS3103
DBV PACKAGE
(TOP VIEW)
3.3 V
RESET
1
6
VDD
RSTVDD
1
6
VDD
GND
2
5
PFO
GND
2
5
RSTSENSE
1.6 V
VCORE
VDD
MR
3
VIO
DSP
R1
PFI
4
TPS3106K33DBV
R3
MR
3
4
SENSE
MR
RSTVDD
RESET
SENSE
TPS3110
DBV PACKAGE
(TOP VIEW)
R2
RSTSENSE
GND
RESET
1
6
VDD
GND
2
5
WDI
MR
3
4
SENSE
GND
GND
Typical Application Circuit
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2001–2006, Texas Instruments Incorporated
TPS3103xxx
TPS3106xxx
TPS3110xxx
www.ti.com
SLVS363D – AUGUST 2001 – REVISED NOVEMBER 2006
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
ORDERING INFORMATION (1)
(1)
(2)
PRODUCT
NOMINAL SUPPLY VOLTAGE
THRESHOLD VOLTAGE, VIT (2)
TPS3103E12DBVR
1.2 V
1.142 V
1.434 V
TPS3103E15DBVR
1.5 V
TPS3103H20DBVR
2.0 V
1.84 V
TPS3103K33DBVR
3.3 V
2.941 V
TPS3106E09DBVR
0.9 V
0.86 V
TPS3106E16DBVR
1.6 V
1.521 V
TPS3106K33DBVR
3.3 V
2.941 V
TPS3110E09DBVR
0.9 V
0.86 V
TPS3110E12DBVR
1.2 V
1.142 V
TPS3110E15DBVR
1.5 V
1.434 V
TPS3110K33DBVR
3.3 V
2.941 V
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Custom threshold voltages are available. Minimum order quantities apply. Contact factory for details and availability.
AVAILABLE OPTIONS
DEVICE
RESET OUTPUT
TPS3103
Open-drain
RSTSENSE, RSTVDD OUTPUT
SENSE INPUT
Open-drain
ü
TPS3106
TPS3110
WDI INPUT
PFO OUTPUT
Open-drain
ü
Push-pull
ü
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range, unless otherwise noted.
Supply voltage, VDD (2)
MR Pin, VMR
All other pins (2)
UNIT
V
–0.3 to VDD + 0.3
V
–0.3 to +3.6
V
5
mA
Maximum high output current, IOH
–5
mA
Input clamp current, IIK (VI < 0 or VI > VDD)
±10
mA
Output clamp current, IOK (VO < 0 or VO > VDD)
±10
mA
Maximum low output current, IOL
Continuous total power dissipation
See Dissipation Rating Table
Operating temperature range, TA
–40 to +85
°C
Storage temperature range, TSTG
–65 to +150
°C
+260
°C
Soldering temperature
(1)
(2)
2
VALUE
–0.3 to +3.6
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to GND. For reliable operation, the device must not be operated at 3.6 V for more than t = 1000h
continuously.
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TPS3110xxx
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SLVS363D – AUGUST 2001 – REVISED NOVEMBER 2006
DISSIPATION RATINGS
PACKAGE
TA≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = +25°C
TA = +70°C
POWER RATING
TA = +85°C
POWER RATING
DBV
437 mW
3.5 mW/°C
280 mW
227 mW
RECOMMENDED OPERATING CONDITIONS
Over operating free-air temperature range, unless otherwise noted.
Supply voltage, VDD (1)
Input voltage, VI
MIN
MAX
0.4
3.3
V
0
VDD + 0.3
V
0.7 × VDD
High-level input voltage, VIH at MR, WDI
V
0.3 × VDD
Low-level input voltage, VIL at MR, WDI
Input transition rise and fall rate at ∆t/∆V at MR, WDI
Operating temperature range, TA
(1)
UNIT
–40
V
100
ns/V
+85
°C
For proper operation of SENSE, PFI, and WDI functions: VDD ≥ 0.8 V.
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDD = 3.3 V, IOH = –3 mA
VDD = 1.8 V, IOH = –2 mA
VOH
High-level output voltage
VDD = 1.5 V, IOH = –1 mA
0.8 × VDD
V
0.7 × VDD
V
VDD = 0.9 V, IOH = –0.4 mA
VDD = 0.5 V, IOH = –5 µA
VDD = 3.3 V, IOL = 3 mA
VOL
Low-level output voltage
VOL
Low-level output voltage
VDD = 1.5 V, IOL = 2 mA
VDD = 1.2 V, IOL = 1 mA
0.3
V
0.1
V
VDD = 0.9 V, IOL = 500 µA
Negative-going input
threshold voltage (1)
VIT–
VIT – (S)
Negative-going input
threshold voltage (1)
VHYS
Hysteresis at VDD input
RESET only
VDD = 0.4 V, IOL = 5 µA
TPS31xxE09
0.854
0.860
0.866
TPS31xxE12
1.133
1.142
1.151
1.423
1.434
1.445
1.512
1.523
1.534
TPS31xxH20
1.829
1.843
1.857
TPS31xxK33
2.919
2.941
2.963
0.542
0.551
0.559
TPS31xxE15
TPS31xxE16
SENSE, PFI
TA = +25°C
VDD ≥ 0.8 V, TA = +25°C
0.8 V ≤ VIT < 1.5 V
20
1.6 V ≤ VIT < 2.4 V
30
2.5 V ≤ VIT < 3.3 V
50
T(K)
Temperature coefficient of VIT–, PFI,
SENSE
TA = –40°C to +85°C
VHYS
Hysteresis at SENSE, PFI input
VDD ≥ 0.8 V
IIH
(1)
High-level input current
–0.012
V
V
mV
–0.019
15
%/K
mV
MR
MR = VDD, VDD = 3.3 V
–25
25
SENSE, PFI,
WDI
SENSE, PFI, WDI = VDD,
VDD = 3.3 V
–25
25
nA
To ensure the best stability of the threshold voltage, a bypass capacitor (ceramic, 0.1 µF) should be placed close to the supply
terminals.
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SLVS363D – AUGUST 2001 – REVISED NOVEMBER 2006
ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
IIL
Low-level input current
IOH
High-level output current
at RESET (2)
IDD
TEST CONDITIONS
MIN
TYP
MAX
UNIT
–33
–25
µA
25
nA
200
nA
MR
MR = 0 V, VDD = 3.3 V
–47
SENSE, PFI,
WDI
SENSE, PFI, WDI = 0 V,
VDD = 3.3 V
–25
Open-drain
VDD = VIT + 0.2 V, VOH = 3.3 V
Supply current
VDD > VIT (average current),
VDD < 1.8 V
1.2
3
VDD > VIT (average current),
VDD > 1.8 V
2
4.5
VDD < VIT, VDD < 1.8 V
22
VDD < VIT, VDD > 1.8 V
Internal pull-up resistor at MR
CI
(2)
µA
27
70
100
Input capacitance at MR, SENSE, PFI, WDI VI = 0 V to VDD
130
kΩ
1
pF
Also refers to RSTVDD and RSTSENSE.
SWITCHING CHARACTERISTICS
At RL = 1 MΩ, CL = 50 pF, and TA = –40°C to +85°C, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
65
130
195
ms
VIH = 1.1 × VIT, VIL = 0.9 × VIT
40
µs
VDD to RESET or
RSTVDD delay
VIH = 1.1 × VIT, VIL = 0.9 × VIT
40
µs
Propagation delay time,
high-to-low level output
SENSE to RESET or
RSTSENSE delay
VDD ≥ 0.8 V, VIH = 1.1 × VIT, VIL = 0.9 × VIT
40
µs
tPLH
Propagation delay time,
high-to-low level output
SENSE to RESET or
RSTSENSE delay
VDD ≥ 0.8 V, VIH = 1.1 × VIT, VIL = 0.9 × VIT
40
µs
tPHL
Propagation delay time,
high-to-low level output
PFI to PFO delay
VDD ≥ 0.8 V, VIH = 1.1 × VIT, VIL = 0.9 × VIT
40
µs
tPLH
Propagation delay time,
low-to-high level output
PFI to PFO delay
VDD ≥ 0.8 V, VIH = 1.1 × VIT, VIL = 0.9 × VIT
300
µs
tPHL
Propagation delay time,
low-to-high level output
MR to RESET.
RSTVDD,
RSTSENSE delay
VDD ≥ 1.1 × VIT, VIL = 0.3 × VDD, VIH = 0.7 × VDD
1
5
µs
tPLH
Propagation delay time,
low-to-high level output
MR to RESET.
RSTVDD,
RSTSENSE delay
VDD ≥ 1.1 × VIT, VIL = 0.3 × VDD, VIH = 0.7 × VDD
1
5
µs
VDD ≥ 1.1 × VIT, MR = 0.7 × VDD, See Timing Diagrams
tD
Delay time
tPHL
Propagation delay time,
high-to-low level output
VDD to RESET or
RSTVDD delay
tPLH
Propagation delay time,
low-to-high level output
tPHL
TIMING REQUIREMENTS
At RL = 1 MΩ, CL = 50 pF, and TA = –40°C to +85°C, unless otherwise noted.
PARAMETER
tT(OUT)
tW
4
Time-out period
Pulse width
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.55
1.1
1.65
s
at WDI
VDD ≥ 0.85 V
at VDD
VIH = 1.1 × VIT, VIL = 0.9 × VIT–, VIT– = 0.86 V
20
at MR
VDD ≥ VIT + 0.2 V, VIL = 0.3 × VDD, VIH = 0.7 × VDD
0.1
at SENSE
VDD ≥ VIT, VIH = 1.1 × VIT – (S), VIL = 0.9 × VIT – (S)
20
at PFI
VDD ≥ 0.85 V, VIH = 1.1 × VIT – (S),VIL = 0.9 × VIT – (S)
20
at WDI
VDD ≥ VIT, VIL = 0.3 × VDD, VIH = 0.7 × VDD
0.3
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TPS3110xxx
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SLVS363D – AUGUST 2001 – REVISED NOVEMBER 2006
FUNCTIONAL BLOCK DIAGRAMS
TPS3103
VDD
VIT+
_
MR
Reset Logic
and Timer
+
_
PFI
RESET
PFO
0.551 V
GND
TPS3106
VDD
VIT-
+
_
MR
+
_
SENSE
Reset Logic
and Timer
Reset Logic
and Timer
RSTVDD
RSTSENSE
0.551 V
GND
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SLVS363D – AUGUST 2001 – REVISED NOVEMBER 2006
FUNCTIONAL BLOCK DIAGRAMS (continued)
TPS3110
VDD
VIT-
+
_
MR
RESET
Reset Logic
and Timer
+
_
SENSE
0.551 V
Watchdog
Logic and
Control
WDI
GND
Table 1. TPS3103 FUNCTION TABLE
(1)
MR
V(PFI) > 0.551 V
VDD > VIT
RESET
L
0
X (1)
L
PFO
L
L
1
X
L
H
H
0
0
L
L
H
0
1
H
L
H
1
0
L
H
H
1
1
H
H
X = Don’t care.
Table 2. TPS3106 FUNCTION TABLE
(1)
MR
V(SENSE) > 0.551 V
VDD > VIT
RSTVDD
RSTSENSE
L
X (1)
X
L
L
H
0
0
L
L
H
0
1
H
L
H
1
0
L
H
H
1
1
H
H
X = Don’t care.
Table 3. TPS3110 FUNCTION TABLE (1)
(1)
(2)
6
MR
V(SENSE) > 0.551 V
VDD > VIT
RESET
L
X (2)
X
L
H
0
0
L
H
0
1
L
H
1
0
L
H
1
1
H
Function of watchdog-timer not shown.
X = Don’t care.
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SLVS363D – AUGUST 2001 – REVISED NOVEMBER 2006
PIN DESCRIPTIONS
TPS3106
DBV PACKAGE
(TOP VIEW)
TPS3103
DBV PACKAGE
(TOP VIEW)
TPS3110
DBV PACKAGE
(TOP VIEW)
RESET
1
6
VDD
RSTVDD
1
6
VDD
GND
2
5
PFO
GND
2
5
RSTSENSE
MR
3
4
PFI
MR
3
4
SENSE
RESET
1
6
VDD
GND
2
5
WDI
MR
3
4
SENSE
TERMINAL FUNCTIONS
TERMINAL
DESCRIPTION
NAME
DEVICE
NO.
GND
ALL
2
GND
MR
ALL
3
Manual-reset input. Pull low to force a reset. RESET remains low as long as MR is low and for
the timeout period after MR goes high. Leave unconnected or connect to VDD when unused.
PFI
TPS3103
4
Power-fail input compares to 0.551 V with no additional delay. Connect to VDD if not used.
PFO
TPS3103
5
Power-fail output. Goes high when voltage at PFI rises above 0.551 V.
RESET
TPS3103,
TPS3110
1
Active-low reset output. Either push-pull or open-drain output stage.
RSTSENSE
TPS3106
5
Active-low reset output. Logic level at RSTSENSE only depends on the voltage at SENSE and
the status of MR.
RSTVDD
TPS3106
1
Active-low reset output. Logic level at RSTVDD only depends on the voltage at VDD and the
status of MR.
SENSE
TPS3106,
TPS3110
4
A reset will be asserted if the voltage at SENSE is lower than 0.551 V. Connect to VDD if
unused.
VDD
ALL
6
Supply voltage. Powers the device and monitors its own voltage.
WDI
TPS3110
5
Watchdog timer input. If WDI remains high or low longer than the time-out period, then reset is
triggered. The timer clears when reset is asserted or when WDI sees a rising edge or a falling
edge.
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SLVS363D – AUGUST 2001 – REVISED NOVEMBER 2006
TIMING DIAGRAMS
Timing Diagrams for TPS3103
VDD
VIT
0.4 V
t
tD
SENSE
VIT - (S) = 0.551 V
tD
tD
tD
tD
t
t
RESET
Output Condition
Undefined
Output Condition
Undefined
t
MR
t
PFI
VIT - (S) = 0.551 V
t
PFO
Output Condition
Undefined
Output Condition
Undefined
t
8
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TIMING DIAGRAMS (continued)
Timing Diagram for TPS3106
VDD
VIT
0.4 V
tD
t
tD
RSTVDD
Output Condition
Undefined
Output Condition
Undefined
t
SENSE
VIT - (S) = 0.551 V
RSTSENSE
t
tD
Output Condition
Undefined
Output Condition
Undefined
tD
t
MR
t
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SLVS363D – AUGUST 2001 – REVISED NOVEMBER 2006
TIMING DIAGRAMS (continued)
Timing Diagram for TPS3110
VDD
VIT
0.4 V
tD
t
SENSE
VIT - (S) = 0.551 V
tD
tD
tD
t
tD
RESET
tD
Output Condition
Undefined
Output Condition
Undefined
t(TOUT)
WDI
x = Don’t Care
MR
t
10
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TYPICAL CHARACTERISTICS
TPS3110E09
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
TPS3110E09
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
20
0.30
TA = 85°C
16
TA = 25°C
14
TA = 0°C
VOL - Low-Level Output Voltage - V
IDD - Supply Current - mA
18
SENSE = VDD
MR = Open
RESET = Open
WDI: Triggered
12
10
TA = -40°C
8
6
4
VDD = 0.9 V
SENSE = GND
MR = GND
WDI = GND
0.25
0.20
TA = 85°C
TA = 25°C
0.15
TA = 0°C
0.10
TA = -40°C
0.05
2
0
0
0.5
1.0
1.5
2.0
2.5
VDD - Supply Voltage - V
0
3.0
Figure 2.
TPS3110E09
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
TPS3110E09
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
2.0
0.90
VDD = 3.3 V
SENSE = GND
MR = GND
WDI = GND
0.8
TA = 85°C
VOH - High-Level Output Voltage - V
0.9
TA = 25°C
0.7
0.6
TA = 0°C
0.5
TA = -40°C
0.4
0.3
0.2
0.85
TA = 85°C
0.80
0.75
TA = 25°C
TA = 0°C
0.70
VDD = 0.9 V
SENSE = VDD
MR = VDD
WDI : Triggered
0.65
0.1
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
IOL - Low-Level Output Current - mA
Figure 1.
1.0
VOL - Low-Level Output Voltage - V
0
0
2
4
6
8
10
12
14
16
18
20
0.60
0
IOL - Low-Level Output Current - mA
Figure 3.
-0.1
TA = -40°C
-0.2
-0.3
-0.4
-0.5
IOH - High-Level Output Current - mA
Figure 4.
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TYPICAL CHARACTERISTICS (continued)
TPS3110K33
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
MINIMUM PULSE DURATION AT VDD
vs
THRESHOLD OVERDRIVE VOLTAGE
50
VDD = 3.3 V
SENSE = VDD
MR = VDD
WDI : Triggered
3.2
tW - Minimum Pulse Duration at VDD - ms
VOH - High-Level output Voltage - V
3.4
3.0
TA = -40°C
2.8
TA = 0°C
2.6
TA = 25°C
2.4
TA = 85°C
2.2
2.0
MR : Open
SENSE = VDD
45
40
35
30
VDD = 3.3 V
25
20
15
10
VDD = 0.9 V
5
0
0
-5
-10
-15
-20
0
-25
0.1
0.2
Figure 5.
Figure 6.
NORMALIZED THRESHOLD VOLTAGE
vs
FREE-AIR TEMPERATURE
VIT - Normalized Threshold Voltage - V
1.008
1.006
1.004
1.002
1.000
0.998
0.996
0.994
0.992
-50
0
50
TA - Free-Air Temperature - °C
Figure 7.
12
0.3
0.4
VDD - Threshold Overdrive Voltage - V
IOH - Low-Level Output Current - mA
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0.5
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APPLICATION INFORMATION
The TPS31xx family has a quiescent current in the 1-µA to 2-µA range. When RESET is active, triggered by the
voltage monitored at VDD, the quiescent current increases to about 20 µA (see the Electrical Characteristics).
In some applications it is necessary to minimize the quiescent current even during the reset period. This is
especially true when the voltage of a battery is supervised and the RESET is used to shut down the system or
for an early warning. In this case the reset condition will last for a longer period of time. The current drawn from
the battery should almost be zero, especially when the battery is discharged.
For this kind of application, either the TPS3103 or TPS3106 is a good fit. To minimize current consumption,
select a version where the threshold voltage is lower than the voltage monitored at VDD. The TPS3106 has two
reset outputs. One output (RSTVDD) is triggered from the voltage monitored at VDD. The other output
(RSTSENSE) is triggered from the voltage monitored at SENSE. In the application shown in Figure 8, the
TPS3106E09 is used to monitor the input voltage of two NiCd or NiMH cells. The threshold voltage (V(TH) = 0.86
V) was chosen as low as possible to ensure that the supply voltage is always higher than the threshold voltage
at VDD. The voltage of the battery is monitored using the SENSE input. The voltage divider was calculated to
assert a reset using the RSTSENSE output at 2 × 0.8 V = 1.6 V.
R1 + R2
ǒ
Ǔ
VTRIP
*1
VIT(S)
(1)
where:
VTRIP is the voltage of the battery at which a reset is asserted and
VIT(S) is the threshold voltage at SENSE = 0.551 V.
R1 was chosen for a resistor current in the 1-µA range.
With VTRIP = 1.6 V:
R1 ≈ 1.9 × R2
R1 = 820 kΩ, R2 = 430 kΩ
VDD
R1
TPS3106E09DBV
R3
MR
RSTVDD
SENSE
RSTSENSE
2 Cell
NiMH
R2
Reset Output
GND
Figure 8. Battery Monitoring with 3-µA Supply Current for Device and Resistor Divider
Submit Documentation Feedback
13
TPS3103xxx
TPS3106xxx
TPS3110xxx
www.ti.com
SLVS363D – AUGUST 2001 – REVISED NOVEMBER 2006
APPLICATION INFORMATION (continued)
WATCHDOG
The TPS3110 device integrates a watchdog timer that must be periodically triggered by a positive or negative
transition of WDI. When the supervising system fails to retrigger the watchdog circuit within the time-out interval,
RESET becomes active for the time period (tD). This event also reinitializes the watchdog timer.
MANUAL RESET (MR)
Many µC-based products require manual-reset capability, allowing an operator or logic circuitry to initiate a
reset. Logic low at MR asserts reset. Reset remains asserted while MR is low and for a time period (tD) after MR
returns high. The input has an internal 100-kΩ pull-up resistor, so it can be left open if it is unused.
Connect a normally open momentary switch from MR to GND to create a manual reset function. External
debounce is not required. If MR is driven from long cables or if the device is used in noisy environments,
connecting a 0.1-µF capacitor from MR to GND provides additional noise immunity.
If there is a possibility of transient or DC conditions causing MR to rise above VDD, a diode should be used to
limit MR to a diode drop above VDD.
PFI, PFO
The TPS3103 has an integrated power-fail (PFI) comparator with a separate open-drain (PFO) output. The PFI
and PFO can be used for low-battery detection, power-fail warning, or for monitoring a power supply other than
the main supply, and has no effect on RESET.
An additional comparator is provided to monitor voltages other than the nominal supply voltage. The power-fail
input (PFI) will be compared with an internal voltage reference of 0.551 V. If the input voltage falls below the
power-fail threshold (VIT – (S)), the power-fail output (PFO) goes low. If it goes above 0.551 V plus approximately
15-mV hysteresis, the output returns to high. By connecting two external resistors, it is possible to supervise any
voltage above 0.551 V. The sum of both resistors should be approximately 1 MΩ, to minimize power
consumption and to assure that the current into the PFI pin can be neglected, compared with the current through
the resistor network. The tolerance of the external resistors should be not more than 1% to ensure minimal
variation of sensed voltage. If the power-fail comparator is unused, connect PFI to GND and leave PFO
unconnected. For proper operation of the PFI-comparator, the supply voltage (VDD) must be higher than 0.8 V.
SENSE
The voltage at the SENSE input is compared with a reference voltage of 0.551 V. If the voltage at SENSE falls
below the sense-threshold (VIT – (S)), reset is asserted. On the TPS3106, a dedicated RSTSENSE output is
available. On the TPS3110, the logic signal from SENSE is OR-wired with the logic signal from VDD or MR. An
internal timer delays the return of the output to the inactive state, once the voltage at SENSE goes above 0.551
V plus about 15 mV of hysteresis. For proper operation of the SENSE-comparator, the supply voltage must be
higher than 0.8 V.
14
Submit Documentation Feedback
TPS3103xxx
TPS3106xxx
TPS3110xxx
www.ti.com
SLVS363D – AUGUST 2001 – REVISED NOVEMBER 2006
APPLICATION INFORMATION (continued)
2V
VDD
R1
(1)
RESET
PFI
R2
MSP430
Low-Power mC
Px.x
RESET
TPS3103H20
MR
VDD
(1)
Analog
Circuit
Py.x
PFO
GND
GND
-2 V
V(NEG_TH) = 0.551 V - R2 (VDD - 0.551 V)
R1
(1) Resistor may be integrated in mC.
Figure 9. TPS3103 Monitoring a Negative Voltage
3.3 V
1.5 V
VCORE
VDD
V(CORE_TH) = 0.551 V x R1 + R2
R2
R1
TPS3110K33
MR
RESET
SENSE
WDI
R2
GND
VIO
DSP
RESET
Px.y
GND
GND
Figure 10. TPS3110 in a DSP-System Monitoring Both Supply Voltages
Submit Documentation Feedback
15
PACKAGE OPTION ADDENDUM
www.ti.com
16-Feb-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TBD
Lead/Ball Finish
SN0402002DBVR
ACTIVE
SOT-23
DBV
6
TPS3103E12DBVR
ACTIVE
SOT-23
DBV
6
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3103E12DBVRG4
ACTIVE
SOT-23
DBV
6
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3103E12DBVT
ACTIVE
SOT-23
DBV
6
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3103E12DBVTG4
ACTIVE
SOT-23
DBV
6
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3103E15DBVR
ACTIVE
SOT-23
DBV
6
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3103E15DBVRG4
ACTIVE
SOT-23
DBV
6
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3103E15DBVT
ACTIVE
SOT-23
DBV
6
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3103E15DBVTG4
ACTIVE
SOT-23
DBV
6
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3103H20DBVR
ACTIVE
SOT-23
DBV
6
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3103H20DBVRG4
ACTIVE
SOT-23
DBV
6
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3103H20DBVT
ACTIVE
SOT-23
DBV
6
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3103H20DBVTG4
ACTIVE
SOT-23
DBV
6
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3103K33DBVR
ACTIVE
SOT-23
DBV
6
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3103K33DBVRG4
ACTIVE
SOT-23
DBV
6
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3103K33DBVT
ACTIVE
SOT-23
DBV
6
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3103K33DBVTG4
ACTIVE
SOT-23
DBV
6
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3106E09DBVR
ACTIVE
SOT-23
DBV
6
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3106E09DBVRG4
ACTIVE
SOT-23
DBV
6
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3106E09DBVT
ACTIVE
SOT-23
DBV
6
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3106E09DBVTG4
ACTIVE
SOT-23
DBV
6
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3106E16DBVR
ACTIVE
SOT-23
DBV
6
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3106E16DBVRG4
ACTIVE
SOT-23
DBV
6
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3106E16DBVT
ACTIVE
SOT-23
DBV
6
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3106E16DBVTG4
ACTIVE
SOT-23
DBV
6
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Addendum-Page 1
Call TI
MSL Peak Temp (3)
Call TI
PACKAGE OPTION ADDENDUM
www.ti.com
16-Feb-2007
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TPS3106K33DBVR
ACTIVE
SOT-23
DBV
6
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3106K33DBVRG4
ACTIVE
SOT-23
DBV
6
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3106K33DBVT
ACTIVE
SOT-23
DBV
6
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3106K33DBVTG4
ACTIVE
SOT-23
DBV
6
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3110E09DBVR
ACTIVE
SOT-23
DBV
6
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3110E09DBVRG4
ACTIVE
SOT-23
DBV
6
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3110E09DBVT
ACTIVE
SOT-23
DBV
6
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3110E09DBVTG4
ACTIVE
SOT-23
DBV
6
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3110E12DBVR
ACTIVE
SOT-23
DBV
6
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3110E12DBVRG4
ACTIVE
SOT-23
DBV
6
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3110E12DBVT
ACTIVE
SOT-23
DBV
6
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3110E12DBVTG4
ACTIVE
SOT-23
DBV
6
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3110E15DBVR
ACTIVE
SOT-23
DBV
6
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3110E15DBVRG4
ACTIVE
SOT-23
DBV
6
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3110E15DBVT
ACTIVE
SOT-23
DBV
6
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3110E15DBVTG4
ACTIVE
SOT-23
DBV
6
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3110K33DBVR
ACTIVE
SOT-23
DBV
6
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3110K33DBVRG4
ACTIVE
SOT-23
DBV
6
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3110K33DBVT
ACTIVE
SOT-23
DBV
6
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS3110K33DBVTG4
ACTIVE
SOT-23
DBV
6
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
16-Feb-2007
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 3
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