NCP5008, NCP5009
Backlight LED Boost Driver
The NCP5008/NCP5009 is a high efficiency boost converter
operating in current loop control mode to drive Light Emitting
Diode. The current mode regulation allows a uniform brightness of
the LEDs.
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Features
•
•
•
•
•
•
•
•
•
•
•
•
•
2.7 to 6.0 V Input Voltage Range
Output Voltage from Vbat to 15 V
3.0 mA Quiescent Supply Current
Automatically LEDs Current Matching
No External Sense Resistor
Includes Dimming Function
Programmable or Automatic Current Output Mode
LOCAL or REMOTE Control Facility
Photo Transistor Sense Feedback Input
Inductor Based Converter brings High Efficiency
Low Noise DC/DC Converter
All Pins are Fully ESD Protected
Pb−Free Package is Available
MARKING
DIAGRAM
Micro 10
DM SUFFIX
CASE 846B
1
1
5Tx = Device Number
x = 8 or 9
A
= Assembly Location
Y
= Year
W = Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
PIN CONNECTIONS
Typical Applications
• LED Display Back Light Control
• High Efficiency Step Up Converter
Vbat
C1
U1
R1
1
30 k
2
GND
Q1
NPN−PHOTO
Iref
Vbat
PHOTO
L1
10
10 mF/6.3 V
GND
MICROCONTROLLER
Vcc
D5 MBR0520
D1
LED
1
10
NC
CS
2
3
9
8
VBIAS
4
7
GND
CLOCK
5
6
LOCAL
8
7
GND
6
LOCAL
Iref
1
10
Photo
CS
2
3
9
8
VBIAS
4
CLOCK
5
7
6
LED
D3
D4
LED
LED
Device
Figure 1. Typical Battery Powered LED Boost Driver
April, 2006 − Rev. 7
L2 Iout
GND
LOCAL
ORDERING INFORMATION
2.2 mF/16 V
© Semiconductor Components Industries, LLC, 2006
Vbat
L1
GND
1
Package
Shipping†
NCP5008DMR2
Micro 10
NCP5008DMR2G
Micro 10 4000 / Tape & Reel
(Pb−Free)
NCP5009DMR2
Micro 10
C2
GND
L2 Iout
NCP5009
L2
NCP5009
D2
Vbat
L1
NCP5008
GND
L1
22 mH
4
VBIAS
3
CS
5
CLK
Iref
9
Vbat
GND
5Tx
AYW G
G
4000 / Tape & Reel
4000 / Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Publication Order Number:
NCP5008/D
NCP5008, NCP5009
BACK LIGHT WHITE LED CURRENT DRIVE CONTROLLER
Vbat
Vbat
POR
R1
Iout Reference
50 k
3
9
L1
Vbat
8
L2
7
GND
Isense
+
−
CS
5
Vbat
POR
1:8
Vref Selection
CLK
4
Serial To Parallel
Latches
VBIAS
10
1R8
BandGap
A=10
GND
Vbat
Vbat
Vref
Q2
Vbat
50 k
POR
Iout
Q1
LOCAL
6
Iref
1
2
GND
Vbat
Vbat
+
Vbat_OK
BANDGAP
REFERENCE
−
PHOTO
(See Note)
CONTROLLER
GND
NOTE: This functionality is NOT implemented on the NCP5008 type.
Figure 2. Block Diagram
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2
BandGap
NCP5008, NCP5009
PIN FUNCTION DESCRIPTION
Pin
Symbol
Type
Description
1
Iref
INPUT
This pin provides the output current range adjustment by means of a resistor connected to
ground. The current output tolerance depends upon the accuracy of this resistor. Using a "1%
metal film resistor, or better, yields the best output current accuracy.
2
PHOTO
SIGNAL
This pin provides an access to the output current control loop for the NCP5009 version. The current sunk to ground from this pin is subtracted from the output current mirror. Primary use is the
ambient light automatic adjustment by means of an external photo transistor connected across
this pin and ground. The output current decreases as the ambient light increases. The internal
circuit provides a 1/1 current ratio with the Iref defined by the resistor connected from pin 1 to
ground. This current shall be limited to 65 mA.
This functionality is NOT implemented on the NCP5008 type.
3
CS
INPUT
Negative going Chip Select logic input. This pin is used to select the NCP5008/ NCP5009 and
validate the clock/data when CS = Low. The internal shift register is automatically clear to zero
upon the falling edge, thanks to a 20 ns built−in one shoot. The built−in pull−up resistor disables
the device when the CS pin is left open.
4
VBIAS
POWER
5
CLOCK
INPUT
The clock signal connected to this pin is used to serially shift right the internal preset high logic
level. The clock is valid between the falling edge and until the rising edge of the CS. There is neither a feedback nor an overflow control. If the clock count exceeds 8 bits, the internal register is
clear, the output current is forced to zero and the device comes back to the shutdown mode.
6
LOCAL
INPUT
This pin is used to select the mode of operation.
• When LOCAL = High or Open, the chip is controlled by two digital lines:CS and CLOCK. The
output current is programmed by the logic control of these pins, allowing a current adjustment
within the range defined by the Iref resistor.
• When LOCAL = Low, the chip is turned ON /OFF by means of the CS line, the CLOCK pins
being deactivated. The output current is constant, as defined by the Iref resistor value.
In order to minimize the standby current a dynamic pull−up resistor is activated when POR is
High, this pull−up resistor being disconnected when LOCAL = Low.
7
GND
POWER
This pin is the system ground for the NCP5008/NCP5009 and carries both the Power and the
Digital signals. High quality ground must be provided to avoid spikes and/or uncontrolled operation. Care must be observed to avoid high−density current flow in a limited PCB copper track.
8
L2
POWER
This pin is the power side of the external inductor and must be connected either to the external
Schottky diode (see Figure 22) or directly to one external LED (see Figure 23). It provides the
output current to the load. Since the boost converter operates in a current loop mode, the output
voltage can range up to +15 V but shall not extend this limit. The user must make sure this voltage
will not be exceeded during the normal operation of this part.
An external low cost ceramic capacitor (2.2 mF/16 V, ESR < 100 mW) is recommended to smooth
the current flowing into the diode(s), thus limiting the noise created by the fast transients present
in this circuitry.
Care must be observed to avoid EMI though the PCB copper tracks connected to this pin.
9
L1
POWER
The return side of the external inductor shall be connected to this pin. Typical application will use a
22 mH, size 1210, to handle the 2.8 to 364 mA max range. On the other hand, when the desired
output current is above 20 mA, the inductor shall have an ESR < 1.0 W. The output current tolerance can be improved by using a larger inductor value.
10
Vbat
POWER
The external voltage supply is connected to this pin. A high quality reservoir capacitor must be
connected across pin 10 and Ground to achieve the specified output voltage parameters. A
10 mF/6.3 V, low ESR capacitor must be connected as close as possible across pin 10 and
ground pin 7. The X5R ceramic types are recommended.
This pin should be connected to Vbat.
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3
NCP5008, NCP5009
Table 1. Shift Register Bits Assignment and Functions
SetReg shift register (Note: The register content is latched upon CS positive going).
B7
B6
B5
B4
B3
B2
B1
0
0
0
0
0
0
0
Iout Peak (mA)
Iref*k*7.5
Iref*k*6.5
Iref*k*5.5
Iref*k*4.5
Iref*k*3.5
Iref*k*2.5
Iref*k*1.5
LOCAL
CLOCK
CS
B1−B7
L
X
H
X
0
L
X
L
X
Iref * k
H or Open
X
H
No Change
Iref * k * (Bn + 0.5)
H or Open
↓
L
No Change
Iref * k * (Bn + 0.5)
H or Open
↑
L
Qdata → Bn
Iref * k * (Bn + 0.5)
Bn Value After POR
Output Current
The register is clear to 0 during the first 20 ns following the CS falling edge.
Note:
Coefficient Value (internal ratio): k = 746
Maximum output peak current @ B7 = 1 and Iphoto = 0 mA : Iout peak = Iref * (7 + 0.5) * 746 = Iref * 5595
V
Iref + ref + 1.24 V
R1
R1
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Vbat, VBIAS
7.0
V
VL2
16
V
CLK, CS
−0.3 tV tVbat + 3.0 V
1.0
V
mA
Human Body Model: R = 1500 W, C = 100 pF
ESD
"2.0
kV
Machine Model
ESD
"200
V
Micro 10 Package
Power Dissipation @ TA = +85°C
Thermal Resistance, Junction−to−Air
PD
RThja
200
200
mW
°C/W
Power Supply
Output Power Supply Voltage Compliance
Digital Input Voltage
Digital Input Current
Operating Ambient Temperature Range
TA
−25 to +85
°C
Operating Junction Temperature Range
TJ
−25 to +125
°C
TJmax
+150
°C
Tstg
−65 to +150
°C
Maximum Junction Temperature
Storage Temperature Range
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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4
NCP5008, NCP5009
POWER SUPPLY SECTION (−25°C to +85°C ambient temperature, unless otherwise noted.)
Pin
Symbol
Min
Typ
Max
Unit
Power Supply
10
Vbat
2.7
−
6.0
V
Power Supply Threshold Startup Voltage
10
VbatThr
−
2.3
2.7
V
Output Load Voltage Compliance
8
Vout
−
−
15.0
V
Pulsed Current Regulation Range
8
Iout
0
−
400
mA
Continuous DC Current in the Load
8
Iout
−
−
75
mA
Output Pulsed Current Tolerance @ Vbat = 3.6 V, L1 = 22 mH/0.71 W,
Rref "1%, ILED = 20 mA (Note 1)
8
Iout
−
"5.0
−
%
Output Leakage @ LOCAL = 0, CS = H, Vout = 15 V, Vbat = 6.0 V
8
Iout
−
−
500
nA
Standby Current @ Iout = 0 mA, CS = H, CLK = H, Vbat = VBIAS = 3.6 V
10
Istdb
−
3.0
−
mA
Standby Current @ Iout = 0 mA, CS = H, CLK = H, Vbat = VBIAS = 6.0 V
10
Istdb
−
−
10
mA
Operating Current @ Vbat = VBIAS = 3.6 V, Iref = 30 mA, CLK = H, CS = L,
LOCAL = Open
10
Iope
−
600
−
Boost Internal Oscillator Clock @ L1 = 22 mH, Vbat = VBIAS = 3.6 V,
Iout = 20 mA (Vout = 14 V)
−
Rating
mA
Fosc
−
300
−
kHz
1. The tolerance refers to the 20 mA to 70 mA current range.
DIGITAL SECTION (−25°C to +85°C ambient temperature, unless otherwise noted.)
Pin
Symbol
Min
Typ
Max
Unit
High Level Input Voltage
Low Level Input Voltage
Input Capacitance
(Note 2)
(Note 2)
3, 5
VIH
VIL
Cin
0.7*Vbat
−
−
−
−
10
Vbat
0.3*Vbat
−
V
V
pF
High Level Input Voltage
Low Level Input Voltage
Input Capacitance
(Note 2)
(Note 2)
6
VIH
VIL
Cin
−
−
−
0.6*Vbat
0.4*Vbat
10
−
−
−
V
V
pF
LOCAL Pullup Resistor
6
Rloc
20
−
80
kW
LOCAL Leakage Current
9
ILoc
−
−
100
nA
CS Pullup Resistor
3
Rcs
20
−
80
kW
Minimum CS Low Time
3
Tcssetup
250
−
−
ns
Clock Frequency
5
FCLK
−
−
5.0
MHz
CLOCK tr and tf
5
trCLK, tfCLK
10
−
−
ns
Internal Register Clear
−
tclear
10
30
−
ns
Internal Power on Reset Width
−
tPOR
−
100
−
ms
Pin
Symbol
Min
Typ
Max
Unit
Output Voltage Range Reference @ 2.5 mA < Iref < 65 mA (Note 3)
1
Vref
1.20
1.24
1.28
V
Maximum Output Current Range Ratio
8
Iout
−
5595
−
−
Minimum Output Current Range Ratio
8
Iout
−
1119
−
−
10, 9
Rs
−
1.8
5.0
W
Rating
2. Digital inputs undershoot < − 0.30 V, Digital inputs overshoot < 0.30 V.
ANALOG SECTION (−25°C to +85°C ambient temperature, unless otherwise noted.)
Rating
Output Current Sense Resistor
Output Voltage Range Reference @ 2.5 mA < Ipho < 65 mA
2
Vpho
1.20
1.24
1.28
V
Output Current Stabilization tdelay following a DC/DC startup
8
Ioutdly
−
100
−
ms
Internal NMOS Resistor @ Vbat = 3.6 V
8
QRDSON
−
2.2
3.0
W
Internal Comparator Delay Time
−
Tdcomp
−
60
−
ns
3. The overall tolerance depends upon the accuracy of the external resistor. Using a 1%/low PPM metal film resistor is recommended to achieve
"5% output current tolerance.
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5
NCP5008, NCP5009
TYPICAL OPERATING CHARACTERISTICS
80
80
75
75
Vbat = 4.2 V
EFFICIENCY (%)
EFFICIENCY (%)
Condition: Typical Application: L = 22 mH, Cin = 10 mF, Cout = 2.2 mF, R1 = 30 kW
70
Vbat = 3.6 V
65
60
55
Vbat = 4.2 V
Vbat = 3.6 V
70
65
60
55
Vbat = 3.0 V
Vbat = 3.0 V
50
50
0
5
10
15
20
25
30
35
0
5
10
15
ILED (mA)
20
25
30
35
ILED (mA)
Figure 4. Efficiency vs. Load Current @ 3 LEDS
(Vload = 3*Vf ⇒ 10.5 V)
Figure 3. Efficiency vs. Load Current @ 4 LEDS
(Vload = 4*Vf ⇒ 14.2 V)
100
85
Vbat = 4.2 V
90
Vbat = 3.6 V
75
EFFICIENCY (%)
EFFICIENCY (%)
80
Vbat = 3.0 V
70
Vout =7.5 V
Iled = 40 mA
80
Vout = 15 V
Iled = 20 mA
70
60
65
50
2.5
60
0
5
10
15
20
25
30
35
3.0
3.5
4.0
4.5
5.0
5.5
ILED (mA)
Vbat (V)
Figure 5. Efficiency vs. Load Current @ 2 LEDS
(Vload = 2*Vf ⇒ 7.1 V)
Figure 6. Efficiency vs. Vbat @
Vout = 15 V/Iled = 20mA and
Vout = 7.5 V/Iled = 40 mA
100
400
Vbat = 6.0 V
300
7
6
250
5
Ipeak (mA)
EFFICIENCY (%)
95
5.0 V
4.2 V
85
4
200
3
150
2
100
80
6.5
Bn
350
90
6.0
1
50
3.6 V
3.0 V
75
0
10
20
30
40
50
60
0
0
70
20
40
60
ILED (mA)
Iref (mA)
Figure 7. Efficiency vs. Load Current @ 4 LEDS
(Vload = 2 strings of 2 LEDs in series = 7.1V)
Figure 8. Inductor peak Current vs.
Iref @ Bn = {1, 2, 3, 4, 5, 6, 7}
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80
NCP5008, NCP5009
TYPICAL OPERATING CHARACTERISTICS
Condition: Typical Application: L = 22 mH, Cin = 10 mF, Cout = 2.2 mF, R1 = 30 kW
50
20
18
Vload = 10 V
40
16
35
14
Ipeak ERROR (%)
ILED (mA)
45
30
Vload = 15 V
25
20
15
12
10
8
6
10
4
5
2
0
0
10
20
30
40
50
60
0
0
70
50
100
150
200
250
300
350
Iref (mA)
THEORETICAL Ipeak (mA)
Figure 9. Load Current (Iled) vs. Iref
@ Vbat = 3.6 V, Vload = 15 V and 10 V
Figure 10. Inductor Peak Current Error vs.
Theoretical Inductor Peak Current
400
7.0
200
180
6.5
Theoretical
160
6.0
Measured
120
Istby (mA)
Ipeak (mA)
140
100
80
5.5
5.0
4.5
60
4.0
40
3.5
20
3.0
2.4
0
0
10
20
30
40
2.8
3.2
3.6
Iphoto (mA)
4.8
5.2
5.6
6.0
Figure 12. Stand by Current vs. Vbat @ T = 20°C
80
85
75
80
Vbat = 4.2 V
70
EFFICIENCY (%)
EFFICIENCY (%)
4.4
Vbat (V)
Figure 11. Inductor Peak Current vs. Iphoto @ Iref = 34 mA
65
60
Vbat = 4.2 V
75
Vbat = 3.6 V
70
65
60
Vbat = 3.6 V
55
4.0
Vbat = 3.0 V
55
Vbat = 3.0 V
50
50
0
5
10
15
20
25
30
35
0
ILED (mA)
5
10
15
20
25
30
35
ILED (mA)
Figure 14. Efficiency vs. Load Current @ 3 LEDS
(Vload = 3*Vf ⇒ 10.5 V)
Figure 13. Efficiency vs. Load Current @ 4 LEDS
(Vload = 4*Vf ⇒ 14.2 V)
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NCP5008, NCP5009
TYPICAL OPERATING CHARACTERISTICS
Condition: Typical Application: L = 22 mH, Cin = 10 mF, Cout = 2.2 mF, R1 = 30 kW
90
100
Vbat = 6.0 V
Vbat = 4.2 V
95
EFFICIENCY (%)
EFFICIENCY (%)
85
Vbat = 3.6 V
80
75
Vbat = 3.0 V
70
5.0 V
90
4.2 V
85
80
3.6 V
65
75
60
70
3.0 V
0
5
10
15
20
25
30
35
0
10
20
30
40
50
60
70
ILED (mA)
ILED (mA)
Figure 15. Efficiency vs Load Current @ 2 LEDS
(Vload = 2*Vf ⇒ 7.1 V)
Figure 16. Efficiency vs Load Current @ 4 LEDS
(Vload = 2 strings of 2 LEDs in series = 7.1 V)
Operating Description
Output
tCLKmin
Vbat
ON
90%
50%
10%
tf
tr
OFF
Input
0.30* Vbat
Figure 17. Digital Timing Definitions
0.70* Vbat
Vbat
Figure 18. Typical Schmitt Trigger Characteristic
Input Schmitt Triggers
All the Logic Input pins have built−in Schmitt trigger
circuits to prevent the NCP5008/NCP5009 against
uncontrolled operation. The typical dynamic characteristics
of the related pins are depicted in Figure 18.
The output signal is guaranteed to go High when the
input voltage is above 0.70*Vbat, and will go Low when the
input voltage is below 0.30*Vbat.
the current drawn pin 1. The clock signal is irrelevant and
the output current is derived by equation Iout = Iref * k, the
internal constant k being equal to 746.
ESD Protection
The NCP5008/NCP5009 includes silicon devices to
protect the pins against the ESD spikes voltages. To cope
with the different ESD voltages developed in the
applications, the built−in structures have been designed to
handle $2.0 kV in Human Body Model (HBM) and
$200 V in Machine Model (MM) and on each pin.
Local Mode
When the system operate in a Local Mode (Pin 6,
/LOCAL=Low), the output current depends solely upon
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NCP5008, NCP5009
Remote Control Programming Sequence
tCSsetup
CS
tclear
CLEAR
CLK
Qdata
B1
B2
B3
B4
B5
Last Latched Bit
B6
B7
Iout ref
Output Current Programmed Register
Internal Latch Data and Reset
Ioutdly
Iout
Figure 19. Programming Sequence
Upon CS transition from High to Low, the internal
sequence will take place:
− Qdata is internally set to high level.
− Upon positive going transition of the next CLK signal,
the Qdata is shifted to the next Bn stage.
− Clear the Qdata flip−flop upon the positive going of
the SetReg[B1] transient.
The sequence keeps going until CS = High.
When the CS line returns to a High state, the
programming output current flip−flop is set according to
the previous state of the shift register and SetReg B[1−7] is
cleared afterward.
Depending upon the CS width, for a given CLK period,
the last SetReg bit will be latched and the output current
will be adjusted accordingly. If the number of CLK pulses
is higher than 7, the Qdata is lost and the SetReg register
bits B[1−7] are in the Low state, yielding a zero output
current.
The internal shift register can be clear by sending more
than 7 pulses to the CLK pin when the pin CS is low. If the
internal shift register is clear upon the CS transition from
Low to High, the device will be placed or maintained in the
shut down mode.
When the register content is higher than zero, the DC/DC
is activated and a 100 ms delay (typical) is necessary to
stabilize the output current to the programmed value.
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NCP5008, NCP5009
Set Up Output Current Range
Vbat
1
1
Vbat
+
Iref
BandGap
−
Vbat
GND
Iref
GND
1
Vbat
Rref
30 k
1:746
Iphoto
1
Iout Reference
= (Iref−Iphoto)*746*(Bn+0.5)
1
I = (Iref−Iphoto)*(Bn+0.5)
Vbat
1
+
−
1
1
1:Bn
2:1
BandGap
GND
GND GND
GND
GND
GND
Photo
Q1
NPN−PHOTO
GND
Figure 20. Functional Diagram
The current sunk to ground on PHOTO pin is subtracted
from the current sunk to ground on Iref pin. The result is
multiplied by the programmed value (Bn) and then
multiplied by the constant factor ratio (k = 746) in the
current mirror.
The constant factor k is a ratio between the current on
Iout sense and the Iout reference internally fixed.
The output current reference is:
Ipeak = Ivalley + (Iref − Iphoto) * Bn * k.
Where k = 746, Bn represents the bit of the internal shift
register, range from 1 to 7, and Ivalley = (Iref − Iphoto)
* 0.5 * k.
We can write also Ipeak = (Iref − Iphoto) * (Bn + 0.5) * k.
Please find below the formula to quickly calculate R1
resistor (resistor on Iref pin):
Iref + 1.24
R1
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NCP5008, NCP5009
DC/DC Converter Operation
The DC/DC converter operates with a boost structure
depicted in Figure 21, the load being supplied by the pulsed
current coming from the external inductor L1. The current
is monitored by the internal sense resistor Rsense to Set and
Reset the flip−flop U3 and U6 according to the comparators
U2 and U4 output state.
Vbat
Vbat
Vbat
+
U1
−
Rsense
1R8
L1
Vbat
GND
L1
22 mH
+
U2
−
Ipeak_ref
U3
L2
Vbat
+
U4
−
Ivalley_ref
D5
MBR0520
GND
U5
U6
D4
LED
Q1
U7
D3
LED
GND
GND
C2
2.2 mF/16 V
POR
D2
LED
D1
LED
GND
GND
Figure 21. Basic DC/DC Boost Structure
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11
NCP5008, NCP5009
Output Load Drive
In order to make profit of the built−in Boost capabilities,
one shall operate the NCP5008/NCP5009 in the continuous
output current mode. Such a mode is achieved by using and
external reservoir capacitor (preferably a low ESR ceramic
type) across the LED as depicted in Figures 22, 23, 24, 25,
and 26.
Using an extra photo sensor is not mandatory and the
related pin 2 can be either left open or connected to Vbat,
but must not be grounded on the NCP5009 version only.
At this point, the designer must carefully analyze two
parameters:
1. The output voltage must be limited to 15 V
maximum. It’s the designer responsibility to
make sure that spike voltages beyond the
maximum rating will not exist across pin 8 and
ground. Depending upon a specific application
(Vbat voltage, PCB layout…), using an external
voltage clamp could be necessary.
2. The peak current flowing into the LED diodes
shall be within the maximum ratings specified for
these devices.
The Schottky diode D5, associated with capacitor C2,
provides a rectification and filtering function.
When a pulse−operating mode is acceptable:
• The LEDs brightness can be controlled in LOCAL
mode with a PWM on CS pin as depicted in Figure 24.
• Or the Schottky can be removed and replaced by at
least one LED diode as depicted in Figure 23.
TYPICAL APPLICATION CIRCUIT
Vbat
C1
U1
R1
1
30 k
2
Iref
Vbat
PHOTO
L1
10 mF/6.3 V
10
GND
9
GND
Vcc
Q1
NPN−PHOTO
L1
22 mH
Vbat
MICROCONTROLLER
GND
4
VBIAS
3
CS
5
CLK
GND
NCP5009
GND
D5
8
7
GND
6
LOCAL
L2
D1
D2
D3
D4
LED
LED
LED
LED
C2
2.2 mF/16 V
GND
Figure 22. Basic DC Current Mode Operation in REMOTE Control
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MBR0520
NCP5008, NCP5009
Vbat
C1
U1
R1
1
30 k
2
GND
Vcc
Q1
NPN−PHOTO
Iref
Vbat
PHOTO
L1
10 mF/6.3 V
10
GND
9
L1
22 mH
Vbat
MICROCONTROLLER
GND
4
VBIAS
3
CS
5
CLK
8
7
GND
6
LOCAL
L2
GND
NCP5009
D3
D4
LED
LED
GND
C2
GND
1.0 mF/16 V
Figure 23. Typical Semi−Pulsed Mode of Operation in REMOTE Mode
Vbat
C1
U1
R1
1
30 k
2
GND
Q1
NPN−PHOTO
Iref
Vbat
PHOTO
L1
10 mF/6.3 V
10
GND
9
L1
22 mH
Vbat
GND
PWM
4
VBIAS
3
CS
5
CLK
D5
8
7
GND
6
LOCAL
L2
NCP5009
GND
D1
D2
D3
D4
LED
LED
LED
LED
C2
2.2 mF/16 V
GND
Figure 24. PWM Current Control Mode Operation in LOCAL Mode
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MBR0520
NCP5008, NCP5009
Vbat
C1
U1
R1
1
DAC
30 k
2
Q1
NPN−PHOTO
Iref
PHOTO
10 mF/6.3 V
10
Vbat
GND
9
L1
L1
22 mH
Vbat
GND
4
VBIAS
3
CS
5
CLK
OFF ON
D5
8
7
GND
6
LOCAL
L2
MBR0520
NCP5009
GND
D1
D2
D3
D4
LED
LED
LED
LED
C2
2.2 mF/16 V
GND
Figure 25. DAC Current Control Mode Operation in LOCAL Mode
Vbat
C1
U1
R1
1
30 k
2
GND
Q1
NPN−PHOTO
Iref
Vbat
PHOTO
L1
10 mF/6.3 V
10
GND
9
L1
22 mH
Vbat
GND
OFF ON
4
VBIAS
3
CS
5
CLK
D5
8
7
GND
6
LOCAL
L2
NCP5009
GND
D1
D2
D3
D4
LED
LED
LED
LED
C2
GND
2.2 mF/16 V
Figure 26. Basic DC Current Mode Operation in LOCAL Mode
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MBR0520
NCP5008, NCP5009
TYPICAL LEDS LOAD MAPPING
75 mA
Load+
D1
LED
D3
LED
D5
LED
D7
LED
D9
LED
D2
LED
D4
LED
D6
LED
D8
LED
D10
LED
6.7 V
Example 1
GND
50 mA
Load+
D1
LED
D4
LED
D7
LED
D2
LED
D5
LED
D8
LED
D3
LED
D6
LED
D9
LED
60 mA
Load+
D1
LED
D3
LED
D5
LED
D2
LED
D4
LED
D6
LED
10.4 V
6.7 V
GND
Example 2
GND
Example 3
Figure 27. Three different examples of load can be driven by the NCP5009 or NCP5008
Condition: Vbat = 3.6 V, L = 22 mH
MANUFACTURER REFERENCE
Design Ref
Value/Reference or Size
Manufacturer
Reference Number
D5
MBR0520/SOD−123
ON Semiconductor
MBR0520
L1
22 mH/1210
MURATA
LQH3C220K34
C1
10 mF/ 6.3 V/0805
MURATA
GRM40 X5R 106K 6.3
C2
2.2 mF/16 V/1206
MURATA
GRM42−6 X7R 225K 16
Q1
SFH320/PLCC2
Osram
SFH320
D1 to D4
White LED
Osram
LW5413−VBW−1
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NCP5008, NCP5009
LAYOUT EXAMPLE
Figure 28. Typical Printed Circuit Layout
(the Top Silk Screen and the Top Layer)
The Figure 28 represents the typical printed circuit
layout based on the basic application Figure 1. This
application has been routed on a single copper layer to save
cost. A dual side PCB has better noise protection and can
be the right choice for an industrial system. In order to
avoid voltage spikes, care must be observed to group the
capacitors, the inductor, the Schottky diode and the
integrated circuit in the same area. On the other hand, using
large copper tracks to reduce the resistor connectivity is
strongly recommended.
Obviously, the connectors GND, CLK, CS, Vbat and
Load are for engineering purpose only and not for final
application.
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16
NCP5008, NCP5009
PACKAGE DIMENSIONS
Micro10
CASE 846B−03
ISSUE D
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION “A” DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE
BURRS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
4. DIMENSION “B” DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. 846B−01 OBSOLETE. NEW STANDARD
846B−02
−A−
−B−
K
D 8 PL
0.08 (0.003)
PIN 1 ID
G
0.038 (0.0015)
−T−
SEATING
PLANE
M
T B
S
A
DIM
A
B
C
D
G
H
J
K
L
S
C
H
L
J
MILLIMETERS
MIN
MAX
2.90
3.10
2.90
3.10
0.95
1.10
0.20
0.30
0.50 BSC
0.05
0.15
0.10
0.21
4.75
5.05
0.40
0.70
INCHES
MIN
MAX
0.114
0.122
0.114
0.122
0.037
0.043
0.008
0.012
0.020 BSC
0.002
0.006
0.004
0.008
0.187
0.199
0.016
0.028
SOLDERING FOOTPRINT*
10X
1.04
0.041
0.32
0.0126
3.20
0.126
8X
10X
4.24
0.167
0.50
0.0196
SCALE 8:1
5.28
0.208
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any
liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental
damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over
time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under
its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body,
or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death
may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees,
subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of
personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part.
SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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NCP5008/D