NCV1124 Dual Variable−Reluctance Sensor Interface IC The NCV1124 is a monolithic integrated circuit designed primarily to condition signals from sensors used to monitor rotating parts. The NCV1124 is a dual channel device. Each of the two identical channels interfaces with a variable−reluctance sensor, and continuously compares the sensor output signal to a user−programmable internal reference. An alternating input signal of appropriate amplitude at IN1 or IN2 will result in a rectangular waveform at the corresponding OUT terminal, suitable for interface to either standard microprocessors or standard logic families. A diagnostic input, common to both channels, provides a means to test for degradation or loss of the physical connector to both sensors. http://onsemi.com 8 1 SO−8 CASE 751 Typical Applications • • • • Anti−Skid Braking and Traction Control Vehicle Stability Control Drive Belt Slippage Detection Crankshaft/Camshaft Position Sensing MARKING DIAGRAM 8 V1124 ALYW4 G Features • • • • • • Two Independent Channels Internal Hysteresis Built−In Diagnostic Mode Designed to Work from a 5.0 V "10% Supply Site and Control for Automotive Applications Pb−Free Packages are Available 1 V1124 A L Y W G VCC VCC VCC VCC OUT1 To mP DIAG R1 RRS PIN CONNECTIONS VCC INP1 INAdj IN1 + − C1 Active Clamp 8 VCC IN1 IN2 OUT1 OUT2 GND DIAG ORDERING INFORMATION Variable Reluctance Sensor RRS 1 INAdj COMP1 VRS R2 = Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package VCC VCC OUT2 To mP INP2 See detailed ordering and shipping information in the package dimensions section on page 3 of this data sheet. IN2 C2 + − Active Clamp COMP2 VRS Variable Reluctance Sensor GND RAdj Figure 1. Block Diagram © Semiconductor Components Industries, LLC, 2006 April, 2006 − Rev. 0 1 Publication Order Number: NCV1124/D NCV1124 MAXIMUM RATINGS Rating Value Unit Storage Temperature Range −65 to 150 °C Ambient Operating Temperature −40 to 125 °C Supply Voltage Range (continuous) −0.3 to 7.0 V Input Voltage Range (at any input, R1 = R2 = 22 k) −250 to 250 V Maximum Junction Temperature 150 °C ESD Susceptibility (Human Body Model) 2.0 kV 240 peak °C Lead Temperature Soldering: Reflow: (SMD styles only) (Note 1) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. 60 second maximum above 183°C. ELECTRICAL CHARACTERISTICS (4.5 V < VCC < 5.5 V, −40°C < TA < 125°C, VDIAG = 0; unless otherwise specified.) Characteristic Test Conditions Min Typ Max Unit VCC = 5.0 V − − 5.0 mA Input Threshold − Positive VDIAG = Low VDIAG = High 135 135 160 160 185 185 mV mV Input Threshold − Negative VDIAG = Low VDIAG = High −185 135 −160 160 −135 185 mV mV Input Bias Current (INP1, INP2) VIN = 0.336 V −16 −11 −6.0 mA Input Bias Current (DIAG) VDIAG = 0 V − − 1.0 mA Input Bias Current Factor (KI) (INAdj = INP × KI) VIN = 0.336 V, VDIAG = Low VIN = 0.336 V, VDIAG = High − 152 100 155 − 157 %INP %INP Bias Current Matching INP1 or INP2 to INAdj, VIN = 0.336 V −1.0 0 1.0 mA Input Clamp − Negative IIN = −50 mA IIN = −12 mA −0.5 −0.5 −0.25 −0.30 0 0 V V Input Clamp − Positive IIN = +12 mA 5.0 7.0 9.8 V Output Low Voltage IOUT = 1.6 mA − 0.2 0.4 V Output High Voltage IOUT = −1.6 mA VCC − 0.5 VCC − 0.2 − V 0 − 20 ms VCC SUPPLY Operating Current Supply Sensor Inputs Mode Change Time Delay − Input to Output Delay IOUT = 1.0 mA − 1.0 20 ms Output Rise Time CLOAD = 30 pF − 0.5 2.0 ms Output Fall Time CLOAD = 30 pF − 0.05 2.0 ms Open−Sensor Positive Threshold VDIAG = High, RIN(Adj) = 40 k. Note 2 29.4 54 86.9 kW DIAG Input Low Threshold − − − 0.2 × VCC V DIAG Input High Threshold − 0.7 × VCC − − V 8.0 8.0 22 22 70 70 kW kW Logic Inputs DIAG Input Resistance VIN = 0.3 × VCC , VCC = 5.0 V VIN = VCC, VCC = 5.0 V 2. This parameter is guaranteed by design, but not parametrically tested in production. http://onsemi.com 2 NCV1124 PACKAGE PIN DESCRIPTION PIN # SO−8 PIN SYMBOL FUNCTION 1 INAdj External resistor to ground that sets the trip levels of both channels. Functions for both diagnostic and normal mode 2 IN1 Input to channel 1 3 IN2 Input to channel 2 4 GND Ground 5 DIAG Diagnostic mode switch. Normal mode is low 6 OUT2 Output of channel 2 7 OUT1 Output of channel 1 8 VCC Positive 5.0 volt supply input ORDERING INFORMATION Device Shipping † Package NCV1124DG SO−8 NB (Pb−Free) 98 Units / Rail NCV1124DR2G SO−8 NB (Pb−Free) 2500 Units / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. VCC VCC VCC VCC VCC INP1 DIAG R1 RRS VRS OUT1 To mP INAdj IN1 C1 + − Active Clamp COMP1 Variable Reluctance Sensor GND RAdj Figure 2. Application Diagram http://onsemi.com 3 NCV1124 THEORY OF OPERATION INP1 + INAdj NORMAL OPERATION Figure 2 shows one channel of the NCV1124 along with the necessary external components. Both channels share the INAdj pin as the negative input to a comparator. A brief description of the components is as follows: VRS − Ideal sinusoidal, ground referenced, sensor output − amplitude usually increases with frequency, depending on loading. RRS − Source impedance of sensor. R1/RAdj − External resistors for current limiting and biasing. INP1/INAdj − Internal current sources that determine trip points via R1/RAdj. COMP1 − Internal comparator with built−in hysteresis set at 160 mV. OUT1 − Output 0 V − 5.0 V square wave with the same frequency as VRS. By inspection, the voltage at the (+) and (−) terminals of COMP1 with VRS = 0V are: V+ + INP1(R1 ) RRS) V− + INAdj (9) We can now re−write equation (7) as: VRS(+TR) u INP1(RAdj * R1 * RRS) ) VHYS (10) By making RAdj + R1 ) RRS (11) you can detect signals with as little amplitude as VHYS. A design example is given in the applications section. OPEN SENSOR PROTECTION The NCV1124 has a DIAG pin that when pulled high (5.0 V), will increase the INAdj current source by roughly 50%. Equation (7) shows that a larger VRS(+TRP) voltage will be needed to trip comparator COMP1. However, if no VRS signal is present, then we can use equations 1, 2, and 4 (equation 5 does not apply in this mode) to get: INP1(R1 ) RRS) u INP1 KI RAdj ) VHYS (12) (1) RAdj Since RRS is the only unknown variable we can solve for RRS, (2) As VRS begins to rise and fall, it will be superimposed on the DC biased voltage at V+. RRS + INP1 KI RAdj ) VHYS * R1 INP1 (13) To get comparator COMP1 to trip, the following condition is needed when crossing in the positive direction, Equation (13) shows that if the output switches states when entering the diag mode with VRS = 0, the sensor impedance must be greater than the above calculated value. This can be very useful in diagnosing intermittent sensor. V+ u V− ) VHYS INPUT PROTECTION V+ + INP1(R1 ) RRS) ) VRS (3) (4) (VHYS is the built−in hysteresis set to 160 mV), or when crossing in the negative direction, V+ t V− * VHYS As shown in Figure 2, an active clamp is provided on each input to limit the voltage on the input pin and prevent substrate current injection. The clamp is specified to handle ±12 mA. This puts an upper limit on the amplitude of the sensor output. For example, if R1 = 20 k, then (5) Combining equations 2, 3, and 4, we get: INP1(R1 ) RRS) ) VRS u INAdj RAdj ) VHYS VRS(MAX) + 20 k (6) Therefore, the VRS(pk−pk) voltage can be as high as 480 V. The NCV1124 will typically run at a frequency up to 1.8 MHz if the input signal does not activate the positive or negative input clamps. Frequency performance will be lower when the positive or negative clamps are active. Typical performance will be up to a frequency of 680 kHz with the clamps active. therefore, VRS(+TRP) t INAdj RAdj * INP1(R1 ) RRS) ) VHYS (7) It should be evident that tripping on the negative side is: VRS(−TRP) t INAdj 12 mA + 240 V RAdj * INP1(R1 ) RRS) * VHYS (8) In normal mode, http://onsemi.com 4 NCV1124 CIRCUIT DESCRIPTION Figure 3 shows the part operating near the minimum input thresholds. As the sin wave input threshold is increased, the low side clamps become active (Figure 4). Increasing the amplitude further (Figure 5), the high−side clamp becomes active. These internal clamps allow for voltages up to −250 V and 250 V on the sensor side of the setup (with R1 = R2 = 22 k) (reference the diagram page 1). Figure 6 shows the effect using the diagnostic (DIAG) function has on the circuit. The input threshold (negative) is switched from a threshold of −160 mV to +160 mV when DIAG goes from a low to a high. There is no hysteresis when DIAG is high. OUT1, 2.0 V/div IN1, 5.0 V/div 20 ms/div Figure 5. Low− and High−Side Clamps IN1, 200 mV/div DIAG 5.0 V/div OUT1, 2.0 V/div IN1 1.0 V/div OUT1 5.0 V/div 20 ms/div Figure 3. Minimum Threshold Operation 20 ms/div OUT1, 2.0 V/div Figure 6. Diagnostic Operation IN1, 5.0 V/div 20 ms/div Figure 4. Low−Side Clamp http://onsemi.com 5 NCV1124 APPLICATION INFORMATION 5. Calculate C1 for low pass filtering Referring to Figure 2, the following will be a design example given these system requirements: Since the sensor guarantees 40 Vpk−pk @ 10 kHz, a low pass filter using R1 and C1 can be used to eliminate high frequency noise without affecting system performance. RRS + 1.5 kW (u 12 kW is considered open) VRS(MAX) + 120 Vpk Gain Reduction + 0.29 V + 0.0145 + *36.7 dB 20 V VRS(MIN) + 250 mVpk Therefore, a cut−off frequency, fC, of 145 Hz could be used. FVRS + 10 kHz @ VRS(MIN) + 40 Vpk−pk C1 v 1. Determine tradeoff between R1 value and power rating. (use 1/2 watt package) PD + ǒ Ǔ 120 2 Ǹ2 R1 Set C1 = 0.047 mF. 6. Calculate the minimum RRS that will be indicated as an open circuit. (DIAG = 5.0 V) Rearranging equation (7) gives t 1ń2 W ƪ VHYS ) [INP1 * VRS(+TRP) Set R1 = 15 k. (The clamp current will then be 120/15 k = 8.0 mA, which is less than the 12 mA limit.) RRS + 2. Determine RAdj KI RAdj] ƫ * R1 INP1 But, VRS = 0 during this test, so it drops out. Using the following as worst case Low and High: Set RAdj as close to R1 + RRS as possible. Therefore, RAdj = 17 k. 3. Determine VRS(+TRP) using equation (7). VRS(+TRP) + 11mA 1 v 0.07 mF 2pfCR1 INAdj 17 k * 11mA(15 k ) 1.5 k) ) 160 m VRS(+TRP) + 166 mV typical (easily meets 250 mV minimum) Worst Case Low (RRS) Worst Case High (RRS) 23.6 mA = 15 mA × 1.57 10.7 mA = 7.0 mA × 1.53 RAdj 16.15 k 17.85 k VHYS 135 mV 185 mV 16 mA 6.0 mA R1 15.75 k 14.25 k KI 1.57 1.53 INP1 4. Calculate worst case VRS(+TRP) Examination of equation (7) and the spec reveals the worst case trip voltage will occur when: VHYS = 180 mV INAdj = 16 mA INP1 = 15 mA R1 = 14.25 k (5% low) RAdj = 17.85 k (5% High) 135 mV ) 23.6 mA 16 mA + 16.5 k RRS + 16.15 k * 15.75 k Therefore, RRS(MIN) + 16.5 k (meets 12 k system spec) VRS(+)MAX + 16 mA(17.85 k) * 15mA(14.25 k ) 1.5 k) ) 180 mV + 229 mV and, 185 mV ) 10.7 mA 6.0mA + 48.4 k RRS(MAX) + which is still less than the 250 mV minimum amplitude of the input. http://onsemi.com 6 17.85 k * 14.25 k NCV1124 PACKAGE DIMENSIONS SO−8 NB CASE 751−07 ISSUE AG −X− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A 8 5 0.25 (0.010) S B 1 M Y M 4 K −Y− G C N DIM A B C D G H J K M N S X 45 _ SEATING PLANE −Z− 0.10 (0.004) H D 0.25 (0.010) M Z Y S X M J S MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. PACKAGE THERMAL DATA Parameter SO−8NB Unit RqJC Typical 45 °C/W RqJA Typical 165 °C/W http://onsemi.com 7 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 NCV1124 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. 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