PYRAMID P4C1256

P4C1256
HIGH SPEED 32K x 8
STATIC CMOS RAM
FEATURES
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Fast tOE
Automatic Power Down
Packages
—28-Pin 300 mil DIP, SOJ, TSOP
—28-Pin 300 mil Ceramic DIP
—28-Pin 600 mil Ceramic DIP
—28-Pin CERPACK
—28-Pin SOP
—28-Pin LCC (350 mil x 550 mil)
—32-Pin LCC (450 mil x 550 mil)
High Speed (Equal Access and Cycle Times)
— 12/15/20/25/35 ns (Commercial)
— 15/20/25/35/45 ns (Industrial)
— 20/25/35/45/55/70 ns (Military)
Low Power
Single 5V±10% Power Supply
Easy Memory Expansion Using CE and OE
Inputs
Common Data I/O
Three-State Outputs
DESCRIPTION
The P4C1256 device provides asynchronous operation
with matching access and cycle times. Memory locations are specified on address pins A0 to A14. Reading
is accomplished by device selection (CE and output
enabling (OE) while write enable (WE) remains HIGH.
By presenting the address under these conditions, the
data in the addressed memory location is presented on
the data input/output pins. The input/output pins stay
in the HIGH Z state when either CE or OE is HIGH or
WE is LOW.
The P4C1256 is a 262,144-bit high-speed CMOS
static RAM organized as 32Kx8. The CMOS memory
requires no clocks or refreshing, and has equal access
and cycle times. Inputs are fully TTL-compatible. The
RAM operates from a single 5V±10% tolerance power
supply.
Access times as fast as 12 nanoseconds permit greatly
enhanced system operating speeds. CMOS is utilized
to reduce power consumption to a low level. The
P4C1256 is a member of a family of PACE RAM™ products offering fast access times.
Package options for the P4C1256 include 28-pin 300
mil DIP, SOJ and TSOP packages. For military temperature range, Ceramic DIP and LCC packages are available.
PIN CONFIGURATIONS
FUNCTIONAL BLOCK DIAGRAM
DIP (P5, C5, C5-1, D5-2), SOJ (J5), SOP (S11-1, S11-3)
CERPACK (F4) SIMILAR
1519B
See end of datasheet
for LCC and TSOP
pin configurations.
Document # SRAM119 REV G
1
Revised June 2007
P4C1256
MAXIMUM RATINGS(1)
Symbol
Parameter
Value
Unit
V CC
Power Supply Pin with
Respect to GND
–0.5 to +7
V
V TERM
Terminal Voltage with
Respect to GND
(up to 7.0V)
–0.5 to
VCC +0.5
V
TA
Operating Temperature
–55 to +125
°C
Symbol
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade(2)
Ambient
Temperature
Parameter
Temperature Under
Bias
–55 to +125
°C
TSTG
Storage Temperature
–65 to +150
°C
PT
Power Dissipation
1.0
W
IOUT
DC Output Current
50
mA
CAPACITANCES(4)
VCC = 5.0V, TA = 25°C, f = 1.0MHz
VCC
Symbol
Parameter
0V
0V
0V
5.0V ± 10%
5.0V ± 10%
5.0V ± 10%
CIN
Input Capacitance
–55°C to +125°C
–40°C to +85°C
Industrial
Commercial
0°C to +70°C
Unit
TBIAS
GND
Military
Value
COUT
Conditions Typ. Unit
VIN = 0V
8
pF
Output Capacitance VOUT = 0V
10
pF
DC ELECTRICAL CHARACTERISTICS
Over recommended operating temperature and supply voltage(2)
Symbol
Parameter
VIH
Input High Voltage
VIL
Input Low Voltage
V HC
CMOS Input High Voltage
CMOS Input Low Voltage
VOL
Output Low Voltage
(TTL Load)
IOL = +8 mA, VCC = Min.
VOH
Output High Voltage
(TTL Load)
IOH = –4 mA, VCC = Min.
Input Leakage Current
–0.5
VCC = Max.
(3)
0.2
–0.5
(3)
0.4
–10
0.4
V
V
+10
–5
+5
n/a
Ind./Com’l.
–5
+5
Mil.
–10
+10
–5
+5
Ind./Com’l.
–5
+5
n/a
n/a
Mil.
___
45
___
30
Standby Power Supply
VCC= Max,
Ind./Com’l.
Current (TTL Input Levels) f = Max., Outputs Open
___
30
___
n/a
Mil.
___
20
___
10
Ind./Com’l.
___
10
___
n/a
Output Leakage Current
CE = VIH,
V
V
n/a
VIN = GND to VCC
V
0.2
2.4
2.4
Mil.
VCC = Max.,
ILO
P4C1256L
Unit
Min
Max
VCC +0.5 V
2.2
0.8
0.8
–0.5(3)
–0.5(3)
VCC –0.2 VCC +0.5 VCC –0.2 VCC +0.5
VLC
ILI
P4C1256
Min
Max
V
+0.5
2.2
CC
Test Conditions
µA
µA
VOUT = GND to VCC
CE ≥ VIH
ISB
CE ≥ VHC
ISB1
Standby Power Supply
Current
(CMOS Input Levels)
VCC= Max,
mA
mA
f = 0, Outputs Open
VIN ≤ VLC or VIN ≥ VHC
N/A = Not Applicable
Document # SRAM119 REV G
Page 2 of 17
P4C1256
DATA RETENTION CHARACTERISTICS (P4C1256L Military Temperature Only)
Symbol
Parameter
Test Conditons
V DR
VCC for Data Retention
ICCDR
Data Retention Current
CE ≥ VCC –0.2V,
t CDR
Chip Deselect to
Data Retention Time
VIN ≥ VCC –0.2V
tR †
Operation Recovery Time
Min
Typ.*
VCC =
2.0V
3.0V
Max
VCC =
2.0V
3.0V
V
2.0
10
or VIN ≤ 0.2V
Unit
15
100
200
µA
0
ns
tRC§
ns
*TA = +25°C
§tRC = Read Cycle Time
†
This parameter is guaranteed but not tested.
DATA RETENTION WAVEFORM
POWER DISSIPATION CHARACTERISTICS VS. SPEED
Symbol
ICC
Parameter
Temperature
Range
Commercial
Dynamic Operating Current* Industrial
Military
–12
170
–15
–20
160
N/A
N/A
Unit
155
–25
150
–35
145
–45
N/A
–55
N/A
–70
N/A
170
165
160
155
150
N/A
N/A
mA
N/A
170
165
160
155
150
150
mA
mA
*VCC = 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V. CE = VIL, OE = VIH.
Document # SRAM119 REV G
Page 3 of 17
P4C1256
AC ELECTRICAL CHARACTERISTICS—READ CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
Sym.
-12
Parameter
-15
-20
-25
-35
-45
-55
-70
Unit
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max
t RC
Read Cycle Time
tAA
Address Access
Time
12
15
20
25
35
45
55
70
ns
t AC
Chip Enable
Access Time
12
15
20
25
35
45
55
70
ns
t OH
Output Hold from
Address Change
2
2
2
3
3
3
3
3
ns
tLZ
Chip Enable to
Output in Low Z
2
2
2
3
3
3
3
3
ns
t HZ
Chip Disable to
Output in High Z
5
8
9
11
15
20
25
30
ns
tOE
Output Enable
Low to Data
Valid
5
7
9
10
15
20
25
30
ns
tOLZ
Output Enable
Low to Low Z
t OHZ
Output Enable
High to High Z
t PU
Chip Enable to
Power Up Time
Chip Disable to
Power Down
Time
t PD
12
0
0
5
0
Document # SRAM119 REV G
20
15
0
7
0
12
25
0
9
0
15
35
0
11
0
20
0
15
0
20
55
45
20
ns
30
25
30
ns
ns
0
0
25
ns
0
0
0
20
70
35
ns
Page 4 of 17
P4C1256
OE CONTROLLED)(5)
TIMING WAVEFORM OF READ CYCLE NO. 1 (OE
TIMING WAVEFORM OF READ CYCLE NO. 2 (ADDRESS CONTROLLED)(5,6)
CE CONTROLLED)(5,7)
TIMING WAVEFORM OF READ CYCLE NO. 3 (CE
Notes:
1. Stresses greater than those listed under MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAXIMUM rating conditions for extended
periods may affect reliability.
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. Transient inputs with VIL and IIL not more negative than –3.0V and
–100mA, respectively, are permissible for pulse widths up to 20 ns.
Document # SRAM119 REV G
4. This parameter is sampled and not 100% tested.
5. WE is HIGH for READ cycle.
6. CE is LOW and OE is LOW for READ cycle.
7. ADDRESS must be valid prior to, or coincident with CE transition LOW.
8. Transition is measured ± 200 mV from steady state voltage prior to
change, with loading as specified in Figure 1. This parameter is
sampled and not 100% tested.
9. Read Cycle Time is measured from the last valid address to the first
transitioning address.
Page 5 of 17
P4C1256
AC CHARACTERISTICS—WRITE CYCLE
(VCC = 5V ± 10%, All Temperature Ranges)(2)
Sym.
Parameter
-12
-15
-20
-25
-45
-35
-55
-70
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max
Unit
tWC
Write Cycle Time 12
15
20
25
35
45
55
70
ns
tCW
Chip Enable
Time to End of
Write
Address Valid to
End of Write
Address Set-up
Time
Write Pulse
Width
Address Hold
Time
Data Valid to
End of Write
9
10
15
18
22
30
35
40
ns
9
10
15
20
25
35
40
45
ns
0
0
0
0
0
0
0
0
ns
9
11
15
18
22
25
30
35
ns
0
0
0
0
0
0
0
0
ns
8
9
11
13
15
20
25
30
ns
0
0
0
0
0
0
0
0
ns
tAW
tAS
tWP
tAH
tDW
t DH
Date Hold Time
tWZ
Write Enable to
Output in High Z
tOW
Output Active
from End of Write
7
3
8
3
10
3
11
3
15
5
18
5
25
0
30
0
ns
ns
WE CONTROLLED)(10,11)
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE
Document # SRAM119 REV G
Page 6 of 17
P4C1256
CE CONTROLLED)(10)
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE
Notes:
10. CE and WE must be LOW for WRITE cycle.
11. OE is LOW for this WRITE cycle to show tWZ and tOW.
12. If CE goes HIGH simultaneously with WE HIGH, the output remains
Document # SRAM119 REV G
in a high impedance state
13. Write Cycle Time is measured from the last valid address to the first
transitioning address.
Page 7 of 17
P4C1256
AC TEST CONDITIONS
TRUTH TABLE
Input Pulse Levels
GND to 3.0V
Input Rise and Fall Times
3ns
Input Timing Reference Level
Output Timing Reference Level
Output Load
Mode
CE O E W E
I/O
Power
1.5V
Standby
Standby
H
X
X
X
X
X
High Z
High Z
Standby
Standby
1.5V
DOUT Disabled
L
H
H
High Z
Active
Read
L
L
H
DOUT
Active
Write
L
X
L
High Z
Active
See Figures 1 and 2
Figure 1. Output Load
Figure 2. Thevenin Equivalent
* including scope and test fixture.
Note:
Because of the ultra-high speed of the P4C1256, care must be taken when
testing this device; an inadequate setup can cause a normal functioning part
to be rejected as faulty. Long high-inductance leads that cause supply
bounce must be avoided by bringing the VCC and ground planes directly up
to the contactor fingers. A 0.01 µF high frequency capacitor is also required
between VCC and ground. To avoid signal reflections, proper termination
Document # SRAM119 REV G
must be used; for example, a 50Ω test environment should be terminated
into a 50Ω load with 1.73V (Thevenin Voltage) at the comparator input,
and a 116Ω resistor must be used in series with DOUT to match 166Ω
(Thevenin Resistance).
Page 8 of 17
P4C1256
ORDERING INFORMATION
SELECTION GUIDE
The P4C1256 is available in the following temperature, speed and package options. The P4C1256L is available only
over the military temperature range. **
Temperature
Range
Commercial
Industrial
Speed
Package
12
15
20
25
35
45
55
70
Plastic DIP
-12PC
-15PC
-20PC
-25PC
-35PC
N/A
N/A
N/A
Plastic SOJ
-12JC
-15JC
-20JC
-25JC
-35JC
N/A
N/A
N/A
Plastic TSOP
-12TC
-15TC
-20TC
-25TC
-35TC
N/A
N/A
N/A
Plastic SOP (S11-1)
-12SC
-15SC
-20SC
-25SC
-35SC
N/A
N/A
N/A
Plastic SOP (S11-3)
Plastic DIP
-12SSC
N/A
-15SSC
-15PI
-20SSC
-20PI
-25SSC
-25PI
-35SSC
-35PI
N/A
-45PI
N/A
N/A
N/A
N/A
N/A
Plastic SOJ
N/A
-15JI
-20JI
-25JI
-35JI
-45JI
N/A
Plastic TSOP
N/A
-15TI
-20TI
-25TI
-35TI
-45TI
N/A
N/A
Plastic SOP (S11-1)
N/A
-15SI
-20SI
-25SI
-35SI
-45SI
N/A
N/A
Plastic SOP (S11-3)
N/A
-15SSI
-20SSI
-25SSI
-35SSI
-45SSI
N/A
N/A
* Military temperature range with MIL-STD-883, Class B processing.
** For RoHS compliant plastic products, the suffix "LF" (Lead Free) should be added to the part number.
N/A = Not Available
Document # SRAM119 REV G
Page 9 of 17
P4C1256
SELECTION GUIDE (CONTINUED)
Temperature
Range
Military
Temperature
Military
Processed*
Package
Speed
12
15
20
25
35
45
55
70
Side Brazed DIP (300 mil)
N/A
N/A
-20CM
-25CM
-35CM
-45CM
-55CM
-70CM
Side Brazed DIP (600 mil)
N/A
N/A
-20CWM
-25CWM
-35CWM
-45CWM
-55CWM
-70CWM
Ceramic DIP
N/A
N/A
-20DM
-25DM
-35DM
-45DM
-55DM
-70DM
CERPACK
N/A
N/A
-20FM
-25FM
-35FM
-45FM
-55FM
-70FM
LCC (28-Pin)
N/A
N/A
-20L28M
-25L28M
-35L28M
-45L28M
-55L28M
-70L28M
LCC (32-Pin)
N/A
N/A
-20L32M
-25L32M
-35L32M
-45L32M
-55L32M
-70L32M
Side Brazed DIP (300 mil)
N/A
N/A
-20CMB
-25CMB
-35CMB
-45CMB
-55CMB
-70CMB
Side Brazed DIP (600 mil)
N/A
N/A
-20CWMB
-25CWMB
-35CWMB
-45CWMB
-55CWMB
-70CWMB
-70DMB
Ceramic DIP
N/A
N/A
-20DMB
-25DMB
-35DMB
-45DMB
-55DMB
CERPACK
N/A
N/A
-20FMB
-25FMB
-35FMB
-45FMB
-55FMB
-70FMB
LCC (28-Pin)
N/A
N/A
-20L28MB
-25L28MB
-35L28MB
-45L28MB
-55L28MB
-70L28MB
LCC (32-Pin)
N/A
N/A
-20L32MB
-25L32MB
-35L32MB
-45L32MB
-55L32MB
-70L32MB
LCC PIN CONFIGURATIONS
28 LCC (L5)
32 LCC (L6)
TSOP (T1)
Document # SRAM119 REV G
Page 10 of 17
P4C1256
Pkg #
# Pins
Symbol
A
b
b2
C
D
E
eA
e
L
Q
S1
S2
Pkg #
# Pins
Symbol
A
b
b2
C
D
E
eA
e
L
Q
S1
S2
C5
SIDE BRAZED CERAMIC DUAL IN-LINE PACKAGE (300 Mils)
28 (300 mil)
Min
Max
0.225
0.014
0.026
0.045
0.065
0.008
0.018
1.485
0.240
0.310
0.300 BSC
0.100 BSC
0.125
0.200
0.015
0.070
0.005
0.005
-
C5-1
SIDE BRAZED CERAMIC DUAL IN-LINE PACKAGE (600 Mils)
28 (600 mil)
Min
Max
0.232
0.014
0.026
0.045
0.065
0.008
0.018
1.490
0.500
0.610
0.600 BSC
0.100 BSC
0.125
0.200
0.015
0.060
0.005
0.005
-
Document # SRAM119 REV G
Page 11 of 17
P4C1256
Pkg #
# Pins
Symbol
A
b
b2
C
D
E
eA
e
L
Q
S1
α
Pkg #
# Pins
Symbol
A
b
c
D
E
e
k
L
Q
S
S1
D5-2
CERDIP DUAL IN-LINE PACKAGE
28 (300 mil)
Min
Max
0.225
0.014
0.026
0.045
0.065
0.008
0.018
1.485
0.240
0.310
0.300 BSC
0.100 BSC
0.125
0.200
0.015
0.060
0.005
0°
15°
F4
CERPACK CERAMIC FLAT PACKAGE
28
Min
Max
0.060
0.090
0.015
0.022
0.004
0.009
0.730
0.330
0.380
0.050 BSC
0.005
0.018
0.250
0.370
0.026
0.045
0.085
0.005
-
Document # SRAM119 REV G
Page 12 of 17
P4C1256
Pkg #
# Pins
Symbol
A
A1
b
C
D
e
E
E1
E2
Q
Pkg #
# Pins
Symbol
A
A1
B1
D
D1
D2
D3
E
E1
E2
E3
e
h
j
L
L1
L2
ND
NE
J5
SOJ SMALL OUTLINE IC PACKAGE
28 (300 mil)
Min
Max
0.120
0.148
0.078
0.014
0.020
0.007
0.011
0.700
0.730
0.050 BSC
0.335 BSC
0.292
0.300
0.267 BSC
0.025
-
L5
RECTANGULAR LEADLESS CHIP CARRIER (28 Pins)
28
Min
Max
0.060
0.075
0.050
0.065
0.022
0.028
0.342
0.358
0.200 BSC
0.100 BSC
0.358
0.540
0.560
0.400 BSC
0.200 BSC
0.558
0.050 BSC
0.040 REF
0.020 REF
0.045
0.055
0.045
0.055
0.075
0.095
5
9
Document # SRAM119 REV G
Page 13 of 17
P4C1256
Pkg #
# Pins
Symbol
A
A1
B1
D
D1
D2
D3
E
E1
E2
E3
e
h
j
L
L1
L2
ND
NE
Pkg #
# Pins
Symbol
A
A1
b
b2
C
D
E1
E
e
eB
L
α
L6
RECTANGULAR LEADLESS CHIP CARRIER (32 Pins)
32
Min
Max
0.060
0.075
0.050
0.065
0.022
0.028
0.442
0.458
0.300 BSC
0.150 BSC
0.458
0.540
0.560
0.400 BSC
0.200 BSC
0.558
0.050 BSC
0.040 REF
0.020 REF
0.045
0.055
0.045
0.055
0.075
0.095
7
9
P5
PLASTIC DUAL IN-LINE PACKAGE
28 (300 mil)
Min
Max
0.210
0.014
0.023
0.045
0.070
0.008
0.014
1.345
1.400
0.270
0.300
0.300
0.380
0.100 BSC
0.430
0.115
0.150
0°
15°
Document # SRAM119 REV G
Page 14 of 17
P4C1256
Pkg #
# Pins
Symbol
A
A2
b
D
E
e
HD
Pkg #
# Pins
Symbol
A
A1
b2
C
D
e
E
H
h
L
α
T1
TSOP THIN SMALL OUTLINE PACKAGE (8 x 13.4 mm)
28
Min
Max
0.039
0.047
0.036
0.040
0.007
0.011
0.461
0.469
0.311
0.319
0.022 BSC
0.520
0.535
S11-1
SOIC/SOP SMALL OUTLINE IC PACKAGE
28 (300 Mil)
Min
Max
0.093
0.104
0.004
0.012
0.013
0.020
0.009
0.012
0.696
0.712
0.050 BSC
0.291
0.299
0.394
0.419
0.010
0.029
0.016
0.050
0°
8°
Document # SRAM119 REV G
Page 15 of 17
P4C1256
Pkg #
# Pins
Symbol
A
A1
B
C
D
e
E
H
h
L
α
S11-3
SOIC/SOP SMALL OUTLINE IC PACKAGE
28 (300 Mil)
Min
Max
0.094
0.110
0.002
0.014
0.014
0.020
0.008
0.012
0.702
0.710
0.050 BSC
0.291
0.300
0.463
0.477
0.010
0.029
0.020
0.042
0°
8°
Document # SRAM119 REV G
Page 16 of 17
P4C1256
REVISIONS
DOCUMENT NUMBER:
DOCUMENT TITLE:
SRAM119
HIGH SPEED 32K x 8 STATIC CMOS RAM
REV.
ISSUE
DATE
ORIG. OF
CHANGE
OR
1997
RKK
New Data Sheet
A
Oct-05
JDB
Change logo to Pyramid
B
Oct-05
JDB
Added SOP Package
C
Apr-06
JDB
Added Lead-Free ordering information.
D
May-06
JDB
Added PDIP to Ordering Information diagram
E
Jun-06
JDB
Added Ceramic DIP package
F
Aug-06
JDB
Updated SOJ package information
G
Jun-07
JDB
Corrected SOP package information
Document # SRAM119 REV G
DESCRIPTION OF CHANGE
Page 17 of 17