TI SN74LVC1G98DBVR

SN74LVC1G98
CONFIGURABLE MULTIPLE-FUNCTION GATE
www.ti.com
SCES417H – DECEMBER 2002 – REVISED JUNE 2005
•
FEATURES
•
•
•
•
•
•
Available in the Texas Instruments
NanoStar™ and NanoFree™ Packages
Supports 5-V VCC Operation
Inputs Accept Voltages to 5.5 V
Max tpd of 6.3 ns at 3.3 V
Low Power Consumption, 10-µA Max ICC
±24-mA Output Drive at 3.3 V
DBV PACKAGE
(TOP VIEW)
In1
1
6
Ioff Supports Partial-Power-Down Mode
Operation
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
•
•
DCK PACKAGE
(TOP VIEW)
In1
In2
GND
GND
2
5
VCC
In0
3
4
Y
1
2
6
5
In2
VCC
In1
GND
In0
In0
3
4
YEA, YEP, YZA,
OR YZP PACKAGE
(BOTTOM VIEW)
DRL PACKAGE
(TOP VIEW)
1
2
3
6
5
4
In2
VCC
Y
In0
3 4
Y
GND
2 5
VCC
In1
1 6
In2
Y
See mechanical drawings for dimensions.
DESCRIPTION/ORDERING INFORMATION
This configurable multiple-function gate is designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC1G98 features configurable multiple functions. The output state is determined by eight patterns of
3-bit input. The user can choose the logic functions MUX, AND, OR, NAND, NOR, inverter, and noninverter. All
inputs can be connected to VCC or GND.
ORDERING INFORMATION
PACKAGE (1)
TA
ORDERABLE PART NUMBER
NanoStar™ – WCSP (DSBGA)
0.17-mm Small Bump – YEA
NanoFree™ – WCSP (DSBGA)
0.17-mm Small Bump – YZA (Pb-free)
NanoStar™ – WCSP (DSBGA)
0.23-mm Large Bump – YEP
–40°C to 85°C
SOT (SC-70) – DCK
SOT (SOT-553) – DRL
(1)
(2)
SN74LVC1G98YEAR
SN74LVC1G98YZAR
Reel of 3000
_ _ _CW_
SN74LVC1G98YEPR
NanoFree™ – WCSP (DSBGA)
0.23-mm Large Bump – YZP (Pb-free)
SOT (SOT-23) – DBV
TOP-SIDE MARKING (2)
SN74LVC1G98YZPR
Reel of 3000
SN74LVC1G98DBVR
Reel of 250
SN74LVC1G98DBVT
Reel of 3000
SN74LVC1G98DCKR
Reel of 250
SN74LVC1G98DCKT
Reel of 4000
SN74LVC1G98DRLR
C98_
CW_
CW_
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
DBV/DCK/DRL: The actual top-side marking has one additional character that designates the assembly/test site.
YEA/YZA, YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one
following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar, NanoFree are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2002–2005, Texas Instruments Incorporated
SN74LVC1G98
CONFIGURABLE MULTIPLE-FUNCTION GATE
www.ti.com
SCES417H – DECEMBER 2002 – REVISED JUNE 2005
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
This device functions as an independent gate, but because of Schmitt action, it may have different input
threshold levels for positive-going (VT+) and negative-going (VT–) signals.
NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
FUNCTION TABLE
INPUTS
OUTPUT
Y
In2
In1
L
L
In0
L
H
L
L
H
H
L
H
L
L
L
H
H
L
H
L
L
H
H
L
H
L
H
H
L
H
H
H
H
L
LOGIC DIAGRAM (POSITIVE LOGIC)
In0
3
4
In1
In2
1
6
FUNCTION SELECTION TABLE
LOGIC FUNCTION
2
FIGURE NO.
2-to-1 data selector with inverted output
1
2-input NAND gate
2
2-input NOR gate with one inverted input
3
2-input AND gate with one inverted input
3
2-input NAND gate with one inverted input
4
2-input OR gate with one inverted input
4
2-input NOR gate
5
Noninverted buffer
6
Inverter
7
Y
SN74LVC1G98
CONFIGURABLE MULTIPLE-FUNCTION GATE
www.ti.com
SCES417H – DECEMBER 2002 – REVISED JUNE 2005
LOGIC CONFIGURATIONS
VCC
VCC
A/B
A
A
Y
B
B
1
6
2
5
3
4
A/B
A
Y
B
B
Y
GND
1
6
2
5
3
4
A
Y
GND
Figure 2. 2-Input NAND Gate
Figure 1. 2-to-1 Data Selector With Inverted
Output
VCC
A
VCC
A
A
Y
Y
B
B
Y
B
B
1
6
2
5
3
4
B
A
A
Y
Y
B
1
6
2
5
3
4
A
Y
GND
GND
Figure 3. 2-Input NOR Gate With One Inverted
Input
2-Input AND Gate With One Inverted Input
Figure 4. 2-Input NAND Gate With One
Inverted Input
2-Input OR Gate With One Inverted Input
VCC
VCC
A
Y
1
B
B
6
2
5
3
4
A
A
Y
Y
1
6
2
5
3
4
A
Y
GND
GND
Figure 6. Noninverted Buffer
Figure 5. 2-Input NOR Gate
VCC
A
A
Y
1
6
2
5
3
4
Y
GND
Figure 7. Inverter
3
SN74LVC1G98
CONFIGURABLE MULTIPLE-FUNCTION GATE
www.ti.com
SCES417H – DECEMBER 2002 – REVISED JUNE 2005
Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VCC
Supply voltage range
–0.5
6.5
V
VI
Input voltage range (2)
–0.5
6.5
V
–0.5
6.5
V
–0.5
VCC + 0.5
state (2) (3)
UNIT
VO
Voltage range applied to any output in the high-impedance or power-off
VO
Voltage range applied to any output in the high or low state
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
±100
mA
Continuous current through VCC or GND
θJA
Package thermal impedance (4)
DBV package
165
DCK package
259
DRL package
142
YEA/YZA package
143
YEP/YZP package
Tstg
(1)
(2)
(3)
(4)
Storage temperature range
V
°C/W
123
–65
150
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
The value of VCC is provided in the recommended operating conditions table.
The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions (1)
Operating
MIN
MAX
1.65
5.5
UNIT
VCC
Supply voltage
VI
Input voltage
0
5.5
V
VO
Output voltage
0
VCC
V
Data retention only
1.5
VCC = 1.65 V
–4
VCC = 2.3 V
IOH
High-level output current
–8
–16
VCC = 3 V
Low-level output current
–32
VCC = 1.65 V
4
VCC = 2.3 V
8
16
VCC = 3 V
(1)
4
Operating free-air temperature
mA
24
VCC = 4.5 V
TA
mA
–24
VCC = 4.5 V
IOL
V
32
–40
85
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
°C
SN74LVC1G98
CONFIGURABLE MULTIPLE-FUNCTION GATE
www.ti.com
SCES417H – DECEMBER 2002 – REVISED JUNE 2005
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VT+
Positivegoing input
threshold
voltage
VT–
Negativegoing input
threshold
voltage
∆VT
Hysteresis
(VT+ – VT–)
IOH = –100 µA
VOH
(1)
2.3 V
1.11
1.56
3V
1.5
1.87
4.5 V
2.16
2.74
5.5 V
2.61
3.33
1.65 V
0.35
0.62
2.3 V
0.58
0.87
3V
0.84
1.19
4.5 V
1.41
1.9
5.5 V
1.87
2.29
1.65 V
0.3
0.62
2.3 V
0.4
0.8
3V
0.53
0.87
4.5 V
0.71
1.04
5.5 V
0.71
1.11
1.2
2.3 V
1.9
IOH = –16 mA
4.5 V
IOL = 100 µA
1.65 V to 5.5 V
0.1
IOL = 4 mA
1.65 V
0.45
IOL = 8 mA
2.3 V
0.3
0.4
VI = 5.5 V or GND,
IO = 0
One input at VCC – 0.6 V,
Other inputs at VCC or GND
VI = VCC or GND
V
0.55
4.5 V
VI or VO = 5.5 V
V
3.8
3V
Ioff
V
2.3
IOH = –32 mA
VI = 5.5 V or GND
V
V
2.4
3V
IOL = 16 mA
UNIT
VCC – 0.1
IOH = –8 mA
ICC
Ci
1.16
1.65 V
IOL = 32 mA
∆ICC
0.79
1.65 V to 5.5 V
IOL = 24 mA
II
1.65 V
IOH = –4 mA
IOH = –24 mA
VOL
MIN TYP (1) MAX
VCC
0.55
0 to 5.5 V
±5
µA
0
±10
µA
1.65 V to 5.5 V
10
µA
3 V to 5.5 V
500
µA
3.3 V
3.5
pF
All typical values are at VCC = 3.3 V, TA = 25°C.
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 8)
PARAMETER
tpd
FROM
(INPUT)
TO
(OUTPUT)
Any In
Y
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
3.2
14.4
2
8.3
1.5
6.3
1.1
5.1
UNIT
ns
5
SN74LVC1G98
CONFIGURABLE MULTIPLE-FUNCTION GATE
www.ti.com
SCES417H – DECEMBER 2002 – REVISED JUNE 2005
Operating Characteristics
TA = 25°C
PARAMETER
Cpd
6
Power dissipation capacitance
TEST CONDITIONS
f = 10 MHz
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
VCC = 5 V
TYP
TYP
TYP
TYP
23
23
23
26
UNIT
pF
SN74LVC1G98
CONFIGURABLE MULTIPLE-FUNCTION GATE
www.ti.com
SCES417H – DECEMBER 2002 – REVISED JUNE 2005
PARAMETER MEASUREMENT INFORMATION
VLOAD
RL
From Output
Under Test
CL
(see Note A)
S1
Open
GND
RL
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
VI
tr/tf
VCC
VCC
3V
VCC
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
VM
VLOAD
CL
RL
V∆
VCC/2
VCC/2
1.5 V
VCC/2
2 × VCC
2 × VCC
6V
2 × VCC
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tw
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
tPLH
VM
VM
VOL
tPHL
VM
VM
0V
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
tPLZ
VLOAD/2
VM
tPZH
VOH
Output
VM
tPZL
tPHL
VOH
Output
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
VM
VOH − V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 8. Load Circuit and Voltage Waveforms
7
PACKAGE OPTION ADDENDUM
www.ti.com
3-Jun-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN74LVC1G98DBVR
ACTIVE
SOT-23
DBV
6
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC1G98DBVRG4
ACTIVE
SOT-23
DBV
6
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC1G98DBVT
ACTIVE
SOT-23
DBV
6
250
Pb-Free
(RoHS)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC1G98DBVTE4
ACTIVE
SOT-23
DBV
6
250
TBD
SN74LVC1G98DCKR
ACTIVE
SC70
DCK
6
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC1G98DCKT
ACTIVE
SC70
DCK
6
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVC1G98DCKTE4
ACTIVE
SC70
DCK
6
250
TBD
Call TI
SN74LVC1G98DRLR
ACTIVE
SOP
DRL
6
4000 Green (RoHS &
no Sb/Br)
SN74LVC1G98YEAR
ACTIVE
WCSP
YEA
6
3000
SN74LVC1G98YEPR
ACTIVE
WCSP
YEP
6
3000
SN74LVC1G98YZAR
ACTIVE
WCSP
YZA
6
3000
SN74LVC1G98YZPR
ACTIVE
WCSP
YZP
6
3000
Pb-Free
(RoHS)
Lead/Ball Finish
Call TI
MSL Peak Temp (3)
Call TI
Call TI
CU NIPDAU
Level-1-260C-UNLIM
SNPB
Level-1-260C-UNLIM
TBD
SNPB
Level-1-260C-UNLIM
Pb-Free
(RoHS)
SNAGCU
Level-1-260C-UNLIM
SNAGCU
Level-1-260C-UNLIM
TBD
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MPDS114 – FEBRUARY 2002
DCK (R-PDSO-G6)
PLASTIC SMALL-OUTLINE PACKAGE
0,30
0,15
0,65
6
0,10 M
4
1,40
1,10
1
0,13 NOM
2,40
1,80
3
Gage Plane
2,15
1,85
0,15
0°–8°
0,46
0,26
Seating Plane
1,10
0,80
0,10
0,00
0,10
4093553-3/D 01/02
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion.
Falls within JEDEC MO-203
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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