K4C89363AF Network-DRAM-II Specification Version 0.0 - 1 - REV. 0.0 Nov. 2002 K4C89363AF Revision History Version 0.0 (Nov. 2002) - First Release - 2 - REV. 0.0 Nov. 2002 K4C89363AF 2,097,152-WORDS x 4 BANKS x 36-BITS DOUBLE DATA RATE Network-DRAM DESCRIPTION K4C89363AF is a CMOS Double Data Rate Network-DRAM containing 301,989,888 memory cells. K4C89363AF is organized as 2,097,152-words x 4 banks x36 bits. K4C89363AF feature a fully synchronous operation referenced to clock edge whereby all operations are synchronized at a clock input which enables high performance and simple user interface coexistence. K4C89363AD can operate fast core cycle compared with regular DDR SDRAM. K4C89363AF is suitable for Server, Network and other applications where large memory density and low power consumption are required. The Output Driver for Network-DRAM is capable of high quality fast data transfer under light loading condition. FEATURES K4C89363AF Parameter F6 FB F5 CL = 4 4.0 ns 4.5 ns 5.0 ns CL = 5 3.33 ns 3.75 ns 4.5 ns CL = 6 3.0ns 3.33 ns 4.0 ns tRC R a n d o m R e a d / W r i t e C y c l e T i m e ( m i n ) 20.0 ns 22.5 ns 25 ns tR A C R a n d o m A c c e s s T i m e ( m i n ) 20.0 ns 22.5 ns 25 ns ID D 1 S O p e r a t i n g C u r r e n t ( s i n g l e b a n k ) ( m a x ) TBD TBD TBD ID D 2 S P o w e r D o w n C u r r e n t ( m a x ) TBD TBD TBD ID D 3 S S e l f - R e f r e s h C u r r e n t ( m a x ) TBD TBD TBD tC K C l o c k C y c l e T i m e ( m i n ) • Fully Synchronous Operation - Double Data Rate (DDR) - Data input/output are synchronized with both edges of DS / QS. - Differential Clock (CLK and C L K ) inputs - C S, FN and all address input signals are sampled on the positive edge of CLK. - Output data (DQs and QS) is aligned to the crossings of CLK and CLK. • Fast clock cycle time of 3.0 ns minimum - Clock : 333 MHz maximum - Data : 666 Mbps/pin maximum • Quad Independent Banks operation • Fast cycle and Short Latency • Selectable Data Strobe(Uni/Bi-directional data strobe) • Distributed Auto-Refresh cycle in 3.9us • Self-Refresh • Power Down Mode • Variable Write Length Control • Write Latency = C A S Latency-1 • Programable C A S Latency and Burst Length - C A S Laatency = 4, 5, 6 - Burst Length = 2,4 • Organization : 2,097,152 words x 4 banks x 36 bits • P o w e r S u p p l y V o l t a g e V DD : 2 . 5 V ± 0 . 1 2 5 V V DDQ : 1 . 8 V ± 0 . 1 V • • 1.8V CMOS I/O comply with SSTL - 1.8 (half strength driver) • Package : 144Ball BGA, 1mm x 0.8mm Ball pitch • JTAG(for x36) • Notice : Network-DRAM is trademark of Samsung Electronics., Co LTD - 3 - REV. 0.0 Nov. 2002 - 4 - V SS Q V DD Q V SS Q TD 1 T U V TD 0 D Q 34 V SS D Q3 5 VDD V SS Q VDD VS S Q V SS DQ 18 TC K D Q1 9 D Q2 1 TM S V SS Q V DD Q Power Down Control DQ 20 PD V D DQ Reference Voltage VD D Q V REF D Q3 3 Function Control D Q 32 FN V SS Q V DD Q Ground(for I/O buffer) D Q2 3 D Q2 5 V SSQ DQ 22 DQ 24 Chip Select VS S Q V D DQ CS V SS Q VD D Q Power (+1.8V)(for I/O buffer) D Q3 1 D Q2 9 V DDQ D Q 30 D Q 28 V SS Q Ground UDS V DD Q VSS DQ 26 A5 VDD Bank Address VS S Q A4 A7 VS S VDD VS S V SS Q V DD Q V SS Q V DD Q V SS Q V DD Q VDD 12 BA0, BA1 V SS Q V D DQ A6 A9 A 12 /P D V R EF LD S D Q1 0 D Q1 2 D Q1 4 D Q1 6 V SS 11 Power (+2.5V) D Q2 7 VD D Q VDD A8 A 11 CLK /C L K D Q9 DQ 11 DQ 13 DQ 15 DQ 17 V SS 10 VDD UQ S NC VDD VS S VDD VS S VS S Q V D DQ VS S Q V D DQ VS S Q V D DQ VDD 9 Address Input R V SS Q N A3 A2 VSS VDD VSS VS S Q VD D Q V SS Q VD D Q 8 A0 ~ A14 V DD Q V DD Q M A1 A0 BA 1 A 13 /CS D Q8 D Q6 D Q4 7 Data Input/Output NC A1 0 B A0 A1 4 FN LQ S D Q7 D Q5 V SS Q 6 Pin P VDD L V SS Q G VS S V DD Q F K V SS Q E VDD V DD Q D D Q2 VD D Q 5 CLK, CLK D Q3 D Q0 VDD 4 DQ0 ~ DQ35 J V SS Q C D Q1 V SS 3 Name VS S V DD Q B VS S 2 Pin H VDD A I nd ex 1 K4C89363AF Pin Names Name No Connection Clock Input PIN ASSIGNMENT (TOP VIEW) ball pitch=1.0 x 0.8mm REV. 0.0 Nov. 2002 K4C89363AF Block Diagram CLK DLL CLK CLOCK PD BUFFER To Each Block BANK #3 COMMAND CONTROL BANK #2 SIGNAL DECODER GENERATOR BANK #0 ROW DECODER FN BANK #1 MODE REGISTER A0 ~ A14 ADDRESS BA0, BA1 BUFFER UPPER ADDRESS LATCH REFRESH COUNTER D AT A C O NT R O L A N D L A T C H C IR CU IT CS MEMORY CELL ARRAY COLUMN DECODER LOWER ADDRESS LATCH BURST COUNTER READ DATA BUFFER WRITE ADDRESS LATCH ADDRESS COMPARATOR DS QS WRITE DATA BUFFER DQ BUFFER DQ0 ~ DQ35 Note : The K4C89363AD configuration is 4 Bank of 16384 x 128 x 36 of cell array with the DQ pins numbered DQ0~DQ35. - 5 - REV. 0.0 Nov. 2002 K4C89363AF Absolute Maximum Ratings Symbol Parameter Rating Units V DD Power Supply Voltage -0.3 ~ 3.3 V V DDQ Power Supply Voltage (for I/O buffer) -0.3 ~ V DD + 0.3 V V IN Input Voltage -0.3 ~ V DD + 0.3 V VOUT DQ pin Voltage -0.3 ~ V DDQ + 0.3 V VREF Input Reference Voltage -0.3 ~ V DDQ + 0.3 V TOPR Operating Temperature 0 ~ 70 O C T STG Storage Temperature -55 ~ 150 O C T SOLDER Soldering Temperature(10s) 260 O C PD Power Dissipation 2 W IO U T Short Circuit Output Current ± 50 mA Notes Caution : Conditions outside the limits listed under "ABSOLUTE MAXIMUM RATINGS" may cause permanent damage to the device. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to "ABSOLUTE MAXIMUM RATINGS" conditions for extended periods may affect device reliability. Recommended DC,AC Operating Conditions (Notes : 1) Symbol VDD Parameter Power Supply Voltage VDDQ Power Supply Voltage (for I/O Buffer) VREF Input Reference Voltage (Ta = 0 ~ 70 O C) Min Typ Max Units Notes 2.375 2.5 2.625 V 1.7 1.8 1.9 V V DDQ / 2 x 9 6 % V D D Q /2 V DDQ / 2 x 1 0 5 % V 2 V IH ( D C ) Input DC high Voltage V R E F+ 0 . 1 2 5 - V DDQ +0.2 V 5 V IL ( D C ) Input DC Low Voltage -0.1 - V R E F- 0 . 1 2 5 V 5 Differential Clock DC Input Voltage -0.1 - V DDQ +0.1 V 10 V ID ( D C ) Input Differential Voltage. CLK and C L K Inputs (DC) 0.4 - V DDQ +0.2 V 7,10 V IH ( A C ) Input AC High Voltage V R E F+ 0 . 2 - V DDQ +0.2 V 3,6 V IL ( A C ) Input AC Low Voltage -0.1 - V REF-0.2 V 4,6 V ID ( A C ) Input Differential Voltage. CLK and C L K Inputs (AC) 0.55 - V DDQ +0.2 V 7,10 VX (AC) Differential AC Input Cross Point Voltage V DDQ / 2 - 0 . 1 2 5 - V DDQ /2+0.125 V 8,10 Differential Clock AC Middle Level V DDQ / 2 - 0 . 1 2 5 - V DDQ /2+0.125 V 9,10 V ICK ( D C ) V ISO ( A C ) - 6 - REV. 0.0 Nov. 2002 K4C89363AF Notes: 1. All voltages are referenced to Vss, VssQ. 2. V REF i s e x p e c t e d t o t r a c k v a r i a t i o n s i n V d d Q D C l e v e l o f t h e t r a n s m i t t i n g d e v i c e . P e a k t o p e a k A C n o i s e o n V REF m a y n o t e x c e e d ± 2 % o f V R E F ( D C ) . 3. Overshoot Iimit : V IH( m a x . ) = V d d Q + 0 . 7 V w i t h a p u l s e w i d t h < = 5 n s 4 . U n d e r s h o o t I i m i t : V I L( m i n . ) = - 0 . 7 V w i t h a p u l s e w i d t h < = 5 n s 5 . V I H ( D C ) a n d V IL ( D C ) a r e l e v e l s t o m a i n t a i n t h e c u r r e n t l o g i c s t a t e . 6 . V I H ( A C ) a n d V I L( A C ) a r e l e v e l s t o c h a n g e t o t h e n e w l o g i c s t a t e . 7. V ID i s m a g n i t u d e o f t h e d i f f e r e n c e b e t w e e n C L K i n p u t l e v e l a n d C L K input level. 8. The value of Vx(AC) is expected to equal VddQ/2 of the transmitting device. 9 . V I S O m e a n s [ V I C K( C L K ) + V I C K (C L K ) ] / 2 10. Refer to the figure below. CLK VX VX VX VX VX V ID ( A C ) CLK VI C K V ICK VI C K VI C K VSS V ID ( A C ) 0 V Differential V ISO V ISO(min) V I S O (max) VSS 1 1 . I n t h e c a s e o f e x t e r n a l t e r m i n a t i o n , V T T ( T e r m i n a t i o n V o l t a g e ) s h o u l d b e g o n e i n t h e r a n g e o f V R E F( D C ) ± 0 . 0 4 V . Pin Capacitance o (V DD = 2 . 5 V , V D D Q = 1 . 8 V , f = 1 M H z , T a = 2 5 C ) Symbol Min Max Delts Units Input Pin Capacitance 1.5 2.5 0.25 pF C INC Clock Pin (CLK, C L K ) Capacitance 1.5 2.5 0.25 pF C I/O DQ, DS, QS Capacitance 2.5 3.5 0.5 pF C NC NC Pin Capacitance - 1.5 - pF C IN Parameter Note : These parameters are periodically sampled and not 100% tested. - 7 - REV. 0.0 Nov. 2002 K4C89363AF DC Characteristics and Operating Conditions (Vdd = 2.5V ± 0.125V, VddQ = 1.8V ± 0.1V, Ta = 0~70 °C ) Max Parameter Symbol Units Notes F6 FB F5 I DD1S TBD TBD TBD 1, 2 ID D 2 N TBD TBD TBD 1 Operating Current t CK = m i n , I RC = m i n Read/Write command cycling O V < = V IN< = V IL(AC) ( m a x . ) V IH(AC) ( m i n . ) < = VIN < = V DDQ 1 bank operation, Burst Length = 4 A d d r e s s c h a n g e u p t o 2 t i m e s d u r i n g m i n i m u m IR C . Standby Current t CK = m i n , C S = V IH, P D = V IH , 0 V < = V IN< = V IL(AC) ( m a x . ) V IH(AC) ( m i n . ) < = V IH < = VDDQ All Banks : inactive state O t h e r i n p u t s i g n a l s a r e c h a n g e d o n e t i m e d u r i n g 4 * tC K Standby (Power Down) Current t CK = m i n , C S = V IH, P D = V IL ( P o w e r D o w n ) 0 V < = V IN< = V DDQ mA I DD2P TBD TBD TBD 1 I DD5 TBD TBD TBD 1 I DD6 TBD TBD TBD All Banks : inactive state Auto-Refresh Current t CK = m i n , I REFC = m i n , t REFI = m i n Auto-Refresh command cycling 0 V < = V IN< = V IL( A C ) ( m a x . ) , V IH( A C ) ( m i n . ) < = V IN < = V DDQ A d d r e s s c h a n g e u p t o 2 t i m e s d u r i n g m i n i m u m I R E F C. Self-Refresh Current self-Refresh mode P D = 0 . 2 V , O V < = V IN < = V DDQ Parameter Input Leakage Current ( 0 V < = V IN< = V d d Q , A l l o t h e r p i n s n o t u n d e r t e s t = 0 V ) Output Leakage Current ( O u t p u t d i s a b l e d , 0 V < = VO U T < = V d d Q ) V REF C u r r e n t Output Source DC Current V d d Q = 1 . 7 V / V OH = 1 . 4 2 0 V Symbol Min Max Unit Notes ILI -5 5 uA I LO -5 5 uA I REF -5 5 uA I O H( D C ) -5.6 - 3 IOL ( D C ) 5.6 - 3 I O H( D C ) -9.8 - Normal Output Driver Output Sink DC Current V d d Q = 1 . 7 V / V OL = 0 . 2 8 0 V Output Source DC Current V d d Q = 1 . 7 V / V OH = 1 . 4 2 0 V Strong Output Driver 3 mA Output Sink DC Current V d d Q = 1 . 7 V / V OL = 0 . 2 8 0 V Output Source DC Current V d d Q = 1 . 7 V / V OH = 1 . 4 2 0 V IOL ( D C ) 9.8 - 3 I O H( D C ) -2.8 - 3 IOL ( D C ) 2.8 - 3 Weak Output Driver Output Sink DC Current V d d Q = 1 . 7 V / V OL = 0 . 2 8 0 V N o t e s : 1 . T h e s e p a r a m e t e r s d e p e n d o n t h e c y c l e r a t e a n d t h e s e v a l u e s a r e m e a s u r e d a t a c y c l e r a t e w i t h t h e m i n i m u m v a l u e s o f t C K, t RC a n d I RC . 2. These parameters depend on the output loading. The specified values are obtained with the output open. 3. Refer to output driver characteristics for the detail. Output Driver Strength is selected by Extended Mode Regis ter. - 8 - REV. 0.0 Nov. 2002 K4C89363AF AC Characteristics and Operating Conditions (Notes : 1, 2) F6 Symbol F5 Units Min t RC FB Parameter Random Cycle Time t CK Clock Cycle Time t RAC Random Access Time Max Min Max Min Notes Max 20.0 - 22.5 - 25 - 3 CL = 4 4.0 7.5 4.5 7.5 5.0 7.5 3 CL = 5 3.33 7.5 3.75 7.5 4.5 7.5 3 CL = 6 3.0 7.5 3.33 7.5 4.0 7.5 3 - 20.0 - 22.5 - 25 3 - 3 t CH Clock High Time 0 . 4 5 * tC K - 0.45*tC K - 0 . 4 5 * tC K t CL Clock Low Time 0 . 4 5 * tC K - 0.45*tC K - 0 . 4 5 * tC K - 3 t CKQS QS Access Time from CLK -0.45 0.45 -0.45 0.45 -0.5 0.5 3, 8 tQSQ Data Output Skew from QS - 0.2 - 0.25 - 0.3 4 t AC Data Access Time from CLK -0.5 0.5 -0.5 0.5 -0.6 0.6 3, 8 t OH Data Output Hold Time from CLK t HP C L K h a l f p e r i o d ( m i n i u m o f A c t u a l tC H , t CL ) t QSP t QSQV t QHS DQ, QS Hold skew factor t DQSS DS(Write) Low to High Setup Time 0.8*t C K 1.2*t C K 0 . 8 * tC K 1.2*t C K 0.8*t C K 1.2*t C K t DSPRE DS(Write) Preamble Pulse Width 0.4*t C K - 0 . 4 * tC K - 0.4*t C K - 4 t DSPRES DS First Input Setup Time 0 - 0 - 0 - 3 t DSPREH DS First Low Input Hold Time 0.3*t C K - 0 . 3 * tC K - 0.3*t C K - 3 t DSP DS High or Low Input Pulse Width 0 . 4 5 * tC K 0.55*t C K 0.45*tC K 0.55*t C K 0 . 4 5 * tC K 0.55*t C K 4 CL = 4 0.9 - 0.9 - 1.0 - 3, 4 CL = 5 0.9 - 0.9 - 1.0 - 3, 4 CL = 6 0.9 - 0.9 - 1.0 - 3, 4 0 . 4 5 * tC K - 0.45*tC K 0 . 4 5 * tC K - 4 CL = 4 0.9 - 0.9 - 1.0 - 3, 4 CL = 5 0.9 - 0.9 - 1.0 - 3, 4 CL = 6 0.9 - 0.9 - 1.0 t DSS t DSPST t DSPSTH -0.5 0.5 -0.5 0.5 -0.6 0.6 3, 8 m i n ( tC H , t CL ) - min(tC H , tC L ) - m i n ( tC H , t CL ) - 3 QS(Read) Pulse Width t HP-t QHS - t H P-tQ H S - t HP-t QHS - 4, 8 Data Output Valid Time from QS t HP-t QHS - t H P-tQ H S - t HP-t QHS - 4, 8 DS Input Falling Edge to Clock Setup Time DS(Write) Postamble Pulse Width DS(Write) Postamble Hold Time 0.055x - t CK+ 0 . 1 7 - 0.055x tC K+0.17 - 0.055x t CK+ 0 . 1 7 ns 3 3, 4 t DS Data Input Setup Time from DS 0.3 - 0.35 - 0.4 - 4 t DH Data Input Hold Time from DS 0.3 - 0.35 - 0.4 - 4 t IS Command / Address Input Setup Time 0.6 - 0.6 - 0.7 - 3 t IH Command / Address Input Hold Time 0.6 - 0.6 - 0.7 - 3 - 9 - REV. 0.0 Nov. 2002 K4C89363AF AC Characteristics and Operating Conditions (Notes : 1, 2) (Continued) F6 Symbol FB F5 Parameter Units Notes Min Max Min Max Min Max -0.5 - -0.5 - -0.6 - 3, 6, 8 3, 7, 8 tL Z Data-out Low Impedance Time from CLK tH Z Data-out High Impedance Time from CLK - 0.5 - 0.5 - 0.6 tQPDH Last Output to P D H i g h H o l d T i m e 0 - 0 - 0 - tPDEX Power Down Exit Time 0.6 - 0.6 - 0.7 - tT Input Transition Time 0.1 1 0.1 1 0.1 1 tF P D L P D Low Input Window for Self-Refresh Entry -0.5*t C K 5 - 0 . 5 * tC K 5 -0.5*t C K 5 tR E F I Auto-Refresh Average Interval 0.4 3.9 0.4 3.9 0.4 3.9 3 3 5 us tPAUSE Pause Time after Power-up 200 - 200 - 200 - CL = 4 5 - 5 - 5 - CL = 5 6 - 6 - 6 - CL = 6 7 - 7 - 7 - 1 1 1 1 1 1 CL = 4 4 - 4 - 4 - CL = 5 5 - 5 - 5 - CL = 6 6 - 6 - 6 - 2 - 2 - 2 - Random Read/Write Cycle Time IR C IRCD IRAS IRBD IRWD IWRD (Applicable to Same Bank) RDA/WRA to LAL Command Input Delay (Applicable to Same Bank) LAL to RDA/WRA Command Input Delay (Applicable to Same Bank) Random Bank Access Delay (Applicable to Other Bank) LAL following RDA to WRA Delay BL = 2 2 - 2 - 2 - (Applicable to Other Bank) BL = 4 3 - 3 - 3 - 1 - 1 - 1 - CL = 4 7 - 7 - 7 - CL = 5 7 - 7 - 7 - CL = 6 7 - 7 - 7 - - 2 - 2 - 2 LAL following WRA to RDA Delay (Applicable to Other Bank) IRSC Mode Register Set Cycle Time IPD P D Low to Inactive State of Input Buffer IP D A P D High to Active State of Input Buffer IP D V IR E F C ICKD ILOCK Power down mode valid from REF command Auto-Refresh Cycle Time 1 - 1 - 1 - CL = 4 19 - 19 - 19 - CL = 5 23 - 23 - 23 - CL = 6 25 - 25 - 25 - CL = 4 19 - 19 - 19 - CL = 5 23 - 23 - 23 - CL = 6 25 - 25 - 25 - I REFC - I REFC - IREFC - 200 - 200 - 200 - REF Command to Clock Input Disable at Self-Refresh Entry DLL Lock-on Time (Applicable to RDA command) - 10 - Cycle REV. 0.0 Nov. 2002 K4C89363AF AC Test Conditions Value Units V IH ( m i n ) Symbol Input high voltage (minimum) V REF + 0.2 V V IL ( m a x ) Input low voltage (maximum) V REF - 0.2 V VddQ/2 V VREF V 0.7 V V X(AC) V V REF Parameter Input reference voltage V TT Termination voltage V SWING Input signal peak to peak swing VR Differential clock input reference level V ID ( A C ) SLEW V OTR Input differential voltage 1.0 V Input signal minimum slew rate 2.5 V/ns VddQ/2 V Output timing measurement reference voltage Notes 9 V TT VddQ 50 Ω V IH min (AC) V SWING Z=50Ω 25 Ω VREF Output V IL m a x (AC) Z=50Ω 50 Ω Vss ∆T V TT ∆T S l e w = ( V I H m i n ( A C ) - V I L m a x ( A C ) ) /∆ T AC Test Load N o t e s : 1 . T r a n s i t i o n t i m e s a r e m e a s u r e d b e t w e e n V I H m i n ( D C ) a n d V IL m a x ( D C ) . Transition (rise and fall) of input signals have a fixed slope. 2. If the result of nominal calculation with regard to tCK contains more than one decimal place, the result is rounded up to the nearest decimal place. (i.e., tD Q S S = 0 . 8 * t C K , tC K = 3 . 3 n s , 0 . 8 * 3 . 3 n s = 2 . 6 4 n s i s r o u n d e d u p t o 2 . 7 n s . ) 3. These parameters are measured from the differential clock (CLK and C LK) AC cross point. 4 . T h e s e p a r a m e t e r s a r e m e a s u r e d f r o m s i g n a l t r a n s i t i o n p o i n t o f D S c r o s s i n g V R E F level. 5. The t REFI(MAX.) applies to equally distributed refresh method. The t REFI(MIN.) applies to both burst refresh method and distributed refresh method. In such case, the average interval of eight consecutive Auto-Refresh commands has to be more than 400ns always. In other words, the number of Auto- Refresh cycles which can be performed within 3.2us (8X400ns) is to 8 times in the maximum. 6. Low Impedance State is speified at VddQ/2± 0.2V from steady state. 7. High Impedance State is specified where output buffer is no longer driven. 8. These parameters depend on the clock jitter. These parameters are measured at stable clock. 9. Output timing is measured by using Normal driver strength. - 11 - REV. 0.0 Nov. 2002 K4C89363AF Power Up Sequence 1. As for PD , being maintained by the low state (<0.2V) is desirable before a power-supply injection. 2 . A p p l y V DD b e f o r e o r a t t h e s a m e t i m e a s V DDQ . 3 . A p p l y V D D Q b e f o r e o r a t t h e s a m e t i m e a s V R E F. 4. Start clock (CLK, C L K ) and maintain stable condition for 200us (min.). 5. After stable power and clock, apply DESL and take PD = H. 6. Issue EMRS to enable DLL and to define driver strength and data strobe type. (Note : 1) 7. Issue MRS for set C A S Latency (CL), Burst Type (BT), and Burst Length (BL). (Note : 1) 8. Issue two or more Auto-Refresh commands. (Note:1) 9. Ready for normal operation after 200 clocks from Extended Mode Register programming. Note : 1. Sequence 6, 7 and 8 can be issued in random order. 2. L=Logic Low, H = Logic High ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ 2.5V(TYP) V DD ∼ ∼ ∼ ∼ ∼ ∼ 1.8V(TYP) V DDQ ∼ ∼ ∼ ∼ ∼ ∼ 0.9V(TYP) V REF ∼ ∼ CLK ∼ ∼ ∼ ∼ CLK tP D E X 200 µ s(min) IP D A lR S C lR S C RDA MRS DESL WRA REF DESL ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ DS WRA REF op-code EMRS DQ DESL ∼ ∼ DESL ∼ ∼ RDA MRS ∼ ∼ DESL op-code Address ∼ ∼ 200 clock cycle(min) ∼ ∼ ∼ ∼ Command lR E F C ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ PD lR E F C MRS Hi-Z QS (Uni-QS mode) - 12 - ∼ ∼ MRS ∼ ∼ EMRS ∼ ∼ ∼ ∼ QS (Free Running mode) Low Auto Refresh cycle Normal Operation REV. 0.0 Nov. 2002 K4C89363AF Basic Timing Diagrams Input Timing Command and Address tC K tC H tC K tC L CK ~ CK tIH tI S 1st CS tIH ~ ~ ~ tI S 2nd tIPW tI S tI S tIH ~ ~ ~ ~ 1st FN tIH 2nd tI P W A0-A14 BA0.BA1 tI S tIH tIH ~ ~ ~ ~ tI S LA UA, BA ~ Data LDS/UDS tD H tD S tD H tD S t DH tD S tD H ~~ ~ tD S DQn (Input) ~ ~ ~ DQm (Input) Refer to the Command Truth Table. Timing of the CLK, C L K tC H tC L V IH V IH(AC) CLK V IL(AC) CLK tT tT V IL tC K V IH CLK V ID(AC) CLK VX VX - 13 - VX V IL REV. 0.0 Nov. 2002 K4C89363AF Read Timing (Burst Length = 4) Unidirectional DS/QS mode 0 1 2 tC H 3 tC L 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 tC K CK CK tI S tIH Input (Control & L A L( a f t e r R D A ) DESL Addresses) LDS/UDS (Input) tC K Q S tCKQS C A S latency = 4 LQS/UQS (Output) tQ S P Low Low tQSQV t LZ DQ (Output) tC K Q S tQSP tQSQ tQ S Q tQSQ tQ S Q V Q0 Q1 Q2 t HZ High-Z tA C tA C Q3 tA C tOH tC K Q S tC K Q S C A S latency = 5 LQS/UQS (Output) tQSP Low Low tQ S Q V tL Z DQ (Output) tC K Q S tQSP tQ S Q tQSQ Q0 Q1 tQSQ tQ S Q V tHZ High-Z tA C Q2 tA C Q3 tA C tOH tC K Q S tC K Q S C A S latency = 6 LQS/UQS (Output) tQ S P Low Low tQ S Q V tL Z DQ (Output) tCKQS tQ S P tQSQ tQ S Q Q0 Q1 tQ S Q tQ S Q V tH Z High-Z t AC tA C Q2 t AC Q3 tO H Note : DQ0 to DQ17 are aligned with LQS. DQ18 to DQ35 are aligned with UQS. - 14 - REV. 0.0 Nov. 2002 K4C89363AF Read Timing (Burst Length = 4) Unidirectional DS/Free Running QS mode 0 1 2 tC H 3 tC L 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 tC K CK CK tI S Input (Control & tIH L A L( a f t e r R D A ) DESL Addresses) LDS/UDS (Input) tC K Q S tCKQS C A S latency = 4 tC K Q S tQSP tQ S P LQS/UQS (Output) tQSQV t LZ DQ (Output) tQSQ tQ S Q tQSQ tQ S Q V Q0 Q1 Q2 t HZ High-Z tA C tA C Q3 tA C tOH tC K Q S tC K Q S C A S latency = 5 tC K Q S tQSP tQSP LQS/UQS (Output) tQ S Q V tL Z DQ (Output) tQ S Q tQSQ Q0 Q1 tQSQ tQ S Q V tHZ High-Z tA C Q2 tA C Q3 tA C tOH tC K Q S tC K Q S C A S latency = 6 tCKQS tQ S P tQ S P LQS/UQS (Output) tQ S Q V tL Z DQ (Output) tQSQ tQ S Q Q0 Q1 tQ S Q tQ S Q V tH Z High-Z t AC tA C Q2 t AC Q3 tO H Note : DQ0 to DQ17 are aligned with LQS. DQ18 to DQ35 are aligned with UQS. LQS/UQS is always asserted in Free Running QS mode. - 15 - REV. 0.0 Nov. 2002 K4C89363AF Write Timing (Burst Length = 4) Unidirectional DS/QS mode, Unidirectional DS/Free Running QS mode 0 1 2 tC H 3 tC L 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 tC K CK CK tI S Input (Control & tIH L A L( a f t e r R D A ) DESL Addresses) tDSPSTH tDQSS tD S S tD S P R E S C A S latency = 4 tD S P tDSPREH tD S P tD S P tD S P S T LDS/UDS (Input) tD S S Preamble tD S P R E tD S tD S tD H DQ (Input) Postamble tD S t DH Q0 Q1 Q2 tD H Q3 tD Q S S tD S S C A S latency = 5 tD S P S T H tDSS tD S P R E S tDSPREH tD S P tD S P tD S P tDSPST LDS/UDS (Input) Preamble tD S P R E tD S Postamble tD S tD H DQ (Input) Q0 t DS t DH tD H Q2 Q3 Q1 tDQSS tD S S C A S latency = 6 tD S P S T H tD S S tD S P R E S tDSPREH tD S P tD S P tD S P tDSPST LDS/UDS (Input) Preamble tDSPRE Postamble tD S tD S tD H DQ (Input) Q0 LQS/UQS (Uni-QS) Q1 t DS t DH tD H Q2 Q3 Low LQS/UQS (Free Runninig) Note : DQ0 to DQ17 are sampled at both edges of LDS. DQ18 to DQ35 are sampled at both edges of UDS. - 16 - REV. 0.0 Nov. 2002 K4C89363AF ~ ~ t R E F I, t P A U S E, I x x x x T i m i n g CLK CLK Input (Control & Addresses) tIH tR E F I , tP A U S E , IX X X X ~ ~ tI S Command N o t e . " I X X X X " m e a n s " IR C " , "I R C D " , t IS t IH Command " IR A S " , e t c . - 17 - REV. 0.0 Nov. 2002 K4C89363AF Function Truth Table (Notes : 1,2,3) Command Truth Table (Notes : 4) •T h e F i r s t C o m m a n d Symbol CS FN BA1-BA0 A14-A9 A8 A7 A6-A0 Device Deselect H X X X X X X RDA Read with Auto-close L H BA UA UA UA UA WRA Write with Auto-close L L BA UA UA UA UA DESL Function •T h e S e c o n d C o m m a n d ( T h e n e x t c l o c k o f R D A o r W R A c o m m a n d ) Symbol Function CS FN BA1-BA0 A14-A13 A12-A11 A10-A9 A8 A7 A6-A0 LAL Lower Address Latch H X X V X X X X LA REF Auto-Refresh L X X X X X X X X MRS Mode Register Set L X V L L L L V V Notes : 1 . L = L o g i c L o w , H = L o g i c H i g h , X = e i t h e r L o r H , V = V a l i d ( S p e c i f i e d V a l u e ) , B A = B a n k A d d r e s s , U A = U p p e r A d d r e s s , LA = Lower Address. 2. All commands are assumed to issue at a valid state. 3. All inputs for command (excluding SELFX and PDEX) are latched on the crossing point of differential clock input where CLK goes to High. 4. Operation mode is decided by the comination of 1st command and 2nd command refer to "STATE DIAGRAM" and the command table below. Read Command Table Command (Symbol) CS FN BA1-BA0 A14-A9 A8 A7 A6-A0 RDA (1st) L H BA UA UA UA UA LAL (2nd) H X X X X X LA Notes Write Command Table Command (Symbol) CS FN WRA (1st) L L LAL (2nd) H X BA1- A14 A13 A12 A11 BA UA UA UA UA X VW0 VW1 X X BA0 A10~ A8 A7 A6-A0 UA UA UA UA X X X LA A9 Notes : 5. A14~A13 are used for Variable Write Length (VW) control at Write Operation. VW Truth Table Function VW0 VW1 Write All Words L X Write First One Word H X Reserved L L BL = 2 Write All Words H L Write First Two Words L H Write First One Word H H BL = 4 - 18 - REV. 0.0 Nov. 2002 K4C89363AF Function Truth Table (Continued) Mode Register Set Command Truth Table Command (Symbol) CS FN BA1-BA0 A14-A9 A8 A7 A6-A0 RDA (1st) L H X X X X X MRS (2nd) L X V L L V V Notes 6 Note : 6. Refer to "Mode Register Table". Auto-Refresh Command Table Command Current (Symbol) State Active WRA(1st) Auto-Refresh REF(2nd) Function PD CS FN H L L X H L X X n-1 n Standby H Active H BA1-BA0 A14-A9 A8 A7 A6-A0 X X X X X X X X Notes Self-Refresh Command Table Command Current (Symbol) State Active WRA(1st) Self-Refresh Entry Function PD CS FN A14-A9 A8 A7 A6-A0 X X X X X X X X X X X X X X X X X X H X X X X X X CS FN n-1 n Standby H H L L REF(2nd) Active H L L - Self-Refresh L L SELFX Self-Refresh L H Command Current (Symbol) State PDEN Self-Refresh Continue Self-Refresh Exit BA1BA0 Notes 7, 8 9 Power Down Table Function Power Down Entry Power Down Continue Power Down Exit Notes : PD BA1- A14-A9 A8 A7 A6-A0 Notes X X X X X 8 X X X X X X X X X X X X n-1 n Standby H L H X - Power Down L L X PDEX Power Down L H H BA0 9 7. PD has to be brought to Low within t FPDL f r o m R E F c o m m a n d . 8. P D should be brought to Low after DQ’s state turned high impedance. 9 . W h e n PD is brought to High from Low, this function is executed asynchronously. - 19 - REV. 0.0 Nov. 2002 K4C89363AF Function Truth Table (Continued) PD Current State CS FN Address Command H H H L X X DESL NOP H BA, UA RDA H H Row activate for Read L L BA, UA WRA H Row activate for Write L H X X PDEN H Power Down Entry L L X X - Illegal Refer to Power Down state n-1 n H H Action Notes Idle Row Active for Read Row Active for Write 10 L X X X X - H H H X LA LAL H H L X Op-Code MRS/EMRS H L H X X PDEN Illegal H L L X X MRS/EMRS Illegal L X X X X - Invalid H H H X LA LAL Begin Write H H L X X REF Auto-Refresh H L H X X PDEN H L L X X REF (Self) L X X X X - H H H X X DESL Continue burst read to end H H L H BA, UA RDA Illegal 11 H H L L BA, UA WRA Illegal 11 H L H X X PDEN Illegal H L L X X - Illegal L X X X X - Invalid H H H X X DESL Data write & continue burst write to end H H L H BA, UA RDA Illegal 11 H H L L BA, UA WRA Illegal 11 H L H X X PDEN Illegal H L L X X - Illegal L X X X X - Invalid H H H X X DESL N O P - > I d l e a f t e r I REFC H H L H BA, UA RDA Illegal H H L L BA, UA WRA Illegal H L H X X PDEN Self-Refresh entry H L L X X - Illegal Refer to Self-Refreshing state Begin read Access to Mode Register Illegal Self-Refresh entry Invalid Read Write Auto-Refreshing Mode Register Accessing Power Down L X X X X - H H H X X DESL N o p - > I d l e a f t e r IRSC H H L H BA, UA RDA Illegal H H L L BA, UA WRA Illegal H L H X X PDEN Illegal H L L X X - Illegal L X X X X - Invalid H X X X X - Invalid L L X X X - Maintain Power Down Mode L H H X X RDEX L H L X X - Illegal H X X X X - Invalid L L X X X - Maintain Self-Refresh L H H X X SELFX L H L X X - 12 E x i t P o w e r D o w n M o d e - > I d l e a f t e r t PDEX Se;f-Refreshing E x i t S e l f - R e f r e s h - > I d l e a f t e r I REFC Illegal Notes : 10. Illegal if any bank is not idle. 11. Illegal to bank in specified states : Function may be Legal in the bank indicated by bank Address (BA). 1 2 . I l l e g a l i f t FPDL i s n o t S t i s f i e d . - 20 - REV. 0.0 Nov. 2002 K4C89363AF Mode Register Table Regular Mode Register (Notes : 1) Address B A 1 *1 B A 0 *1 A14-A8 A 7 *3 A6-A4 A3 A2-A0 Register 0 0 0 TM CL BT BL A7 Test Mode (TM) A3 Burst Type (BT) 0 Regular (Default) 0 Sequential 1 Test Mode Entry 1 Interleave A6 A5 A4 C A S Latency (CL) A2 A1 A0 Burst Length (BL) 0 0 X Reserved *2 0 0 0 Reserved *2 0 1 0 Reserved *2 0 0 1 2 0 1 1 Reserved *2 0 1 0 4 1 0 0 4 0 1 1 1 0 1 1 X X 5 1 1 0 6 1 1 1 Reserved *2 Reserved *2 Extended Mode Register (Notes : 4) A6 Address B A 1 *4 B A 0 *4 A14-A7 A6~A5 A4-A3 A2~A1 A 0 *5 Register 0 1 0 SS DIC(QS) DIC(DQ) DS A5 Strobe Select *2 0 0 Reserved 0 1 Reserved*2 1 0 Unidirectional DS/QS 1 1 Unidirectional DS/Free Running QS QS DQ Output Driver Impedance Control (DIC) A4 A3 A2 A1 0 0 0 0 Normal Output Driver 0 1 0 1 Strong Output Driver 1 0 1 0 Weak Output Driver 1 1 1 1 Reserved Note : 1. Regular Mode Register Is Chosen Using the combination of BA0 = 0 and BA1 = 0. 2. "Reserved" places in Regular Mode Register should not be set. 3. A7 in Regular Mode Register must be set to "0"(Low state). A0 DLL Switch (DS) 0 DLL Enable 1 DLL Disable Because Test Mode is specific mode for supplier. 4. Extended Mode Register is chosen using the Combination of BA0 = 1 and BA1 = 0. 5. A0 in Extended Mode Register must be set to "0" to enable DLL for normal operation. - 21 - REV. 0.0 Nov. 2002 K4C89363AF State Diagram Self Refresh Power Down SELFX PDEX (PD = H ) (P D = H ) PDEN (P D = L ) PD = L Standby (Idle) PD = H AutoRefresh Mode Register WRA RDA REF MRS Active (Restore) Active LAL LAL Write (Buffer) Read Command Input Automatic Return The second command at Active state must be issued 1clock after RDA or WRA command input - 22 - REV. 0.0 Nov. 2002 K4C89363AF Timing Diagrams Single Bank Read Timing (CL=4) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CLK CLK l R C =5cycles Command RDA LAL lR C D =1cycle Address UA Bank Add. #0 DESL lR A S = 4 c y c l e s LA l RC = 5 c y c l e s RDA LAL DESL l R C D =1cycle UA l R A S =4cycles LA lR C = 5 c y c l e s RDA DESL l R C D =1cycle UA #0 LAL RDA l R A S= 4 c y c l e s LA UA #0 #0 Unidirectional DS/QS mode BL =2 LDS/UDS (Input) LQS/UQS (Output) Low CL=4 DQ (Output) CL=4 CL=4 Hi-Z Q0 Q1 Q0 Q1 Q0 BL =4 LDS/UDS (Input) LQS/UQS (Output) Low CL=4 DQ (Output) CL=4 CL=4 Hi-Z Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3 Q0 Unidirectional DS/Free Running QS mode BL =2 LDS/UDS (Input) LQS/UQS (Output) CL=4 DQ (Output) CL=4 CL=4 Hi-Z Q0 Q1 Q0 Q1 Q0 BL =4 LDS/UDS (Input) LQS/UQS (Output) CL=4 DQ (Output) CL=4 CL=4 Hi-Z Q0 Q1 Q2 Q3 - 23 - Q0 Q1 Q2 Q3 Q0 REV. 0.0 Sep. 2002 K4C89363AF Single Bank Read Timing (CL=5) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 RDA LAL 14 15 CLK CLK l R C =6cycles Command RDA LAL l R C D =1cycle Address UA Bank Add. #0 DESL l R A S= 5 c y c l e s LA l RC = 6 c y c l e s RDA LAL DESL l R C D =1cycle lR A S= 5 c y c l e s UA LA UA #0 DESL lR C D =1cycle LA #0 Unidirectional DS/QS mode BL =2 LDS/UDS (Input) LQS/UQS (Output) Low CL=5 DQ (Output) CL=5 Hi-Z Q0 Q1 Q0 Q1 Q0 Q 1 Q2 Q0 Q1 Q0 Q 1 Q2 BL =4 LDS/UDS (Input) LQS/UQS (Output) Low CL=5 DQ (Output) CL=5 Hi-Z Q0 Q1 Q2 Q3 Q3 Unidirectional DS/Free Running QS mode BL =2 LDS/UDS (Input) LQS/UQS (Output) CL=5 DQ (Output) CL=5 Hi-Z Q0 Q1 BL =4 LDS/UDS (Input) LQS/UQS (Output) CL=5 DQ (Output) CL=5 Hi-Z Q0 Q1 - 24 - Q2 Q3 Q3 REV. 0.0 Sep. 2002 K4C89363AF Single Bank Read Timing (CL=6) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RDA LAL CLK CLK lR C = 7 c y c l e s Command RDA LAL l R C D =1cycle Address UA Bank Add. #0 DESL l R C =7cycles RDA l R A S= 6 c y c l e s LAL DESL l R C D =1cycle LA UA l R A S= 6 c y c l e s LA l R C D =1cycle UA #0 LA #0 Unidirectional DS/QS mode BL =2 LDS/UDS (Input) LQS/UQS (Output) Low CL=6 DQ (Output) CL=6 Hi-Z Q0 Q1 Q0 Q1 Q0 Q1 Q0 Q1 Q0 Q1 BL =4 LDS/UDS (Input) LQS/UQS (Output) Low CL=6 DQ (Output) CL=6 Hi-Z Q0 Q1 Q2 Q3 Q2 Unidirectional DS/Free Running QS mode BL =2 LDS/UDS (Input) LQS/UQS (Output) CL=6 DQ (Output) CL=6 Hi-Z Q0 Q1 BL =4 LDS/UDS (Input) LQS/UQS (Output) CL=6 DQ (Output) CL=6 Hi-Z Q0 - 25 - Q1 Q2 Q3 Q2 REV. 0.0 Sep. 2002 K4C89363AF Single Bank Write Timing (CL=4) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CLK CLK l R C =5cycles Command WRA LAL lR C D =1cycle Address UA Bank Add. #0 l RC = 5 c y c l e s DESL WRA lR A S = 4 c y c l e s LAL l R C D =1cycle LA UA lR C = 5 c y c l e s DESL WRA l R A S =4cycles LAL l R C D =1cycle LA UA #0 DESL WRA l R A S= 4 c y c l e s LA UA #0 #0 Unidirectional DS/QS mode BL =2 LDS/UDS (Input) LQS/UQS (Output) Low WL=3 DQ (Output) WL=3 D0 D1 WL=3 D0 D1 D0 D1 D0 D1 D0 D1 D0 D1 BL =4 LDS/UDS (Input) LQS/UQS (Output) Low WL=3 DQ (Output) WL=3 D0 D1 D2 D3 WL=3 D0 D1 D2 D3 D2 D3 D2 D3 Unidirectional DS/Free Running QS mode BL =2 LDS/UDS (Input) LQS/UQS (Output) WL=3 DQ (Output) WL=3 D0 D1 WL=3 D0 D1 BL =4 LDS/UDS (Input) LQS/UQS (Output) WL=3 DQ (Output) WL=3 D0 D1 D2 D3 WL=3 D0 - 26 - D1 D2 D3 REV. 0.0 Sep. 2002 K4C89363AF Single Bank Write Timing (CL=5) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 WRA LAL 14 15 CLK CLK lR C = 6 c y c l e s Command WRA LAL lR C D =1cycle Address UA Bank Add. #0 l R C =6cycles DESL WRA l R A S= 5 c y c l e s LAL l R C D =1cycle LA UA DESL lR A S = 5 c y c l e s DESL l R C D =1cycle LA UA #0 LA #0 Unidirectional DS/QS mode BL =2 LDS/UDS (Input) LQS/UQS (Output) Low WL=4 DQ (Output) WL=4 D 0 D1 D0 D1 D0 D1 D0 D1 D0 D1 BL =4 LDS/UDS (Input) LQS/UQS (Output) Low WL=4 DQ (Output) WL=4 D0 D1 D2 D3 D2 D3 D2 D3 Unidirectional DS/Free Running QS mode BL =2 LDS/UDS (Input) LQS/UQS (Output) WL=4 DQ (Output) WL=4 D 0 D1 BL =4 LDS/UDS (Input) LQS/UQS (Output) WL=4 DQ (Output) WL=4 D0 D1 D2 D3 - 27 - REV. 0.0 Sep. 2002 K4C89363AF Single Bank Write Timing (CL=6) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 WRA LAL CLK CLK lR C = 7 c y c l e s Command WRA LAL lR C D =1cycle Address UA Bank Add. #0 l R C =7cycles DESL WRA l R A S= 6 c y c l e s LAL l R C D =1cycle LA UA DESL lR A S = 6 c y c l e s lR C D = 1 c y c l e LA UA #0 LA #0 Unidirectional DS/QS mode BL =2 LDS/UDS (Input) LQS/UQS (Output) Low WL=5 DQ (Output) WL=5 D0 D1 D0 D1 D0 D1 D0 D1 D0 D1 BL =4 LDS/UDS (Input) LQS/UQS (Output) Low WL=5 DQ (Output) WL=5 D0 D1 D2 D3 D2 D3 D2 D3 Unidirectional DS/Free Running QS mode BL =2 LDS/UDS (Input) LQS/UQS (Output) WL=5 DQ (Output) WL=5 D0 D1 BL =4 LDS/UDS (Input) LQS/UQS (Output) WL=5 DQ (Output) WL=5 D0 D1 - 28 - D2 D3 REV. 0.0 Sep. 2002 K4C89363AF Single Bank Read-Write Timing (CL=4) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CLK CLK l R C =5cycles Command RDA LAL Address UA LA Bank Add. #0 DESL l RC = 5 c y c l e s WRA LAL UA LA lR C = 5 c y c l e s DESL #0 RDA LAL UA LA DESL WRA UA #0 #0 Unidirectional DS/QS mode BL =2 LDS/UDS (Input) LQS/UQS (Output) Low CL=4 DQ (Output) WL=3 CL=4 Hi-Z Q0 Q1 D 0 D1 Q0 BL =4 LDS/UDS (Input) LQS/UQS (Output) Low CL=4 DQ (Output) WL=3 CL=4 Hi-Z Q0 Q1 Q2 Q3 D0 D1 D2 D3 Q0 Unidirectional DS/Free Running QS mode BL =2 LDS/UDS (Input) LQS/UQS (Output) CL=4 DQ (Output) WL=3 CL=4 Hi-Z Q0 Q1 D 0 D1 Q0 BL =4 LDS/UDS (Input) LQS/UQS (Output) CL=4 DQ (Output) WL=3 CL=4 Hi-Z Q0 Q1 Q2 Q3 - 29 - D0 D1 D2 D3 Q0 REV. 0.0 Sep. 2002 K4C89363AF Single Bank Read-Write Timing (CL=5) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 RDA LAL UA LA 14 15 CLK CLK lR C = 6 c y c l e s Command RDA LAL Address UA LA Bank Add. #0 DESL l R C =6cycles WRA LAL UA LA DESL #0 DESL #0 Unidirectional DS/QS mode BL =2 LDS/UDS (Input) LQS/UQS (Output) Low CL=5 DQ (Output) WL=4 Hi-Z Q0 Q1 D0 D1 D0 D1 D0 D1 D0 D1 BL =4 LDS/UDS (Input) LQS/UQS (Output) Low CL=5 DQ (Output) WL=4 Hi-Z Q0 Q1 Q2 Q3 D2 D3 D2 D3 Unidirectional DS/Free Running QS mode BL =2 LDS/UDS (Input) LQS/UQS (Output) CL=5 DQ (Output) WL=4 Hi-Z Q0 Q1 BL =4 LDS/UDS (Input) LQS/UQS (Output) CL=5 DQ (Output) WL=4 Hi-Z Q0 Q1 Q2 Read data - 30 - Q3 Write data REV. 0.0 Sep. 2002 K4C89363AF Single Bank Read-Write Timing (CL=6) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RDA LAL UA LA CLK CLK lR C = 7 c y c l e s RDA LAL Address UA LA Bank Add. #0 Command l R C =7cycles DESL WRA LAL UA LA DESL #0 #0 Unidirectional DS/QS mode BL =2 LDS/UDS (Input) LQS/UQS (Output) Low CL=6 DQ (Output) WL=5 Hi-Z Q0 Q1 D0 D1 D0 D1 D0 D1 D0 D1 BL =4 LDS/UDS (Input) LQS/UQS (Output) Low CL=6 DQ (Output) WL=5 Hi-Z Q0 Q1 Q2 Q3 D2 D3 D2 D3 Unidirectional DS/Free Running QS mode BL =2 LDS/UDS (Input) LQS/UQS (Output) CL=6 DQ (Output) WL=5 Hi-Z Q0 Q1 BL =4 LDS/UDS (Input) LQS/UQS (Output) CL=6 DQ (Output) WL=5 Hi-Z Q0 Q1 Q2 Read data - 31 - Q3 Write data REV. 0.0 Sep. 2002 K4C89363AF Multiple Bank Read Timing (CL=4) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CLK CLK lR B D =2cycles Command Address Bank Add. lR B D= 2 c y c l e s RDA LAL RDA LAL UA LA UA LA Bank "a" DESL Bank "b" lR B D = 2 c y c l e s lR B D = 2 c y c l e s lR B D= 2 c y c l e s RDA LAL RDA LAL RDA LAL RDA LAL RDA LAL RDA UA LA UA LA UA LA UA LA UA LA UA Bank "a" Bank "b" Bank "c" Bank "d" Bank "a" Bank "b" l RC (Bank"a")=5cycles l R C (Bank"a")=5cycles Unidirectional DS/QS mode BL =2 LDS/UDS (Input) Low LQS/UQS (Output) CL=4 CL=4 DQ (Output) Hi-Z Q a 0 Qa1 Q b 0 Qb1 Qa0 Q a 1 Qb0 Q b 1 Qc0 Q c 1 BL =4 LDS/UDS (Input) Low LQS/UQS (Output) CL=4 CL=4 DQ (Output) Hi-Z Q a 0 Qa1 Q a 2 Qa3 Q b 0 Q b 1 Qb2 Q b 3 Qa0 Q a 1 Q a 2 Q a 3 Q b 0 Q b 1 Q b 2 Q b 3 Qc0 Q c 1 Qc2 Unidirectional DS/Free Running QS mode BL =2 LDS/UDS (Input) LQS/UQS (Output) CL=4 CL=4 DQ (Output) Hi-Z Q a 0 Qa1 Q b 0 Qb1 Qa0 Q a 1 Qb0 Q b 1 Qc0 Q c 1 BL =4 LDS/UDS (Input) LQS/UQS (Output) CL=4 CL=4 DQ (Output) Hi-Z Q a 0 Qa1 Q a 2 Qa3 Q b 0 Q b 1 Qb2 Q b 3 Qa0 Q a 1 Q a 2 Q a 3 Q b 0 Q b 1 Q b 2 Q b 3 Qc0 Q c 1 Qc2 Note : l R C to the same bank must be satisfied - 32 - REV. 0.0 Sep. 2002 K4C89363AF Multiple Bank Read Timing (CL=5) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CLK CLK lR B D =2cycles Command Address Bank Add. lR B D =2cycles RDA LAL RDA LAL UA LA UA LA Bank "a" DESL Bank "b" lR B D = 2 c y c l e s lR B D = 2 c y c l e s lR B D =2cycles RDA LAL RDA LAL RDA LAL RDA LAL RDA LAL UA LA UA LA UA LA UA LA UA LA Bank "a" Bank "b" Bank "c" Bank "d" Bank "a" lR C ( B a n k " a " ) = 6 c y c l e s lR C ( B a n k " a " ) = 6 c y c l e s Unidirectional DS/QS mode BL =2 LDS/UDS (Input) Low LQS/UQS (Output) CL=5 CL=5 DQ (Output) Hi-Z Q a 0 Qa1 Qb0 Q b 1 Q a 0 Qa1 Qb0 Q b 1 BL =4 LDS/UDS (Input) Low LQS/UQS (Output) CL=5 CL=5 DQ (Output) Hi-Z Q a 0 Qa1 Q a 2 Q a 3 Qb0 Q b 1 Qb2 Q b 3 Q a 0 Q a 1 Q a 2 Q a 3 Qb0 Q b 1 Q b 2 Q a 0 Qa1 Q a 0 Qa1 Unidirectional DS/Free Running QS mode BL =2 LDS/UDS (Input) LQS/UQS (Output) CL=5 CL=5 DQ (Output) Hi-Z Qb0 Q b 1 Qb0 Q b 1 BL =4 LDS/UDS (Input) LQS/UQS (Output) CL=5 CL=5 DQ (Output) Hi-Z Q a 0 Qa1 Q a 2 Q a 3 Qb0 Q b 1 Qb2 Q b 3 - 33 - Q a 0 Q a 1 Q a 2 Q a 3 Qb0 Q b 1 Q b 2 REV. 0.0 Sep. 2002 K4C89363AF Multiple Bank Read Timing (CL=6) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CLK CLK lR B D =2cycles Command Address Bank Add. lR B D= 2 c y c l e s RDA LAL RDA LAL UA LA UA LA Bank "a" DESL Bank "b" lR B D = 2 c y c l e s lR B D = 2 c y c l e s lR B D= 2 c y c l e s RDA LAL RDA LAL RDA LAL RDA LAL RDA UA LA UA LA UA LA UA LA UA Bank "a" Bank "b" Bank "c" Bank "d" Bank "a" lR C ( B a n k " a " ) = 7 c y c l e s lR C ( B a n k " a " ) = 7 c y c l e s Unidirectional DS/QS mode BL =2 LDS/UDS (Input) Low LQS/UQS (Output) CL=6 CL=6 DQ (Output) Hi-Z Q a 0 Qa1 Qb0 Q b 1 Q a 0 Qa1 BL =4 LDS/UDS (Input) Low LQS/UQS (Output) CL=6 CL=6 DQ (Output) Hi-Z Q a 0 Q a 1 Qa2 Q a 3 Qb0 Q b 1 Q b 2 Q b 3 Q a 0 Qa1 Q a 2 Q a 0 Qa1 Q a 0 Qa1 Unidirectional DS/Free Running QS mode BL =2 LDS/UDS (Input) LQS/UQS (Output) CL=6 CL=6 DQ (Output) Hi-Z Qb0 Q b 1 BL =4 LDS/UDS (Input) LQS/UQS (Output) CL=6 CL=6 DQ (Output) Hi-Z Q a 0 Q a 1 Qa2 Q a 3 Qb0 Q b 1 Q b 2 Q b 3 - 34 - Q a 0 Qa1 Q a 2 REV. 0.0 Sep. 2002 K4C89363AF Multiple Bank Write Timing (CL=4) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CLK CLK lR B D =2cycles Command Address Bank Add. lR B D= 2 c y c l e s WRA LAL WRA LAL UA LA UA LA Bank "a" DESL Bank "b" lR B D = 2 c y c l e s lR B D = 2 c y c l e s lR B D= 2 c y c l e s WRA LAL WRA LAL WRA LAL WRA LAL WRA LAL WRA UA LA UA LA UA LA UA LA UA LA UA Bank "a" Bank "b" Bank "c" Bank "d" Bank "a" Bank "b" Da0 Da1 Db0 Db1 Dc0 Dc1 Dd0 Dd1 l RC (Bank"a")=5cycles l R C (Bank"b")=5cycles Unidirectional DS/QS mode BL =2 LDS/UDS (Input) Low LQS/UQS (Output) WL=3 WL=3 DQ (Output) D a 0 Da1 D b 0 Db1 BL =4 LDS/UDS (Input) Low LQS/UQS (Output) WL=3 WL=3 DQ (Output) D a 0 Da1 D a 2 D a 3 Db0 D b 1 Db2 D b 3 D a 0 D a 1 D a 2 Da3 D b 0 Db1 D b 2 Db3 Dc0 Dc1 Dc2 Dc3 D d 0 D d 1 Unidirectional DS/Free Running QS mode BL =2 LDS/UDS (Input) LQS/UQS (Output) WL=3 WL=3 DQ (Output) D a 0 Da1 D b 0 Db1 Da0 Da1 Db0 Db1 Dc0 Dc1 Dd0 Dd1 BL =4 LDS/UDS (Input) LQS/UQS (Output) WL=3 WL=3 DQ (Output) D a 0 Da1 D a 2 D a 3 Db0 D b 1 Db2 D b 3 - 35 - D a 0 D a 1 D a 2 Da3 D b 0 Db1 D b 2 Db3 Dc0 Dc1 Dc2 Dc3 D d 0 D d 1 REV. 0.0 Sep. 2002 K4C89363AF Multiple Bank Write Timing (CL=5) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CLK CLK lR B D =2cycles Command Address Bank Add. lR B D =2cycles WRA LAL WRA LAL UA LA UA LA Bank "a" DESL Bank "b" lR B D = 2 c y c l e s lR B D = 2 c y c l e s lR B D =2cycles WRA LAL WRA LAL WRA LAL WRA LAL WRA LAL UA LA UA LA UA LA UA LA UA LA Bank "a" Bank "b" Bank "c" Bank "d" Bank "a" lR C ( B a n k " a " ) = 6 c y c l e s lR C ( B a n k " b " ) = 6 c y c l e s Unidirectional DS/QS mode BL =2 LDS/UDS (Input) Low LQS/UQS (Output) WL=4 WL=4 DQ (Output) D a 0 Da1 D b 0 Db1 Da0 Da1 Db0 Db1 Dc0 Dc1 BL =4 LDS/UDS (Input) Low LQS/UQS (Output) WL=4 WL=4 DQ (Output) D a 0 D a 1 Da2 D a 3 Db0 D b 1 D b 2 D b 3 D a 0 D a 1 D a 2 Da3 D b 0 Db1 D b 2 Db3 Dc0 Dc1 Unidirectional DS/Free Running QS mode BL =2 LDS/UDS (Input) LQS/UQS (Output) WL=4 WL=4 DQ (Output) D a 0 Da1 D b 0 Db1 Da0 Da1 Db0 Db1 Dc0 Dc1 BL =4 LDS/UDS (Input) LQS/UQS (Output) WL=4 WL=4 DQ (Output) D a 0 D a 1 Da2 D a 3 Db0 D b 1 D b 2 D b 3 D a 0 D a 1 D a 2 Da3 D b 0 Db1 D b 2 Db3 Dc0 Dc1 N o t e : IR C t o t h e s a m e b a n k m u s t b e s a t i s f i e d . - 36 - REV. 0.0 Sep. 2002 K4C89363AF Multiple Bank Write Timing (CL=6) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CLK CLK lR B D =2cycles Command Address Bank Add. lR B D= 2 c y c l e s WRA LAL WRA LAL UA LA UA LA Bank "a" DESL Bank "b" lR B D = 2 c y c l e s lR B D = 2 c y c l e s lR B D= 2 c y c l e s WRA LAL WRA LAL WRA LAL WRA LAL WRA UA LA UA LA UA LA UA LA UA Bank "a" Bank "b" Bank "c" Bank "d" Bank "a" Da0 D a 1 Db0 Db1 lR C ( B a n k " a " ) = 7 c y c l e s lR C ( B a n k " a " ) = 7 c y c l e s Unidirectional DS/QS mode BL =2 LDS/UDS (Input) Low LQS/UQS (Output) WL=5 WL=5 DQ (Output) D a 0 Da1 D b 0 Db1 BL =4 LDS/UDS (Input) Low LQS/UQS (Output) WL=5 WL=5 DQ (Output) D a 0 D a 1 Da2 D a 3 Db0 D b 1 D b 2 D b 3 D a 0 D a 1 D a 2 D a 3 D b 0 Db1 Unidirectional DS/Free Running QS mode BL =2 LDS/UDS (Input) LQS/UQS (Output) WL=5 WL=5 DQ (Output) D a 0 Da1 D b 0 Db1 Da0 D a 1 Db0 Db1 BL =4 LDS/UDS (Input) LQS/UQS (Output) WL=5 WL=5 DQ (Output) D a 0 D a 1 Da2 D a 3 Db0 D b 1 D b 2 D b 3 D a 0 D a 1 D a 2 D a 3 D b 0 Db1 N o t e : IR C t o t h e s a m e b a n k m u s t b e s a t i s f i e d . - 37 - REV. 0.0 Sep. 2002 K4C89363AF Multiple Bank Read-Write Timing (BL=2) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 DESL WRA LAL RDA LAL DESL WRA LAL RDA LAL DESL WRA UA LA UA LA UA LA UA LA CLK CLK lR B D =2cycles Command Address Bank Add. WRA LAL RDA LAL UA LA UA LA Bank "a" Bank "b" Bank "c" Bank "d" Bank "a" UA Bank "b" Bank "c" l R C (Bank"a") l R C (Bank"a") Unidirectional DS/QS mode CL =4 LDS/UDS (Input) LQS/UQS (Output) Low CL=4 WL=3 DQ Hi-Z D a 0 Da1 (Output) Q b 0 Qb1 Dc0 Dc1 Q d 0 Qd1 Da0 Da1 CL =5 LDS/UDS (Input) LQS/UQS Low (Output) CL=5 WL=4 DQ (Output) Hi-Z D a 0 Da1 Q b 0 Qb1 Dc0 Dc1 Q d 0 Qd1 Da0 Da1 CL =6 LDS/UDS (Input) LQS/UQS Low (Output) CL=6 WL=5 Hi-Z DQ D a 0 Da1 (Output) Q b 0 Qb1 Dc0 Dc1 Q d 0 Qd1 Unidirectional DS/Free Running QS mode CL =4 LDS/UDS (Input) LQS/UQS (Output) CL=4 WL=3 DQ Hi-Z Da0 Qa1 (Output) Q b 0 Qb1 Dc0 Q c 1 Q d 0 Qd1 Da0 Da1 CL =5 LDS/UDS (Input) LQS/UQS (Output) WL=4 CL=5 Hi-Z DQ D a 0 Da1 (Output) Q b 0 Qb1 Dc0 Dc1 Q d 0 Qd1 Da0 Da1 CL =6 LDS/UDS (Input) LQS/UQS (Output) WL=5 CL=6 Hi-Z DQ (Output) D a 0 Da1 Q b 0 Qb1 Dc0 Dc1 Q d 0 Qd1 N o t e : IR C t o t h e s a m e b a n k m u s t b e s a t i s f i e d . - 38 - REV. 0.0 Sep. 2002 K4C89363AF Multiple Bank Read-Write Timing (BL=4) 0 1 2 3 RDA LAL 4 5 6 7 8 9 WRA LAL RDA LAL 10 11 12 13 14 15 WRA LAL RDA LAL CLK CLK lR B D =2cycles Command WRA LAL l W R D =1cycle Address Bank Add. UA LA Bank "a" UA DESL lR W D = 3 c y c l e s l W R D =1cycle LA UA Bank "b" LA UA Bank "c" DESL l R W D =3cycles LA l W R D =1cycle UA Bank "d" LA Bank "a" UA LA Bank "b" l R C (Bank"a") l R C (Bank"a") Unidirectional DS/QS mode CL =4 LDS/UDS (Input) LQS/UQS (Output) Low CL=4 WL=3 DQ Hi-Z D a 0 Da1 D a 2 D a 3 (Output) Q b 0 Q b 1 Q b 2 Qb3 D a 0 Da1 D a 2 D a 3 Qb0 Q b 1 Qb2 Q b 3 CL =5 LDS/UDS (Input) LQS/UQS Low (Output) CL=5 WL=4 DQ (Output) Hi-Z D a 0 Da1 D a 2 D a 3 Q b 0 Qb1 Q b 2 Qb3 Da0 Da1 Da2 Da3 Qb0 Q b 1 Qb2 Q b 3 CL =6 LDS/UDS (Input) LQS/UQS Low (Output) CL=6 WL=5 DQ Hi-Z D a 0 Da1 D a 2 D a 3 (Output) Q b 0 Qb1 Q b 2 Qb3 Da0 Da1 Da2 Da3 Qb0 Q b 1 Unidirectional DS/Free Running QS mode CL =4 LDS/UDS (Input) LQS/UQS (Output) CL=4 WL=3 DQ Hi-Z D a 0 Da1 D a 2 D a 3 (Output) Q b 0 Q b 1 Q b 2 Qb3 D a 0 Da1 D a 2 D a 3 Qb0 Q b 1 Qb2 Q b 3 CL =5 LDS/UDS (Input) LQS/UQS (Output) WL=4 DQ CL=5 Hi-Z D a 0 Da1 D a 2 D a 3 (Output) Q b 0 Qb1 Q b 2 Qb3 Da0 Da1 Da2 Da3 Qb0 Q b 1 Qb2 Q b 3 CL =6 LDS/UDS (Input) LQS/UQS (Output) WL=5 DQ (Output) CL=6 Hi-Z D a 0 Da1 D a 2 D a 3 Q b 0 Qb1 Q b 2 Qb3 Da0 Da1 Da2 Da3 Qb0 Q b 1 N o t e : IR C t o t h e s a m e b a n k m u s t b e s a t i s f i e d . - 39 - REV. 0.0 Sep. 2002 K4C89363AF Write with Variable Write Length (VW) Control(CL=4) 0 1 2 3 4 5 6 WRA LAL UA LA=#1 VW=1 7 8 9 10 11 12 13 14 15 CLK CLK BL=2, SEQUENTIAL MODE Command Address WRA LAL UA LA=#3 VW=All DESL VW0 = Low VW1 = don’t care Bank Add. DESL VW0 = High VW1 = don’t care Bank "a" Bank "a" LDS/UDS (Input) LQS/UQS (Input) D0 D1 D0 Lower Address #3 #2 #1 (#0) Last one data is masked. BL=4, SEQUENTIAL MODE Command Address WRA LAL UA LA=#3 VW=All DESL WRA LAL UA LA=#1 VW=1 VW0 = High VW1 = Low Bank Add. DESL WRA LAL UA LA=#2 VW=2 VW0 = High VW1 = High Bank "a" DESL VW0 = Low VW1 = High Bank "a" Bank "a" LDS/UDS (Input) LQS/UQS (Input) Lower Address D0 D1 D2 D3 #3 #0 #1 #2 D0 #1 (#2) (#3) (#0) Last three data are masked. D0 D1 #2 #3 (#0) (#1) Last two data are masked. Note : DS input must be continued till end of burst count even if some of laster data is masked. - 40 - REV. 0.0 Sep. 2002 K4C89363AF Power Down Timing (CL=4, BL=4) Read cycle to Power Down Mode 0 1 2 3 4 5 6 7 8 9 CLK RDA LAL UA LA DESL n n+1 n+2 DESL RDA or WRA n+3 IP D A ∼ ∼ Address n-1 ∼ ∼ BL=2, SEQUENTIAL MODE Command 10 ∼ ∼ CLK t IH tI S UA I P D =2 cycle ∼ ∼ PD tQ P D H tPDEX IR C ( m i n ) , tR E F I ( m a x ) Unidirectional DS/QS mode ∼ ∼ LDS/UDS (Input) Low DQ (Output) Hi-Z ∼ ∼ LQS/UQS (Output) CL=4 Q1 Q2 Q3 Q0 Q1 Q2 Q3 Hi-Z ∼ ∼ Q0 Unidirectional DS/Free Running QS mode ∼ ∼ LDS/UDS (Input) ∼ ∼ LQS/UQS (Output) CL=4 Hi-Z Hi-Z ∼ ∼ DQ (Output) Power Down Entry Power Down Exit Note : P D must be kept "High" level until end of Burst data output. P D should be brought to "High" within tR E F I (max.) to maintain the data written into cell. In Power Down Mode, P D "Low" and a stable clock signal must be maintained. W h e n PD is brought to "High", a valid executable command may be applied I P D A cycles later. - 41 - REV. 0.0 Sep. 2002 K4C89363AF Power Down Timing (CL=4, BL=4) Write cycle to Power Down Mode 0 1 2 3 4 5 6 7 8 9 10 n-1 n n+1 n+2 n+3 ∼ ∼ CLK CLK IP D A LAL UA LA DESL DESL RDA or WRA ∼ ∼ Address WRA ∼ ∼ Command t IH tI S I P D =2 cycle ∼ ∼ PD UA tPDEX WL=3 IP D =2 cycle IR C ( m i n ) , tR E F I ( m a x ) Unidirectional DS/QS mode ∼ ∼ LDS/UDS (Input) Low ∼ ∼ LQS/UQS (Output) WL=3 D0 D1 D2 D3 D0 D1 D2 D3 ∼ ∼ DQ (Output) Unidirectional DS/Free Running QS mode ∼ ∼ LDS/UDS (Input) ∼ ∼ LQS/UQS (Output) WL=3 ∼ ∼ DQ (Output) Note : P D must be kept "High" level until end of Burst data output. P D should be brought to "High" within tR E F I (max.) to maintain the data written into cell. In Power Down Mode, P D "Low" and a stable clock signal must be maintained. W h e n PD is brought to "High", a valid executable command may be applied I P D A cycles later. - 42 - REV. 0.0 Sep. 2002 K4C89363AF Mode Register Set Timing (CL=4, BL=2) From Read operation to Mode Register Set operation 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RDA or WRA LAL Valid (opcode) UA LA BA0="0" BA1="0" BA CLK CLK l R C =7cycles RDA LAL A14~A0 UA LA BA0, BA1 BA Command DESL RDA MRS DESL CL + BL/2 Unidirectional DS/QS mode LDS/UDS (Input) LQS/UQS (Output) Low DQ (Output) Q0 Q1 Q0 Q1 Unidirectional DS/Free Running QS mode LDS/UDS (Input) LQS/UQS (Output) DQ (Output) Note : Minimum delay from LAL following RDA to RDA of MRS operation is CL+BL/2. - 43 - REV. 0.0 Sep. 2002 K4C89363AF Mode Register Set Timing (CL=4, BL=4) From Write operation to Mode Register Set operation 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RDA or WRA LAL Valid (opcode) UA LA BA0="0" BA1="0" BA CLK CLK l R C =7cycles WRA LAL A14~A0 UA LA BA0, BA1 BA Command DESL RDA MRS DESL WL + BL/2 Unidirectional DS/QS mode LDS/UDS (Input) LQS/UQS (Output) Low DQ (Output) D0 D1 D2 D3 D0 D1 D2 D3 Unidirectional DS/Free Running QS mode LDS/UDS (Input) LQS/UQS (Output) DQ (Output) Note : Minimum delay from LAL following WRA to RDA of MRS operation is WL+BL/2. - 44 - REV. 0.0 Sep. 2002 K4C89363AF Extended Mode Register Set Timing (CL=4, BL=2) From Read operation to Extended Mode Register Set operation 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RDA or WRA LAL Valid (opcode) UA LA BA0="0" BA1="0" BA CLK CLK l R C =7cycles RDA LAL A14~A0 UA LA BA0, BA1 BA Command DESL RDA MRS DESL CL + BL/2 Unidirectional DS/QS mode LDS/UDS (Input) LQS/UQS (Output) Low DQ (Output) Q0 Q1 Q0 Q1 Unidirectional DS/Free Running QS mode LDS/UDS (Input) LQS/UQS (Output) DQ (Output) Note : M i n i m u m d e l a y f r o m L A L f o l l o w i n g R D A t o R D A o f E M R S o p e r a t i o n i s C L + B L / 2 . When DQ strobe mode is changed by EMRS, QS output is invalid for I R S C p e r i o d . DLL switch in Extended Mode Register must be set to enable mode for normal operation. DLL lock-on time is needed after initial EMRS operation. See Power Up Sequence. - 45 - REV. 0.0 Sep. 2002 K4C89363AF Extended Mode Register Set Timing (CL=4, BL=4) From Write operation to Extended Mode Register Set operation 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RDA or WRA LAL Valid (opcode) UA LA BA0="0" BA1="0" BA CLK CLK l R C =7cycles WRA LAL A14~A0 UA LA BA0, BA1 BA Command DESL RDA MRS DESL WL + BL/2 Unidirectional DS/QS mode LDS/UDS (Input) LQS/UQS (Output) Low DQ (Output) D0 D1 D2 D3 D0 D1 D2 D3 Unidirectional DS/Free Running QS mode LDS/UDS (Input) LQS/UQS (Output) DQ (Output) Note : When DQ strobe mode is changed by EMRS, QS output is invalid for I R S C p e r i o d . DLL switch in Extended Mode Register must be set to enable mode for normal operation. DLL lock-on time is needed after initial EMRS operation. See Power Up Sequence. Minimum delay from LAL following WRA to RDA of EMRS operation is WL+BL/2. - 46 - REV. 0.0 Sep. 2002 K4C89363AF Auto-Refresh Timing (CL=4, BL=4) Unidirectional DS/QS mode 0 1 2 3 4 5 6 7 n-1 n n+1 n+2 RDA or WRA LAL or MRS or REF RDA or WRA LAL or MRS or REF CLK CLK l R C =5cycles LAL Bank, Address Bank, UA LA DESL l R C D =1cycle REF DESL l R A S= 4 c y c l e s l R C D =1cycle Low Low ∼ ∼ LQS/UQS (output) WRA ∼ ∼ RDA ∼ ∼ Command lR E F C = 1 9 c y c l e s CL=4 Hi-Z Q0 Q1 Q2 Q3 ∼ ∼ DQ (output) Hi-Z Unidirectional DS/Free Running QS mode CLK CLK l R C =5cycles LAL Bank, Address Bank, UA LA DESL WRA REF DESL ∼ ∼ RDA ∼ ∼ Command lR E F C = 1 9 c y c l e s lR C D = 1 c y c l e s l R A S= 4 c y c l e s l R C D =1cycles ∼ ∼ LQS/UQS (output) CL=4 Hi-Z Q0 Q1 Q2 Q3 ∼ ∼ DQ (output) Hi-Z Note : In case of CL=4, IR E F C must be meet 19 clock cycles. When the Auto-Refresh operation is perfomed, the synthetic average interval of Auto-Refresh command specified by tR E F I m u s t b e s a t i s f i e d . tR E F I is average interval time in 8 Refresh cycles that is sampled randomly. t1 t2 ∼ ∼ WRAREF t8 ∼ ∼ WRA REF t7 ∼ ∼ WRA REF ∼ ∼ ∼ ∼ CLK t3 WRAREF WRA REF 8 Refresh cycle t + t + t + t +t +t +t +t tR E F I = Total time of 8 Refresh cycle = 1 2 3 4 5 6 7 8 8 8 tR E F I is specified to avoid partly concentrated current of Refresh operation that is acivated larger are than Read/Write operation. - 47 - REV. 0.0 Sep. 2002 K4C89363AF Self-Refresh Entry Timing Unidirectional DS/QS mode 0 1 2 3 4 5 6 8 9 10 11 lR C D = 1 c y c l e s lR E F C tF P D L DESL tFPDL (min) (max) ∼ ∼ REF ∼ ∼ WRA ∼ ∼ CLK Command 7 ∼ ∼ CLK Auto Refresh Self Refresh Entry ∼ ∼ ∼ ∼ PD l P D V* 2 tQ P D H ∼ ∼ ∼ ∼ LOW Qx ∼ ∼ Hi-Z ∼ ∼ DQ (output) Hi-Z lC K D LQS/UQS (output) Note : 1. is don’t care. 2. P D must be brought to "Low" within the timing between t F P D L (min) and t F P D L (max) to Self R e f r e s h m o d e . W h e n PD is brought to "Low" after I P D V , K 4 C 8 9 1 8 3 A D perform Auto Refresh and enter Power down mode. 3. It is desirable that clock input is continued at least I C K D f r o m R E F c o m m a n d e v e n t h o u g h P D is brought to "Low" for Self-Refresh Entry. Self-Refresh Exit Timing Unidirectional DS/QS mode 0 1 3 m-1 m m+1 m+2 *2 lR E F C DESL *4 l P D A =2 c y c l e s WRA *5 REF *5 DESL p-1 p C o m m a n d ( 2 n d ) *6 l R C D = 1cycle ∼ ∼ Command n+1 C o m m a n d ( 1 s t ) *6 lR E F C ∼ ∼ ∼ ∼ ∼ ∼ *3 n ∼ ∼ CLK n-1 ∼ ∼ ∼ ∼ ∼ ∼ CLK RDA*7 L A L* 7 l R C D = 1cycle ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ tP D E X PD lL O C K Hi-Z ∼ ∼ ∼ ∼ DQ (output) ∼ ∼ ∼ ∼ LQS/UQS (output) Hi-Z LOW Self-Refresh Exit Note : 1. is don’t care. 2. Clock should be stable prior to PD = "High" if clock input is suspended in Self-Refresh mode. 3 . D E S L c o m m a n d m u s t b e a s s e r t e d d u r i n g I R E F C after P D is brought to "High" 4. l P D A is defined from the first clock rising edge after PD is brought to "High" 5. It is desirable that one Auto-Refresh command is issued just after Self-Refresh Exit before any other operation. 6. Any command (except Read command) can be issued after lR E F C . 7. Read command (RDA +LAL) can be issued after lL C O K . - 48 - REV. 0.0 Sep. 2002 K4C89363AF Self-Refresh Entry Timing Unidirectional DS/Free Running QS mode 0 1 2 3 4 5 m-1 m+1 l R C D =1cycle REF (min) DESL tFPDL (max) ∼ ∼ tF P D L lR E F C ∼ ∼ WRA ∼ ∼ CLK Command m ∼ ∼ CLK Auto Refresh ∼ ∼ ∼ ∼ PD Self Refresh Entry l P D V* 2 tQ P D H ∼ ∼ lC K D LQS/UQS (output) Qx ∼ ∼ Hi-Z ∼ ∼ DQ (output) Hi-Z Note : 1. is don’t care. 2. P D must be brought to "Low" within the timing between t F P D L (min) and t F P D L (max) to Self R e f r e s h m o d e . W h e n P D is brought to "Low" after IP D V , K 4 C 8 9 1 8 3 A D p e r f o r m A u t o R e f r e s h a n d e n t e r Power down mode. 3. It is desirable that clock input is continued at least I C K D f r o m R E F c o m m a n d e v e n t h o u g h P D is brought to "Low" for Self-Refresh Entry. Self-Refresh Exit Timing Unidirectional DS/Free Running QS mode 0 1 3 m-1 m m+1 m+2 lR E F C *4 l P D A =2 c y c l e s WRA *5 REF *5 DESL p-1 p C o m m a n d ( 2 n d ) *6 l R C D = 1cycle ∼ ∼ DESL n+1 C o m m a n d ( 1 s t ) *6 lR E F C ∼ ∼ ∼ ∼ ∼ ∼ Command n ∼ ∼ CLK n-1 ∼ ∼ ∼ ∼ ∼ ∼ CLK RDA*7 L A L* 7 l R C D = 1cycle ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ tP D E X PD lL O C K ∼ ∼ ∼ ∼ LQS/UQS QS (output) Hi-Z ∼ ∼ ∼ ∼ DQ (output) Self-Refresh Exit Note : 1. is don’t care. 2. Clock should be stable prior to PD = "High" if clock input is suspended in Self-Refresh mode. 3 . D E S L c o m m a n d m u s t b e a s s e r t e d d u r i n g I R E F C after P D is brought to "High" 4. l P D A is defined from the first clock rising edge after PD is brought to "High" 5. It is desirable that one Auto-Refresh command is issued just after Self-Refresh Exit before any other operation. 6. Any command (except Read command) can be issued after lR E F C . 7 . R e a d c o m m a n d ( R D A + L A L ) c a n b e i s s u e d a f t e r l L O C K. 8. QS output is invalid until DLL lock from Self-Refresh exit. - 49 - REV. 0.0 Sep. 2002 K4C89363AF Function Description Network - DRAM Network - DRAM is an acronym of Double Data Rate Network - DRAM. Network - DRAM is competent to perform fast random core access, low latency and high-speed data transfer. Pin Functions Clock Inputs : CLK & CLK The CLK and C L K inputs are used as the reference for synchronous operation. CLK is master clock input. The C S, FN and all address input signals are sampled on the crossing of the positive edge of CLK and the negative edge of CLK . The QS and DQ output data are aligned to the crossing point of CLK and C L K . The timing reference point for the differential clock is when the CLK and C L K signals cross during a transition. Power Down : PD T h e PD input controls the entry to the Power Down or Self-Refresh modes. The PD input does not have a Clock Suspend function like a CKE input of a standard SDRAMs, therefore it is illegal to bring PD pin into low state if any Read or Write operation is being performed. Chip Select & Function Control : C S & FN The C S and FN inputs are a control signal for forming the operation commands on Network-DRAM. Each operation mode is decided by the combination of the two consecutive operation commands using the C S and FN inputs. Bank Addresses : BA0 & BA1 The BA0 and BA1 inputs are latched at the time of assertion of the RDA or WRA command and are selected the bank to be used for the operation. BA0 and BA1 also define which mode register is loaded during the Mode Register Set command (MRS or EMRS). BA0 BA1 Bank #0 0 0 Bank #1 1 0 Bank #2 0 1 Bank #3 1 1 Address Inputs : A0 to A14 A d d r e s s i n p u t s a r e u s e d t o a c c e s s t h e a r b i t r a r y a d d r e s s o f t h e m e m o r y c e l l a r r a y w i t h i n e a c h b a n k . T h e U p p e r A d d r e s s e s w i t h B an k address are latched at the RDA or WRA command and the Lower Addresses are latched at the LAL command. The A0 to A14 inputs are also used for setting the data in the Regular or Extended Mode Register set cycle. K4C89363AF Upper Address Lower Address A0 to A14 A0 to A6 - 50 - REV. 0.0 Nov. 2002 K4C89363AF Functional Description (Continued) Data Input/Output : DQ0 ~ DQ35 The input data of DQ0 to DQ35 are taken in synchronizing with the both edges of LDS/UDS input signal. The output data of DQ0 to DQ35 are outputted synchronizing with the both edges of LQS/UQS output signal. Data Strobe : DS(LDS/UDS) or QS(LQS/UQS) Method of data strobe is chosen by Extended mode register. (1) Unidirectional DS/QS mode DS is input signal and QS is output signal. Both edges of DS are used to sample all DQs at Write operation. Both edges of QS are used for trigger signal of all DQs at Read operation. During Write, Auto-Refresh and NOP cycle, QS assert always "Low" level. QS is Hi-Z in Self-Refresh mode. (2) Unidirectional DS/Free running QS mode DS is input signal and QS is output signal. Both edges of DS are used to sample all DQs at Write operation. Both edges of QS are used for trigger signal of all DQs at Read operation. QS assert always toggle signal except Self-Refresh mode. This strobe type is easy to use for pin to pin connect application. P o w e r S u p p l y : V D D , V D D Q , V SS , V S S Q V D D a n d V SS a r e s u p p l y p i n s f o r m e m o r y c o r e a n d p e r i p h e r a l c i r c u i t s . V DDQ a n d V S S Q a r e p o w e r s u p p l y p i n s f o r t h e o u t p u t b u f f e r . Reference Voltage : V REF V REF is reference voltage for all input signals. - 51 - REV. 0.0 Nov. 2002 K4C89363AF Command Functions and Operations K4C89363AF is introduced the two consecutive command input method. Therefore, except for Power Down mode, each operation mode decided by the combination of the first command and the second command from stand-by states of the bank to be accessed. Read Operation (1st command + 2nd command = RDA + LAL) Issuing the RDA command with Bank Addresses and Upper Addresses to the idle bank puts the bank designated by Bank Address in a read mode. When the LAL command with Lower Addresses is issued at the next clock of the RDA command, the data is read out sequentially synchronizing with the both edges of QS output signal (Burst Read Operation). The initial valid read data appears a fter C A S latency, the burst length of read data and the burst type must be set in the Mode Register beforehand. The read operated bank g o e s b a c k a u t o m a t i c a l l y t o t h e i d l e s t a t e a f t e r I RC. Write Operation (1st command + 2nd command = WRA + LAL) Issuing the WRA command with Bank Addresses and Upper Addresses to the idle bank puts the bank designated by Bank Address in a write mode. When the LAL command with Lower Addresses is issued at the next clock of the WRA command, the input data is latched sequentially synchronizing with the both edges of DS input signal (Burst Write Operation). The data and DS inputs have to be asserted in keeping with clock input after C A S latency-1 from the issuing of the LAL command. The DS have to be provided for a burst length. The C A S latency and the burst type must be set in the Mode Register beforehand. The write operated bank goes back automatically to the idle state after IRC. W r i t e B u r s t L e n g t h i s c o n t r o l l e d b y V W 0 a n d V W 1 i n p u t s w i t h L A L c o m m a n d . S e e V W t r u t h t a b l e . Auto-Refresh Operation (1st command + 2nd command = WRA + REF) K4C89363AF is required to refresh like a standard SDRAM. The Auto-Refresh operation is begun with the REF command following to the WRA command. The Auto-Refresh mode can be effective only when all banks are in the idle state and all DQ are in Hi-Z states. In a point to notice, the write mode started with the WRA command is canceled by the REF command having gone into the next clock of the WRA command instead of the LAL command. The minimum period between the Auto-Refresh command and the next command is specified by IREFC. H o w e v e r , a b o u t a s y n t h e t i c a v e r a g e i n t e r v a l o f A u t o - R e f r e s h c o m m a n d , i t m u s t b e c a r e f u l . I n c a s e o f e q u a l l y d i s tributed refresh, Auto-Refresh command has to be issued within once for every 3.9 us by the maximum In case of burst refresh or random distributed refresh, the average interval of eight consecutive Auto-Refresh command has to be more than 400ns always. In oth er words, the number of Auto-Refresh cycles which can be performed within 3.2 us (8x400ns) is to 8 times in the maximum. Self-Refresh Operation (1st command + 2nd command = WRA + REF with PD ="L") It is the function of Self-Refresh operation that refresh operation can be performed automatically by using an internal timer. When all banks are in the idle state and all outputs are in Hi-z states, the K4C89363AF become Self-Refresh mode by issuing the Self-Refresh c o m m a n d . P D h a s t o b e b r o u g h t t o " L o w " w i t h i n t FPDL f r o m t h e R E F c o m m a n d f o l l o w i n g t o t h e W R A c o m m a n d f o r a S e l f - R e f r e s h m o d e entry. In order to satisfy the refresh period, the Self-Refresh entry command should be asserted within 3.9us after the latest AutoR e f r e s h c o m m a n d . O n c e t h e d e v i c e e n t e r s S e l f - R e f r e s h m o d e , t h e D E S L c o m m a n d m u s t b e c o n t i n u e d f o r I REFC period. In addition, it is desirable that clock input is kept in ICKD period. The device is in Self-Refresh mode as long as P D held "Low". During Self-Refresh mode, all input and output buffers except for PD are disabled, therefore the power dissipation lowers. Regarding a Self-Refresh mode exit, P D h a s t o b e c h a n g e d o v e r f r o m " L o w " t o " H i g h " a l o n g w i t h t h e D E S L c o m m a n d , a n d t h e D E S L c o m m a n d h a s t o b e c o n t i n u o u s l y i s s u e d i n t h e n u m b e r o f c l o c k s s p e c i f i e d b y I REFC . The Self-Refresh exit function is asynchronous operation. It is required that one A u t o - R e f r e s h c o m m a n d i s i s s u e d t o a v o i d t h e v i o l e n c e o f t h e r e f r e s h p e r i o d j u s t a f t e r I REFC from Self-Refresh exit. - 52 - REV. 0.0 Nov. 2002 K4C89363AF Power Down Mode( P D="L" ) When all banks are in the idle state and all DQ outputs are in Hi-Z states, the K4C89363AF become Power Down Mode by asserting PD is "Low". When the device enters the Power Down Mode, all input and output buffers except for PD , CLK, C L K and QS. Therefore, the power dissipation lowers. To exit the Power Down Mode, PD has to be brought to "High" and the DESL command has to be issued for IP D A c y c l e a f t e r P D g o e s h i g h . T h e P o w e r D o w n e x i t f u n c t i o n i s a s y n c h r o n o u s o p e r a t i o n . Mode Register Set (1st command + 2nd command = RDA + MRS) When all banks are in the idle state, issuing the MRS command following to the RDA command can program the Mode Register. In a point to notice, the read mode started with the RDA command is canceled by the MRS command having gone into the next clock of the RDA command instead of the LAL command. The data to be set in the Mode Register is transferred using A0 to A14, BA0 and BA1 address inputs. The K4C89363AF have two mode registers. These are Regular and Extended Mode Register. The Regular or Extended Mode Register is chosen by BA0 and BA1 in the MRS command.The Regular Mode Register designates the operation mode for a read or write cycle. The Regular Mode Register has four function fields. The four fields are as follows : (R-1) Burst Length field to set the length of burst data (R-2) Burst Type field to designate the lower address access sequence in a burst cycle (R-3) C A S Latency field to set the access time in clock cycle (R-4) Test Mode field to use for supplier only. The Extended Mode Register has two function fields. The two fields are as follows: (E-1) DLL Switch field to choose either DLL enable or DLL disable (E-2) Output Driver Impedance Control field. (E-3) Data Strobe Select Once these fields in the Mode Register are set up, the register contents are maintained until the Mode Register is set up again b y another MRS command or power supply is lost. The initial value of the Regular or Extended Mode Register after power-up is undefined, therefore the Mode Register Set command must be issued before proper operation. - 53 - REV. 0.0 Nov. 2002 K4C89363AF • Regular Mode Register/Extended Mode Register change bits (BA0, BA1) These bits are used to choose either Regular MRS or Extended MRS BA1 BA0 A14~A0 0 0 Regular MRS cycle 0 1 Extended MRS cycle 1 X Reserved Regular Mode Register Fields (R-1) Burst Length field (A2 to A0) This field specifies the data length for column access using the A2 to A0 pins and sets the Burst Length to be 2 or 4 words. A2 A1 A0 Burst Length 0 0 0 Reserved 0 0 1 2 words 0 1 0 4 words 0 1 1 Reserved 1 X X Reserved (R-2) Burst Type field (A3) This Burst Type can be chosen Interleave mode or Sequential mode. When the A3 bit is " 0", Sequential mode is selected. When the A3 bit is "1", Interleave mode is selected. Both burst types support burst length of 2 and 4 words. A3 Burst Type 0 Sequential 1 Interleave • Addressing sequence of Sequential mode (A3) A column access is started from the inputted lower address and is performed by incrementing the lower address input to the device. C A S Latency = 4 (Free Running QS mode) CK CK Command RDA LAL QS DQ Data 0 Data 1 Data 2 Data 3 Addressing sequence for Sequential mode Data Access Address Data 0 n Burst Length Data 1 n + 1 not carried from LA0~LA1 Data 2 n + 2 4 words(Address bits is LA1, LA0) Data 3 n + 3 2 words (Address bits is LA0) not carried from LA1~LA2 - 54 - REV. 0.0 Nov. 2002 K4C89363AF Functional Description (Continued) • Addressing sequence of Inteleave mode A column access is started from the inputted lower address and is performed by interleaving the address bits in the sequence shown as the following. Addressing sequence for Interleave mode Data Access Address Burst Length Data 0 ...A8 A7 A6 A5 A4 A3 A2 A1 A0 Data 1 ...A8 A7 A6 A5 A4 A3 A2 A1 A 0 Data 2 ...A8 A7 A6 A5 A4 A3 A2 A 1 A 0 Data 3 ...A8 A7 A6 A5 A4 A3 A2 A 1 A 0 2 words 4 words (R-3) C A S Latency field (A6 to A4) This field specifies the number of clock cycles from the assertion of the LAL command following the RDA command to the first data read. The minimum values of C A S Latency depends on the frequency of CLK. In a write mode, the place of clock which should input write data is C A S Latency cycles - 1. Addressing sequence for Interleave mode A6 A5 A4 CAS Latency 0 0 0 Reserved 0 0 1 Reserved 0 1 0 Reserved 0 1 1 Reserved 1 0 0 4 1 0 1 5 1 1 0 6 1 1 1 Reserved (R-4) Test Mode field (A7) This bit is used to enter Test Mode for supplier only and must be set to "0" for normal operation. (R-5) Reserved field in the Regular Mode Register • Reserved bits (A8 to A14) These bits are reserved for future operations. They must be set to "0" for normal operation. - 55 - REV. 0.0 Nov. 2002 K4C89363AF Extended Mode Register Fields (E-1) DLL Switch field (A0) This bit is used to enable DLL. When the A0 bit is set "0", DLL is enabled. (E-2) Output Driver Impedance Control field (A1 to A4) This field is used to choose Output Driver Strength. Four types of Driver Strength are supported. QS and DQ Driver Strength can be chosen separately. A2-A1 specified the DQ Driver Strength. A4-A3 specified the QS Driver Strength. QS DQ Output Driver Impedance Control A4 A3 A2 A1 0 0 0 0 Normal Output Driver 0 1 0 1 Strong Output Driver 1 0 1 0 Weaker Output Driver 1 1 1 1 Reserved (E-3) Strobe Select (A6/A5) Two types of strobe are supported. This field is used to choose the type of data strobe. (1) Unidirectional DS/QS mode Data strobe is separated DS for write strobe and QS for read strobe. DS is used to sample write data at write operation. QS is aligned with read data at Read operation. (2) Unidirectional DS/Free running QS mode Data strobe is separated DS for write strobe and QS for read strobe. DS is used to sample write data at write operation. QS is aligned with read data and always clocking A6 A5 Strobe Select 0 0 Reserved 0 1 Reserved 1 0 Unidirectional DS/QS mode 1 1 Unidirectional DS/Free running QS mode (E-4)Reserved fied (A7 to A14) These bits are reserved for future operations and must be set to "0" for normal operation. - 56 - REV. 0.0 Nov. 2002 K4C89363AF Package Outline Drawing (FBGA 144ball, 1.0 x 0.8 mm) - will be added - 57 - REV. 0.0 Nov. 2002 K4C89363AF General Information Organization F6 (667Mbps) FB (600Mbps ) F5 (500Mbps ) 288M(x32) K4C89323AF-GCF6 K4C89323AF-GCFB K4C89323AF-GCF5 288M(x36) K4C89363AF-GCF6 K4C89363AF-GCFB K4C89363AF-GCF5 1 5 2 3 4 6 7 8 K 4 C XX XX X X X 9 10 11 - X X XX Memory Speed DRAM Temperature & Power Small Classification Package Density and Refresh Version Organization Bank Interface (VDD & VDDQ) 1. SAMSUNG Memory : K 8. Version F : 7th Generation 2. DRAM : 4 3. Small Classification C 9. P a c k a g e : Network-DRAM T : TSOP II (400mil x 875mil) 4. Density & Refresh 89 : 288M G : 144 FBGA 8K/32ms 10. Temperature & Power C : (Commercial, Normal) 5. Organization 32 : x32 36 : x36 11. Speed F6 : 667Mbps/pin (333MHz, CL=6) FB : 600Mbps /pin (300MHz, CL=6) 6. Bank F5 : 500Mbps/pin (250MHz, CL=6) 3 : 4 Bank 7. Interface (VDD & VDDQ) A: SSTL-2(2.5V, 1.8V) - 58 - REV. 0.0 Nov. 2002