SAMSUNG K4M51323PC-SG75

K4M51323PC-S(D)E/G/C/F
Mobile-SDRAM
4M x 32Bit x 4 Banks Mobile SDRAM in 90FBGA
FEATURES
GENERAL DESCRIPTION
•
•
•
•
The K4M51323PC is 536,870,912 bits synchronous high data
rate Dynamic RAM organized as 4 x 4,196,304 words by 32 bits,
fabricated with SAMSUNG’s high performance CMOS technology. Synchronous design allows precise cycle control with the
use of system clock and I/O transactions are possible on every
clock cycle. Range of operating frequencies, programmable
burst lengths and programmable latencies allow the same
device to be useful for a variety of high bandwidth and high performance memory system applications.
1.8V power supply.
LVCMOS compatible with multiplexed address.
Four banks operation.
MRS cycle with address key programs.
-. CAS latency (1, 2 & 3).
-. Burst length (1, 2, 4, 8 & Full page).
-. Burst type (Sequential & Interleave).
• EMRS cycle with address key programs.
• All inputs are sampled at the positive going edge of the system
clock.
• Burst read single-bit write operation.
• Special Function Support.
-. PASR (Partial Array Self Refresh).
-. Internal TCSR (Temperature Compensated Self Refresh)
-. DS (Driver Strength)
-. DPD (Deep Power Down)
• DQM for masking.
• Auto refresh.
• 64ms refresh period (8K cycle).
• Extended Temperature Operation (-25°C ~ 85°C).
• Commercial Temperature Operation (-25°C ~ 70°C).
• 90Balls FBGA( -SXXX -Pb, -DXXX -Pb Free).
ORDERING INFORMATION
Part No.
Max Freq.
K4M51323PC-S(D)E/G/C/F75
133MHz(CL=3),83MHz(CL=2)
K4M51323PC-S(D)E/G/C/F90
111MHz(CL=3),83MHz(CL=2)
K4M51323PC-S(D)E/G/C/F1L
111MHz(CL=3)*1,66MHz(CL2)
Interface
Package
LVCMOS
90 FBGA Pb
(Pb Free)
- S(D)E/G : Normal / Low Power, Extended Temperature(-25°C ~ 85°C)
- S(D)C/F : Normal / Low Power, Commercial Temperature(-25°C ~ 70°C)
Notes :
1. In case of 40MHz Frequency, CL1 can be supported.
Address configuration
Organization
Bank
Row
Column Address
16Mx32
BA0,BA1
A0 - A12
A0 - A8
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could
result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply.
February 2006
K4M51323PC-S(D)E/G/C/F
Mobile-SDRAM
FUNCTIONAL BLOCK DIAGRAM
I/O Control
Data Input Register
Bank Select
4M x 32
4M x 32
Output Buffer
Sense AMP
Row Decoder
Row Buffer
Refresh Counter
ADD
Address Register
CLK
4M x 32
LWE
LDQM
DQi
4M x 32
Col. Buffer
LCBR
LRAS
Column Decoder
Latency & Burst Length
LCKE
Programming Register
LRAS
LCBR
LWE
LCAS
LWCBR
LDQM
Timing Register
CLK
CKE
CS
RAS
CAS
WE
DQM
February 2006
K4M51323PC-S(D)E/G/C/F
Mobile-SDRAM
Package Dimension and Pin Configuration
< Top View*2 >
< Bottom View*1 >
E1
9
8
7
6
5
90Ball(6x15) FBGA
4
3
2
1
1
2
3
7
8
9
A
DQ26
DQ24
VSS
VDD
DQ23
DQ21
B
B
DQ28
VDDQ
VSSQ
VDDQ
VSSQ
DQ19
C
C
VSSQ
DQ27
DQ25
DQ22
DQ20
VDDQ
D
D
VSSQ
DQ29
DQ30
DQ17
DQ18
VDDQ
E
E
VDDQ
DQ31
NC
NC
DQ16
VSSQ
F
VSS
DQM3
A3
A2
DQM2
VDD
G
A4
A5
A6
A10
A0
A1
e
A
F
H
D
D1
G
J
K
L
M
N
P
R
H
A7
A8
A12
NC
BA1
A11
J
CLK
CKE
A9
BA0
CS
RAS
K
DQM1
NC
NC
CAS
WE
DQM0
L
VDDQ
DQ8
VSS
VDD
DQ7
VSSQ
M
VSSQ
DQ10
DQ9
DQ6
DQ5
VDDQ
N
VSSQ
DQ12
DQ14
DQ1
DQ3
VDDQ
P
DQ11
VDDQ
VSSQ
VDDQ
VSSQ
DQ4
R
DQ13
DQ15
VSS
VDD
DQ0
DQ2
E
A
A1
b
z
< Top View*2 >
#A1 Ball Origin Indicator
Pin Name
Pin Function
CLK
System Clock
CS
Chip Select
SAMSUNG
Week
K4M51323PC-XXXX
CKE
Clock Enable
A0 ~ A12
Address
BA0 ~ BA1
Bank Select Address
RAS
Row Address Strobe
CAS
Column Address Strobe
WE
Write Enable
DQM0 ~ DQM3
Data Input/Output Mask
DQ0 ~ 31
Data Input/Output
VDD/VSS
Power Supply/Ground
VDDQ/VSSQ
Data Output Power/Ground
[Unit::mm]
Symbol
Min
Typ
Max
A
-
-
1.00
A1
0.25
-
-
E
10.9
11.0
11.1
E1
-
6.40
-
D
12.9
13.0
13.1
D1
-
11.2
-
e
-
0.80
-
b
0.45
0.50
0.55
z
-
-
0.10
February 2006
K4M51323PC-S(D)E/G/C/F
Mobile-SDRAM
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Unit
Voltage on any pin relative to Vss
VIN, VOUT
-1.0 ~ 2.6
V
Voltage on VDD supply relative to Vss
VDD, VDDQ
-1.0 ~ 2.6
V
TSTG
-55 ~ +150
°C
Power dissipation
PD
1.0
W
Short circuit current
IOS
50
mA
Storage temperature
NOTES:
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = -25 to 85°C for Extended, -25 to 70°C for Commercial)
Parameter
Symbol
Min
Typ
Max
Unit
Note
VDD
1.7
1.8
1.95
V
1
VDDQ
1.7
1.8
1.95
V
1
Input logic high voltage
VIH
0.8 x VDDQ
-
VDDQ + 0.3
V
2
Input logic low voltage
VIL
-0.3
0
0.3
V
3
Output logic high voltage
VOH
VDDQ -0.2
-
-
V
IOH = -0.1mA
Output logic low voltage
VOL
-
-
0.2
V
IOL = 0.1mA
ILI
-2
-
2
uA
4
Supply voltage
Input leakage current
NOTES :
1. Under all conditions, VDDQ must be less than or equal to VDD.
2. VIH (max) = 2.2V AC.The overshoot voltage duration is ≤ 3ns.
3. VIL (min) = -1.0V AC. The undershoot voltage duration is ≤ 3ns.
4. Any input 0V ≤ VIN ≤ VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with tri-state outputs.
4. Dout is disabled, 0V ≤ VOUT ≤ VDDQ.
CAPACITANCE (VDD = 1.8V, TA = 23°C, f = 1MHz, VREF =0.9V ± 50 mV)
Pin
Symbol
Min
Max
Unit
CCLK
1.5
3.5
pF
RAS, CAS, WE, CS, CKE
CIN
1.5
3.0
pF
DQM
CIN
1.5
3.0
pF
Address
CADD
1.5
3.0
pF
DQ0 ~ DQ31
COUT
2.0
4.5
pF
Clock
Note
February 2006
K4M51323PC-S(D)E/G/C/F
Mobile-SDRAM
DC CHARACTERISTICS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = -25 to 85°C for Extended, -25 to 70°C for Commercial)
Version
Parameter
Operating Current
(One Bank Active)
Precharge Standby Current in
power-down mode
Symbol
ICC1
ICC2P
Active Standby Current
in power-down mode
Active Standby Current
in non power-down mode
(One Bank Active)
Operating Current
(Burst Mode)
Refresh Current
Burst length = 1
tRC ≥ tRC(min)
IO = 0 mA
-75
-90
-1L
90
90
90
CKE ≤ VIL(max), tCC = 10ns
ICC3NS
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
1
10
mA
1
CKE ≤ VIL(max), tCC = 10ns
6
mA
3
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
25
mA
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable
15
mA
ICC4
IO = 0 mA
Page burst
4Banks Activated
tCCD = 2CLKs
100
85
85
mA
1
ICC5
tARFC ≥ tARFC(min)
150
150
150
mA
2
TCSR
-E/C
Self Refresh Current
mA
mA
ICC3PS CKE & CLK ≤ VIL(max), tCC = ∞
ICC3N
Note
0.3
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
ICC2NS
Input signals are stable
ICC3P
Unit
0.3
ICC2PS CKE & CLK ≤ VIL(max), tCC = ∞
ICC2N
Precharge Standby Current
in non power-down mode
Test Condition
ICC6
CKE ≤ 0.2V
45 *3
85/70
Full Array
300
600
1/2 of Full
270
500
1/4 of Full
255
450
Full Array
250
500
1/2 of Full
220
400
1/4 of Full
205
350
°C
4
uA
-G/F
Deep Power Down Current
ICC8
CKE ≤ 0.2V
10
5
uA
6
NOTES:
1. Measured with outputs open.
2. Refresh period is 64ms.
3. It has +/-5 °C tolerance.
4. K4M51323PC-S(D)E/C**
5. K4M51323PC-S(D)G/F**
6. DPD(Deep Power Down) function is an optional feature, and it will be enabled upon request.
Please contact Samsung for more information.
7. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ).
February 2006
K4M51323PC-S(D)E/G/C/F
Mobile-SDRAM
AC OPERATING TEST CONDITIONS(VDD = 1.7 ~ 1.95 V, TA = -25 ~ 85°C for Extended,
Parameter
AC input levels (Vih/Vil)
-25 ~ 70°C for Commercial)
Value
Unit
0.9 x VDDQ / 0.2
V
0.5 x VDDQ
V
tr/tf = 1/1
ns
0.5 x VDDQ
V
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
See Figure 2
VDDQ
13.9KΩ
Vtt=0.5 x VDDQ
VOH (DC) = VDDQ - 0.2V, IOH = -0.1mA
Output
VOL (DC) = 0.2V, IOL = 0.1mA
10.6KΩ
50Ω
20pF
Output
Z0=50Ω
20pF
Figure 1. DC Output Load Circuit
Figure 2. AC Output Load Circuit
February 2006
K4M51323PC-S(D)E/G/C/F
Mobile-SDRAM
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Version
Parameter
Symbol
-75
-90
-1L
Unit
Note
Row active to row active delay
tRRD(min)
15
18
18
ns
1
RAS to CAS delay
tRCD(min)
22.5
24
27
ns
1
Row precharge time
tRP(min)
22.5
24
27
ns
1
tRAS(min)
50
50
50
ns
1
Row active time
tRAS(max)
Row cycle time
tRC(min)
Last data in to row precharge
tRDL(min)
Last data in to Active delay
100
72.5
74
us
ns
1
15
ns
2
tDAL(min)
tRDL + tRP
-
Last data in to new col. address delay
tCDL(min)
1
CLK
2
Last data in to burst stop
tBDL(min)
1
CLK
2
Auto refresh cycle time
tARFC(min)
80
ns
3
Exit self refresh to active command
tSRFX(min)
120
ns
Col. address to col. address delay
tCCD(min)
1
CLK
4
ea
5
Number of valid output data
CAS latency=3
2
Number of valid output data
CAS latency=2
1
Number of valid output data
CAS latency=1
-
77
0
NOTES:
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next
higher integer.
2. Minimum delay is required to complete write.
3. Maximum burst refresh cycle : 8
4. All parts allow every cycle column address change.
5. In case of row precharge interrupt, auto precharge and read burst stop.
February 2006
K4M51323PC-S(D)E/G/C/F
Mobile-SDRAM
AC CHARACTERISTICS(AC operating conditions unless otherwise noted)
-75
Parameter
-90
-1L
Symbol
Min
Max
Min
Max
Unit
Note
ns
1
ns
1,2
ns
2
Max
CAS latency=3
tCC
7.5
CAS latency=2
tCC
12
CAS latency=1
tCC
-
CAS latency=3
tSAC
6
7
7
CAS latency=2
tSAC
9
9
10
CAS latency=1
tSAC
-
-
20
CAS latency=3
tOH
2.5
2.5
2.5
CAS latency=2
tOH
2.5
2.5
2.5
CAS latency=1
tOH
-
-
2.5
CLK high pulse width
tCH
2.5
3.0
3.0
ns
3
CLK low pulse width
tCL
2.5
3.0
3.0
ns
3
Input setup time
tSS
2.0
2.0
2.0
ns
3
Input hold time
tSH
1
1
1
ns
3
CLK to output in Low-Z
tSLZ
1
1
1
ns
2
CLK cycle time
CLK to valid output delay
Output data hold time
CAS latency=3
CLK to output in Hi-Z
CAS latency=2
CAS latency=1
tSHZ
9
Min
1000
12
9
1000
-
15
1000
25
6
7
7
9
9
10
-
-
20
ns
NOTES :
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
February 2006
K4M51323PC-S(D)E/G/C/F
Mobile-SDRAM
SIMPLIFIED TRUTH TABLE
COMMAND
Register
CKEn-1 CKEn
Mode Register Set
H
Auto Refresh
X
Entry
Self
Refresh
RAS
CAS
WE
L
L
L
L
X
OP CODE
L
L
L
H
X
X
Exit
3
L
L
3
L
H
H
H
H
X
X
X
H
3
X
X
3
Bank Active & Row Addr.
H
X
L
L
H
H
X
V
Read &
Auto Precharge Disable
Column Address
Auto Precharge Enable
H
X
L
H
L
H
X
V
Write &
Auto Precharge Disable
Column Address
Auto Precharge Enable
H
X
L
H
L
L
X
V
Entry
H
L
L
H
H
L
X
Exit
L
H
H
X
X
X
X
H
X
L
H
H
L
X
H
X
L
L
H
L
X
Row Address
L
Column
Address
(A0~A8)
H
L
Column
Address
(A0~A8)
H
Deep Power Down
4
4, 5
4
4, 5
X
Burst Stop
Bank Selection
Precharge
All Banks
Clock Suspend or
Active Power Down
Note
1, 2
H
H
Refresh
DQM BA0,1 A10/AP
A12,11,
A9 ~ A0
CS
Entry
H
H
X
X
X
L
V
V
V
X
X
X
X
H
X
X
X
L
H
H
H
H
X
X
X
L
Exit
L
H
Entry
H
L
Precharge Power Down
Mode
X
V
L
X
H
6
X
X
X
X
X
X
Exit
L
H
X
L
DQM
H
No Operation Command
H
V
V
V
X
H
X
X
X
L
H
H
H
X
V
X
X
X
7
(V=Valid, X=Don′t Care, H=Logic High, L=Logic Low)
NOTES :
1. OP Code : Operand Code
A0 ~ A12 & BA0 ~ BA1 : Program keys. (@MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are the same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
Partial self refresh can be issued only after setting partial self refresh mode of EMRS.
4. BA0 ~ BA1 : Bank select addresses.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at the positive going edge of CLK masks the data-in at that same CLK in write operation (Write DQM latency
is 0), but in read operation, it makes the data-out Hi-Z state after 2 CLK cycles. (Read DQM latency is 2).
February 2006
K4M51323PC-S(D)E/G/C/F
Mobile-SDRAM
A. MODE REGISTER FIELD TABLE TO PROGRAM MODES
Register Programmed with Normal MRS
BA0 ~ BA1
A12 ~ A10/AP
A9*2
"0" Setting for
Normal MRS
RFU*1
W.B.L
Address
Function
A8
A7
A6
Test Mode
A5
A4
A3
CAS Latency
A2
BT
A1
A0
Burst Length
Normal MRS Mode
Test Mode
CAS Latency
Burst Type
Burst Length
A8
A7
Type
A6
A5
A4
Latency
A3
Type
A2
A1
A0
BT=0
BT=1
0
0
Mode Register Set
0
0
0
Reserved
0
Sequential
0
0
0
1
1
0
1
Reserved
0
0
1
1
1
Interleave
0
0
1
2
2
1
0
Reserved
0
1
0
2
0
1
0
4
4
1
1
Reserved
0
1
1
3
0
1
1
8
8
Write Burst Length
1
0
0
Reserved
1
0
0
Reserved
Reserved
1
0
1
Reserved
1
0
1
Reserved
Reserved
1
1
0
Reserved
Reserved
1
1
1
A9
Length
Mode Select
BA1 BA0
0
0
Burst
1
1
0
Reserved
1
Single Bit
1
1
1
Reserved
Mode
Setting
for Normal MRS
0
Full Page*3 Reserved
Register Programmed with Extended MRS
Address
Function
BA1
BA0
A12 ~ A10/AP
Mode Select
A9
A8
A7
A6
A5
A4
DS
RFU*1
A3
A2
A1
A0
PASR
RFU*1
EMRS for PASR(Partial Array Self Ref.) & DS(Driver Strength)
Mode Select
Driver Strength
PASR *4
BA1
BA0
Mode
A6
A5
Driver Strength
A2
A1
A0
# of Banks
0
0
Normal MRS
0
0
Full
0
0
0
Full Array
0
1
Reserved
0
1
1/2
0
0
1
1/2 of Full Array
1
0
EMRS for Mobile SDRAM
1
0
1/4
0
1
0
1/4 of Full Array
1
1
Reserved
1
1
1/8
0
1
1
Reserved
1
0
0
Reserved
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Reserved
Reserved Address
A12~A10/AP
A9
A8
A7
A4
A3
0
0
0
0
0
0
NOTES:
1. RFU(Reserved for future use) should stay "0" during MRS cycle.
2. If A9 is high during MRS cycle, "Burst Read Single Bit Write" function will be enabled.
3. Full Page Length : x32 : 64Mb(256) , 128Mb (256), 256Mb (512), 512Mb (512)
4. Mobile SDRAM supports PASR of full array, 1/2 of full array and 1/4 of full array.
February 2006
K4M51323PC-S(D)E/G/C/F
Mobile-SDRAM
Partial Array Self Refresh
1. In order to save power consumption, Mobile SDRAM has PASR option.
2. Mobile SDRAM supports 3 kinds of PASR in self refresh mode : Full array, 1/2 of full array, 1/4 of full array
BA1=0
BA0=0
BA1=0
BA0=1
BA1=0
BA0=0
BA1=0
BA0=1
BA1=0
BA0=0
BA1=0
BA0=1
BA1=1
BA0=0
BA1=1
BA0=1
BA1=1
BA0=0
BA1=1
BA0=1
BA1=1
BA0=0
BA1=1
BA0=1
- Full Array
- 1/4 Array
- 1/2 Array
Partial Self Refresh Area
Temperature Compensated Self Refresh
Note :
1. In order to save power consumption, Mobile-SDRAM includes the internal temperature sensor and control units to control the
self refresh cycle automatically according to the two temperature range ; 45 °C and 85 °C(for Extended) / 70 °C(for Commercial).
2. If the EMRS for external TCSR is issued by the controller, this EMRS code for TCSR is ignored.
3. It has +/- 5 °C tolerance.
Self Refresh Current (IDD6)
Temperature Range
-E/C
-G/F
Unit
Full Array
1/2 Array
1/4 Array
Full Array
1/2 Array
1/4 Array
45 °C*3
300
270
255
250
220
205
85/70 °C
600
500
450
500
400
350
uA
B. POWER UP SEQUENCE
1. Apply power and attempt to maintain CKE at a high state and all other inputs may be undefined.
- Apply VDD before or at the same time as VDDQ.
2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us.
3. Issue precharge commands for all banks of the devices.
4. Issue 2 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
6. Issue a extended mode register set command to define DS or PASR operating type of the device after normal MRS.
For operating with DS or PASR, set DS or PASR mode in EMRS setting stage.
In order to adjust another mode in the state of DS or PASR mode, additional EMRS set is required but power up sequence is not
needed again at this time. In that case, all banks have to be in idle state prior to adjusting EMRS set.
February 2006
K4M51323PC-S(D)E/G/C/F
Mobile-SDRAM
C. BURST SEQUENCE
1. BURST LENGTH = 4
Initial Address
Sequential
Interleave
A1
A0
0
0
0
1
2
3
0
1
2
3
0
1
1
2
3
0
1
0
3
2
1
0
2
3
0
1
2
3
0
1
1
1
3
0
1
2
3
2
1
0
2. BURST LENGTH = 8
Initial Address
Sequential
Interleave
A2
A1
A0
0
0
0
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
0
1
1
2
3
4
5
6
7
0
1
0
3
2
5
4
7
6
0
1
0
2
3
4
5
6
7
0
1
2
3
0
1
6
7
4
5
0
1
1
3
4
5
6
7
0
1
2
3
2
1
0
7
6
5
4
1
0
0
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
1
0
1
5
6
7
0
1
2
3
4
5
4
7
6
1
0
3
2
1
1
0
6
7
0
1
2
3
4
5
6
7
4
5
2
3
0
1
1
1
1
7
0
1
2
3
4
5
6
7
6
5
4
3
2
1
0
February 2006