Preliminary K4X51323PC - 7(8)E/G Mobile-DDR SDRAM 16M x32 Mobile-DDR SDRAM 1 Revision 0.6 October 2005 Preliminary K4X51323PC - 7(8)E/G Mobile-DDR SDRAM Document Title 16M x32 Mobile-DDR SDRAM Revision History Revision No. History Draft Date Remark 0.0 - First version for target specification October 27. 2004 Target 0.1 - Insertion of PKG dimension of 90FBGA JEDEC Standard type. December 13. 2004 Target 0.2 - Preliminary Datasheet - Insertion DC Current value. December 20. 2004 Preliminary 0.3 - Changing Frequency from DDR333/DDR266 to DDR266/DDR222. - Updating DC current value. - Changing expression of PKG dimension. February 15. 2005 Preliminary 0.4 - Changing format with JEDEC standard type. February 18. 2005 Preliminary 0.5 - Insertion of Normal power bin. - Changing IDD3P/3PS - Changing IDD6 limit. September 07. 2005 Preliminary 0.6 - Define maximum burst refresh cycle. - Add a note related with Vdd & Vddq. - Add a note related with IDD8. October 18. 2005 2 Preliminary Revision 0.6 October 2005 Preliminary K4X51323PC - 7(8)E/G Mobile-DDR SDRAM 16M x32 Mobile-DDR SDRAM FEATURES • 1.8V power supply, 1.8V I/O power • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Four banks operation • 1 /CS • 1 CKE • Differential clock inputs(CK and CK) • MRS cycle with address key programs - CAS Latency ( 2, 3 ) - Burst Length ( 2, 4, 8, 16 ) - Burst Type (Sequential & Interleave) - Partial Self Refresh Type ( Full, 1/2, 1/4 Array ) - Output Driver Strength Control ( Full, 1/2, 1/4, 1/8 ) • Internal Temperature Compensated Self Refresh • Deep Power Down Mode • All inputs except data & DM are sampled at the positive going edge of the system clock(CK). • Data I/O transactions on both edges of data strobe, DM for masking. • Edge aligned data output, center aligned data input. • No DLL; CK to DQS is not synchronized. • DM0 - DM3 for write masking only. • Auto refresh duty cycle - 7.8us for -25 to 85 °C Operating Frequency DDR266 DDR222 Speed @CL2 *1 83Mhz 66Mhz Speed @CL3 *1 133Mhz 111Mhz Note : 1. CAS Latency Address configuration Organization Bank Row Column 16M x32 BA0,BA1 A0 - A12 A0 - A8 - DM is internally loaded to match DQ and DQS identically. Ordering Information Part No. Max Freq. K4X51323PC-7(8)E/GC3 133MHz(CL=3),83MHz(CL=2) K4X51323PC-7(8)E/GCA 111MHz(CL=3),66MHz(CL=2) Interface Package LVCMOS 90FBGA Pb (Pb Free) - 7(8)E : 90FBGA Pb(Pb Free), Normal Power, Extended Temperature(-25 °C ~ 85 °C) - 7(8)G : 90FBGA Pb(Pb Free), Low Power, Extended Temperature(-25 °C ~ 85 °C) - C3/CA : 133MHz(CL=3) / 111MHz(CL=3) INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. 3 Revision 0.6 October 2005 Preliminary K4X51323PC - 7(8)E/G Mobile-DDR SDRAM FUNCTIONAL BLOCK DIAGRAM CK, CK LWE I/O Control 32 Data Input Register LDM Serial to parallel Bank Select 64 2Mx64 32 Output Buffer 2Mx64 64 2-bit prefetch Sense AMP Row Decoder Refresh Counter Row Buffer ADD Address Register CK, CK 2Mx64 X32 DQi 2Mx64 Column Decoder Col. Buffer LCBR LRAS Latency & Burst Length Strobe Gen. Programming Register Data Strobe LCKE LRAS LCBR LWE LCAS Timing Register CK, CK CKE CS RAS LDM LWCBR CAS DM Input Register WE 4 DM Revision 0.6 October 2005 Preliminary K4X51323PC - 7(8)E/G Mobile-DDR SDRAM Package Dimension and Pin Configuration < Top View*2 > < Bottom View*1 > E1 9 8 7 6 5 90Ball(6x15) FBGA 4 3 2 1 1 2 3 7 8 9 A VSS DQ31 VSSQ VDDQ DQ16 VDD B B VDDQ DQ29 DQ30 DQ17 DQ18 VSSQ C C VSSQ DQ27 DQ28 DQ19 DQ20 VDDQ D D VDDQ DQ25 DQ26 DQ21 DQ22 VSSQ E E VSSQ DQS3 DQ24 DQ23 DQS2 VDDQ F F VDD DM3 NC NC DM2 VSS G CKE CK CK WE CAS RAS H A9 A11 A12 CS BA0 BA1 J A6 A7 A8 A10 A0 A1 K A4 DM1 A5 A2 DM0 A3 VDDQ e A H D D1 G J K L M N P R L VSSQ DQS1 DQ8 DQ7 DQS0 M VDDQ DQ9 DQ10 DQ5 DQ6 VSSQ N VSSQ DQ11 DQ12 DQ3 DQ4 VDDQ P VDDQ DQ13 DQ14 DQ1 DQ2 VSSQ R VSS DQ15 VSSQ VDDQ DQ0 VDD E A A1 b z < Top View*1 > #A1 Ball Origin Indicator Ball Name Ball Function CK, CK System Differential Clock CS Chip Select CKE Clock Enable A0 ~ A12 Address BA0 ~ BA1 Bank Select Address RAS Row Address Strobe CAS Column Address Strobe WE Write Enable DM0~3 Data Input Mask DQS0~3 Data Strobe SAMSUNG Data Input/Output VDD/VSS Power Supply/Ground VDDQ/VSSQ Data Output Power/Ground [Unit::mm] Symbol Week ES K4X51323PC-XXXX DQ0 ~ 31 5 Min Typ Max 1.00 A - - A1 0.25 - - E 10.9 11.0 11.1 E1 - 6.40 - D 13.2 13.0 13.1 D1 - 11.2 - e - 0.80 - b 0.45 0.50 0.55 z - - 0.10 Revision 0.6 October 2005 Preliminary K4X51323PC - 7(8)E/G Mobile-DDR SDRAM Input/Output Function Description SYMBOL TYPE DESCRIPTION CK, CK Input Clock : CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK. Internal clock signals are derived from CK/CK. CKE Input Clock Enable : CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER-DOWN (row ACTIVE in any banks). CKE is synchronous for all functions except for disabling outputs, which is achieved asynchronously. Input buffers, excluding CK, CK and CKE , are disabled during power-down and self refresh mode which are contrived for low standby power consumption. CS Input Chip Select : CS enables(registered LOW) and disables(registered HIGH) the command decoder. All commands are masked when CS is registered HIGH. CS provides for external bank selection on systems with multiple banks. CS is considered part of the command code. RAS, CAS, WE Input Command Inputs : RAS, CAS and WE (along with CS) define the command being entered. DM0,DM1, DM2,DM3 Input Input Data Mask : DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS. DM pins include dummy loading internally, to match the DQ and DQS loading. For the x32, DM0 corresponds to the data on DQ0-DQ7 ; DM1 corresponds to the data on DQ8-DQ15, DM2 corresponds to the data on DQ16-DQ23, DM3 corresponds to the data on DQ24-DQ31 BA0, BA1 Input Bank Addres Inputs : BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRECHARGE command is being applied. A [n : 0] Input Address Inputs : Provide the row address for ACTIVE commands, and the column address and AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also provide the op-code during a MODE REGISTER SET command. BA0 and BA1 determines which mode register ( mode register or extended mode register ) is loaded during the MODE REGISTER SET command. DQ I/O Data Input/Output : Data bus DQS0,DQS1, DQS2,DQS3 I/O Data Strobe : Output with read data, input with write data. Edge-aligned with read data, centered in write data. it is used to fetch write data. For the x32, DQS0 corresponds to the data on DQ0-DQ7 ; DQS1 corresponds to the data on DQ8-DQ15,DQS2 corresponds to the data on DQ16-DQ23, DQS3 corresponds to the data on DQ24-DQ31 NC - No Connect : No internal electrical connection is present. VDDQ Supply DQ Power Supply : 1.7V to 1.95V VSSQ Supply DQ Ground. VDD Supply Power Supply : 1.7V to 1.95V VSS Supply Ground. 6 Revision 0.6 October 2005 Preliminary K4X51323PC - 7(8)E/G Mobile-DDR SDRAM Functional Description POWER APPLIED DEEP POWER DOWN CKEH POWER ON DEEP POWER DOWN PRECHARGE ALL BANKS PARTIAL SELF REFRESH SELF REFRESH REFS REFSX MRS EMRS MRS IDLE ALL BANKS PRECHARGED REFA AUTO REFRESH CKEL CKEH ACT POWER DOWN POWER DOWN CKEH ROW ACTIVE CKEL BURST STOP WRITE READ WRITEA READA WRITEA WRITE READ WRITEA READ READA READA PRE WRITEA PRE PRE PRE READA PRECHARGE PREALL Automatic Sequence Command Sequence Figure.1 State diagram 7 Revision 0.6 October 2005 Preliminary K4X51323PC - 7(8)E/G Mobile-DDR SDRAM Mode Register Definition Mode Register Set(MRS) The mode register is designed to support the various operating modes of DDR SDRAM. It includes Cas latency, addressing mode, burst length, test mode and vendor specific options to make DDR SDRAM useful for variety of applications. The default value of the mode register is not defined, therefore the mode register must be written in the power up sequence of DDR SDRAM. The mode register is written by asserting low on CS, RAS, CAS and WE(The DDR SDRAM should be in active mode with CKE already high prior to writing into the mode register). The states of address pins A0 ~ A12 and BA0, BA1 in the same cycle as CS, RAS, CAS and WE going low are written in the mode register. Two clock cycles are required to complete the write operation in the mode register. Even if the power-up sequence is finished and some read or write operation is executed afterward, the mode register contents can be changed with the same command and two clock cycles. This command must be issued only when all banks are in the idle state. If mode register is changed, extended mode register automatically is reset and come into default state. So extended mode register must be set again. The mode register is divided into various fields depending on functionality. The burst length uses A0 ~ A2, addressing mode uses A3, Cas latency(read latency from column address) uses A4 ~ A6, A7 ~ A12 is used for test mode. BA0 and BA1 must be set to low for proper MRS operation. BA1 0 BA0 A12 ~ A10/AP A9 A8 A7 0 RFU* 0 0 0 A6 A5 A4 CAS Latency A3 A2 BT A3 A1 A0 Address Bus Mode Register Burst Length Burst Type 0 Sequential 1 Interleave A6 A5 A4 CAS Latency A2 A1 A0 Burst Length 0 0 0 Reserved 0 0 0 Reserved 0 0 1 Reserved 0 0 1 2 0 1 0 2 0 1 0 4 0 1 1 3 0 1 1 8 1 0 0 Reserved 1 0 0 16 1 0 1 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 0 Reserved 1 1 1 Reserved 1 1 1 Reserved Figure.2 Mode Register Set Note : RFU(Reserved for future use) should stay "0" during MRS cycle 8 Revision 0.6 October 2005 Preliminary K4X51323PC - 7(8)E/G Mobile-DDR SDRAM Burst address ordering for burst length Burst Length 2 4 8 16 Starting Address (A3, A2, A1, A0) Sequential Mode Interleave Mode xxx0 0, 1 0, 1 xxx1 1, 0 1, 0 xx00 0, 1, 2, 3 0, 1, 2, 3 xx01 1, 2, 3, 0 1, 0, 3, 2 xx10 2, 3, 0, 1 2, 3, 0, 1 xx11 3, 0, 1, 2 3, 2, 1, 0 x000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 x001 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6 x010 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5 x011 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4 x100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 x101 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2 x110 6, 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1 x111 7, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0 0000 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,15 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,15 0001 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,15, 0 1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11,10,13,12,15,14 0010 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,15, 0, 1 2, 3, 0, 1, 6, 7, 4, 5,10,11, 8, 9, 14,15,12,13 0011 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,15, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4,11,10, 9, 8, 15,14,13,12 0100 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,15, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3,12,13,14,15, 8, 9, 10,11 0101 5, 6, 7,8, 9, 10, 11, 12, 13, 14,15, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2,13,12,15,14, 9, 8,11,10 0110 6, 7, 8, 9, 10, 11, 12, 13, 14,15, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1,14,15,12,13,10,11, 8, 9 0111 7, 8, 9, 10, 11, 12, 13, 14,15, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0, 15,14,13,12,11,10, 9, 8 1000 8, 9, 10, 11, 12, 13, 14,15, 0, 1, 2, 3, 4, 5, 6, 7 8, 9,10,11,12,13,14,15, 0, 1, 2, 3, 4, 5, 6, 7 1001 9, 10, 11, 12, 13, 14,15, 0, 1, 2, 3, 4, 5, 6, 7, 8 9, 8, 11,10,13,12,15,14,1, 0, 3, 2, 5, 4, 7, 6 1010 10, 11, 12, 13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 10,11, 8, 9, 14,15,12,13, 2, 3, 0, 1, 6, 7, 4, 5 1011 11, 12, 13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 11,10, 9, 8, 15,14,13,12, 3, 2, 1, 0, 7, 6, 5, 4 1100 12, 13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 12,13,14,15, 8, 9, 10,11, 4, 5, 6, 7, 0, 1, 2, 3 1101 13, 14, 15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11,12 13,12,15,14, 9, 8,11,10, 5, 4, 7, 6, 1, 0, 3, 2 1110 14, 15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 14,15,12,13,10,11, 8, 9, 6, 7, 4, 5, 2, 3, 0, 1 1111 15, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 15,14,13,12,11,10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0 9 Revision 0.6 October 2005 Preliminary K4X51323PC - 7(8)E/G Mobile-DDR SDRAM Extended Mode Register Set(EMRS) The extended mode register is designed to support partial array self refresh or driver strength control. EMRS cycle is not mandatory and the EMRS command needs to be issued only when either PASR or DS is used. The default state without EMRS command issued is half driver strength, and Full array refreshed. The extended mode register is written by asserting low on CS, RAS, CAS, WE and high on BA1 ,low on BA0(The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register). The state of address pins A0 ~ A12 in the same cycle as CS, RAS, CAS and WE going low is written in the extended mode register. Two clock cycles are required to complete the write operation in the extended mode register. Even if the power-up sequence is finished and some read or write operations is executed afterward, the mode register contents can be changed with the same command and two clock cycles. But this command must be issued only when all banks are in the idle state. A0 - A2 are used for partial array self refresh and A5 - A6 are used for driver strength control. "High" on BA1 and"Low" on BA0 are used for EMRS. All the other address pins except A0,A1,A2,A5,A6, BA1, BA0 must be set to low for proper EMRS operation. Refer to the table for specific codes. Extended MRS for PASR(Partial Array Self Refresh) & DS(Driver Strength Control) BA1 BA0 A12 ~ A10/AP A9 A8 A7 1 0 RFU* 0 0 0 DS A6 A5 DS A4 A3 A2 A1 RFU* A5 Driver Strength 0 0 Full 0 1 1/2 1 0 1/4 1 1 1/8 Self refresh cycle is controlled automatically by internal temperature sensor and control circuit according to the three temperature ranges ; 45 °C and 85 °C Address Bus Mode Register PASR Internal TCSR A6 A0 PASR A2 A1 A0 Refreshed Area 0 0 0 Full Array 0 0 1 1/2 of Full Array 0 1 0 1/4 of Full Array 0 1 1 Reserved 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved Figure.3 Extended Mode Register Set Note : RFU(Reserved for future use) should stay "0" during EMRS cycle 10 Revision 0.6 October 2005 Preliminary K4X51323PC - 7(8)E/G Mobile-DDR SDRAM Internal Temperature Compensated Self Refresh (TCSR) Note : 1. In order to save power consumption, Mobile DDR SDRAM includes the internal temperature sensor and control units to control the self refresh cycle automatically according to the three temperature ranges ; 45 °C and 85 °C. 2. If the EMRS for external TCSR is issued by the controller, this EMRS code for TCSR is ignored. 3. It has +/- 5 °C tolerance. Self Refresh Current (IDD6) Temperature Range -E -G Unit Full Array 1/2 Array 1/4 Array Full Array 1/2 Array 1/4 Array 45 °C*3 300 270 255 250 220 205 85 °C 600 500 450 500 400 350 uA Partial Array Self Refresh (PASR) Note : 1. In order to save power consumption, Mobile-DDR SDRAM includes PASR option. 2. Mobile-DDR SDRAM supports three kinds of PASR in self refresh mode; Full array, 1/2 Array, 1/4 Array. BA1=0 BA0=0 BA1=0 BA0=1 BA1=0 BA0=0 BA1=0 BA0=1 BA1=0 BA0=0 BA1=0 BA0=1 BA1=1 BA0=0 BA1=1 BA0=1 BA1=1 BA0=0 BA1=1 BA0=1 BA1=1 BA0=0 BA1=1 BA0=1 - Full Array - 1/2 Array - 1/4 Array Partial Self Refresh Area Figure.4 EMRS code and TCSR , PASR 11 Revision 0.6 October 2005 Preliminary K4X51323PC - 7(8)E/G Mobile-DDR SDRAM Absolute maximum ratings Parameter Symbol Value Unit Voltage on any pin relative to VSS VIN, VOUT -0.5 ~ 2.7 V Voltage on VDD supply relative to VSS VDD -0.5 ~ 2.7 V Voltage on VDDQ supply relative to VSS VDDQ -0.5 ~ 2.7 V Storage temperature TSTG -55 ~ +150 °C Power dissipation PD 1.0 W Short circuit current IOS 50 mA Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommend operation condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC Operating Conditions Recommended operating conditions(Voltage referenced to VSS=0V, Tc = -25°C to 85°C) Parameter Symbol Min Max Unit Note VDD 1.7 1.95 V 1 VDDQ 1.7 1.95 V 1 Input logic high voltage VIH(DC) 0.7 x VDDQ VDDQ+0.3 V 2 Input logic low voltage VIL(DC) -0.3 0.3 x VDDQ V 2 Output logic high voltage VOH(DC) 0.9 x VDDQ - V IOH = -0.1mA Output logic low voltage VOL(DC) - 0.1 x VDDQ V IOL = 0.1mA II -2 2 uA IOZ -5 5 uA Supply voltage(for device with a nominal VDD of 1.8V) I/O Supply voltage Input leakage current Output leakage current Note : 1. Under all conditions, VDDQ must be less than or equal to VDD. 2. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation. 12 Revision 0.6 October 2005 Preliminary K4X51323PC - 7(8)E/G Mobile-DDR SDRAM DC CHARACTERISTICS Recommended operating conditions (Voltage referenced to VSS = 0V, Tc = -25 to 85°C) Parameter Operating Current (One Bank Active) Symbol IDD0 IDD2P Precharge Standby Current in power-down mode IDD2N Precharge Standby Current in non power-down mode Unit 80 70 mA all banks idle, CKE is LOW; CS is HIGH, tCK = t CKmin ; address and control inputs are SWITCHING; data bus inputs are STABLE 0.3 all banks idle, CKE is LOW; CS is HIGH, CK = LOW, CK = HIGH; address and control inputs are SWITCHING; data bus inputs are STABLE 0.3 all banks idle, CKE is HIGH; CS is HIGH, tCK = t CKmin ;address and control inputs are SWITCHING; data bus inputs are STABLE 12 10 all banks idle, CKE is HIGH; CS is HIGH, CK = LOW, CK = HIGH; address and control inputs are SWITCHING; data bus inputs are STABLE 8 7 IDD3P one bank active, CKE is LOW; CS is HIGH, tCK = tCKmin ;address and control inputs are SWITCHING; data bus inputs are STABLE 6 IDD3PS one bank active, CKE is LOW; CS is HIGH, CK = LOW, CK = HIGH;address and control inputs are SWITCHING; data bus inputs are STABLE 3 Active Standby Current in power-down mode mA one bank active, CKE is HIGH; CS is HIGH, tCK = tCKmin ;address and control inputs are SWITCHING; data bus inputs are STABLE 25 20 one bank active, CKE is HIGH; CS is HIGH, CK = LOW, CK = HIGH; address and control inputs are SWITCHING; data bus inputs are STABLE 20 15 IDD4R one bank active; BL = 4; CL = 3; tCK = tCKmin ; continuous read bursts; I OUT = 0 mA address inputs are SWITCHING; 50% data change each burst transfer 125 105 IDD4W one bank active; BL = 4; tCK = tCKmin ; continuous write bursts;address inputs are SWITCHING; 50% data change each burst transfer 100 90 tRC = tRFCmin ; tCK = tCKmin ; burst refresh; CKE is HIGH;address and control inputs are SWITCHING; data bus inputs are STABLE 150 135 mA 45*1 85 °C Full 300 600 1/2 270 500 1/4 255 450 Full 250 500 1/2 220 400 1/4 205 350 IDD3N mA IDD3NS Operating Current (Burst Mode) mA IDD5 TCSR CKE is LOW; tCK = tCKmin ; Extended Mode Register set to all 0’s; address and control inputs are STABLE; data bus inputs are STABLE -E Self Refresh Current DDR222 mA IDD2NS Refresh Current tRC = tRCmin ; tCK = tCKmin ; CKE is HIGH; CS is HIGH between valid commands; address inputs are SWITCHING; data bus inputs are STABLE DDR266 mA IDD2PS Active Standby Current in non power-down mode (One Bank Active) Test Condition IDD6 uA -G Deep Power Down Current 2 IDD8* Address and control inputs are STABLE; data bus inputs are STABLE 10 uA Note : 1. It has +/- 5°C tolerance. 2. DPD(Deep Power Down) function is an optional feature, and it will be enabled upon request. Please contact Samsung for more information. 3. IDD specifications are tested after the device is properly intialized. 4. Input slew rate is 1V/ns. 5. Definitions for IDD: LOW is defined as V IN ≤ 0.1 * VDDQ ; HIGH is defined as V IN ≥ 0.9 * VDDQ ; STABLE is defined as inputs stable at a HIGH or LOW level ; SWITCHING is defined as: - address and command: inputs changing between HIGH and LOW once per two clock cycles ; - data bus inputs: DQ changing between HIGH and LOW once per clock cycle; DM and DQS are STABLE. 13 Revision 0.6 October 2005 Preliminary K4X51323PC - 7(8)E/G Mobile-DDR SDRAM AC Operating Conditions & Timming Specification Parameter/Condition Max Unit Note 0.8 x VDDQ VDDQ+0.3 V 1 -0.3 0.2 x VDDQ V 1 0.4 x VDDQ 0.6 x VDDQ V 2 Symbol Min Input High (Logic 1) Voltage, all inputs VIH(AC) Input Low (Logic 0) Voltage, all inputs VIL(AC) Input Crossing Point Voltage, CK and CK inputs VIX(AC) Note : 1. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation. 2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same. 14 Revision 0.6 October 2005 Preliminary K4X51323PC - 7(8)E/G Mobile-DDR SDRAM AC Timming Parameters & Specifications Parameter Clock cycle time DDR266 Symbol CL=2 CL=3 Row cycle time Min tCK tRC DDR222 Max Min 12.0 15.0 7.5 9.0 67.5 81 ns tRAS 45 tRCD 22.5 27 ns tRP 22.5 27 ns Row active to Row active delay tRRD 15 15 ns Write recovery time tWR 15 15 ns Last data in to Active delay tDAL 2tCK+tRP 2tCK+tRP - Last data in to Read command tCDLR 1 1 tCK Col. address to Col. address delay tCCD 1 tCH 0.45 0.55 0.45 0.55 tCK tCL 0.45 0.55 0.45 0.55 tCK 2 8 2.5 8 2 6 2.5 6 2 8 2.5 8 2 6 2.5 6 Clock low level width DQ Output data access time from CK/ CK CL=2 DQS Output data access time from CK/CK CL=2 CL=3 CL=3 Data strobe edge to ouput data edge Read Preamble tAC tDQSCK tDQSQ CL=2 CL=3 tRPRE 70,000 1 0.6 Note ns RAS to CAS delay Clock high level width 54 Unit Row active time Row precharge time 70,000 Max ns 2 tCK 0.7 0.5 1.1 0.5 1.1 0.9 1.1 0.9 1.1 ns 3 ns ns tCK Read Postamble tRPST 0.4 0.6 0.4 0.6 tCK CK to valid DQS-in tDQSS 0.75 1.25 0.75 1.25 tCK DQS-in setup time tWPRES 0 0 ns DQS-in hold time tWPREH 0.25 0.25 tCK DQS-in high level width tDQSH 0.4 0.6 0.4 0.6 tCK DQS-in low level width 0.6 0.4 0.6 tCK 4 tDQSL 0.4 DQS falling edge to CK setup time tDSS 0.2 0.2 DQS falling edge hold time from CK tDSH 0.2 0.2 DQS-in cycle time tDSC 0.9 Address and Control Input setup time tIS 1.3 1.5 ns 1 Address and Control Input hold time tIH 1.3 1.5 ns 1 Address & Control input pulse width tIPW 2.6 3.0 DQ & DM setup time to DQS tDS 0.9 1.2 ns 5,6 DQ & DM hold time to DQS tDH 0.9 1.2 ns 5,6 DQ & DM input pulse width ns 1.1 0.9 tDIPW 1.8 2.4 DQ & DQS low-impedence time from CK/CK tLZ 1.0 1.0 DQ & DQS high-impedence time from CK/CK tHZ 6.0 DQS write postamble time tWPST 0.4 DQS write preamble time tWPRE 0.25 15 0.6 0.4 0.25 tCK tCK 1.1 tCK 1 ns 7.0 ns 0.6 tCK tCK Revision 0.6 October 2005 Preliminary K4X51323PC - 7(8)E/G Parameter Mobile-DDR SDRAM DDR222 DDR266 Symbol Min Max Min Refresh interval time tREF Mode register set cycle time tMRD 2 64 2 Power down exit time Unit 64 ms tCK tPDEX 1*tCK +tIS 1*tCK +tIS ns CKE min. pulse width(high and low pulse width) tCKE 2 2 tCK Auto refresh cycle time tRFC 80 90 ns Exit self refresh to active command tXSR 120 120 ns Data hold from DQS to earliest DQ edge tQH tHPmin tQHS tHPmin tQHS ns Data hold skew factor Clock half period tQHS tHP 0.75 tCLmin or tCHmin 16 1.0 tCLmin or tCHmin Note Max 7 ns ns Revision 0.6 October 2005 Preliminary K4X51323PC - 7(8)E/G Mobile-DDR SDRAM Note : 1. Input Setup/Hold Slew Rate Derating Input Setup/Hold Slew Rate ∆tIS ∆tIH (V/ns) (ps) (ps) 1.0 0 0 0.8 +50 +50 0.6 +100 +100 This derating table is used to increase tIS/tIH in the case where the input slew rate is below 1.0V/ns. 2. Minimum 3CLK of tDAL(= tWR + tRP) is required because it need minimum 2CLK for tWR and minimum 1CLK for tRP. 3. tAC(min) value is measured at the high Vdd(1.95V) and cold temperature(-25°C). tAC(max) value is measured at the low Vdd(1.7V) and hot temperature(85°C). tAC is measured in the device with half driver strength and under the AC output load condition (Fig.7 in next Page). 4. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress, DQS could be High at this time, depending on tDQSS. 5. I/O Setup/Hold Slew Rate Derating I/O Setup/Hold Slew Rate ∆tDS ∆tDH (V/ns) (ps) (ps) 1.0 0 0 0.8 +75 +75 0.6 +150 +150 This derating table is used to increase tDS/tDH in the case where the I/O slew rate is below 1.0V/ns. 6. I/O Delta Rise/Fall Rate(1/slew-rate) Derating Delta Rise/Fall Rate ∆tDS ∆tDH (ns/V) (ps) (ps) 0 0 0 ±0.25 +50 +50 ±0.5 +100 +100 This derating table is used to increase tDS/tDH in the case where the DQ and DQS slew rates differ. The Delta Rise/Fall Rate is calculated as 1/SlewRate1-1/SlewRate2. For example, if slew rate 1 = 1.0V/ns and slew rate 2 =0.8V/ns, then the Delta Rise/Fall Rate =-0.25ns/V. 7. Maximum burst refresh cycle : 8 17 Revision 0.6 October 2005 Preliminary K4X51323PC - 7(8)E/G Mobile-DDR SDRAM AC Operating Test Conditions(VDD = 1.7V to 1.95V, Tc = -25 to 85°C) Parameter AC input levels (Vih/Vil) Value Unit 0.8 x VDDQ / 0.2 x VDDQ V Input timing measurement reference level 0.5 x VDDQ V 1.0 V/ns Output timing measurement reference level 0.5 x VDDQ V Output load condition See Figure.7 Input signal minimum slew rate 1.8V Vtt=0.5 x VDDQ 13.9KΩ VOH (DC) = 0.9 x VDDQ , IOH = -0.1mA VOL (DC) = 0.1 x VDDQ , IOL = 0.1mA Output 20pF 10.6KΩ 50Ω Output Z0=50Ω 20pF Figure.6 DC Output Load Circuit Figure.7 AC Output Load Circuit Input/Output Capacitance(VDD=1.8, VDDQ=1.8V, TC = 25°C, f=1MHz) Symbol Min Max Unit Input capacitance (A0 ~ A12, BA0 ~ BA1, CKE, CS, RAS,CAS, WE) Parameter CIN1 1.5 3.0 pF Input capacitance( CK, CK ) CIN2 1.5 3.5 pF Data & DQS input/output capacitance COUT 2.0 4.5 pF Input capacitance(DM) CIN3 2.0 4.5 pF 18 Revision 0.6 October 2005 Preliminary K4X51323PC - 7(8)E/G Mobile-DDR SDRAM AC Overshoot/Undershoot Specification for Address & Control Pins Parameter Specification Maximum peak Amplitude allowed for overshoot area 0.9V Maximum peak Amplitude allowed for undershoot area 0.9V Maximum overshoot area above VDD 3V-ns Maximum undershoot area below VSS 3V-ns Maximum Amplitude Overshoot Area Volts (V) VDD VSS Undershoot Area Maximum Amplitude Time (ns) Figure.8 AC Overshoot and Undershoot Definition for Address and Control Pins AC Overshoot/Undershoot Specification for CLK, DQ, DQS and DM Pins Parameter Specification Maximum peak Amplitude allowed for overshoot area 0.9V Maximum peak Amplitude allowed for undershoot area 0.9V Maximum overshoot area above VDDQ 3V-ns Maximum undershoot area below VSSQ 3V-ns Maximum Amplitude Overshoot Area Volts (V) VDDQ VSSQ Undershoot Area Maximum Amplitude Time (ns) Figure.9 AC Overshoot and Undershoot Definition for CLK, DQ, DQS and DM Pins 19 Revision 0.6 October 2005 Preliminary K4X51323PC - 7(8)E/G Mobile-DDR SDRAM Command Truth Table(V=Valid, X=Don′t Care, H=Logic High, L=Logic Low) COMMAND Register CKEn-1 CKEn Mode Register Set H Auto Refresh X Self Refresh RAS CAS WE BA0,1 A10/AP L L L L OP CODE L L L H X A12,A11, Note A9 ~ A0 1, 2 H H Entry Refresh CS 3 L 3 L Exit H H H 3 L H X H X X X Bank Active & Row Addr. H X L L H H V Read & Auto Precharge Disable Column Address Auto Precharge Enable H X L H L H V Write & Auto Precharge Disable Column Address Auto Precharge Enable H X L H L L V 3 Row Address L Column Address (A0~A8) Column Address (A0~A8) H L Entry H L L H H L Exit L H H X X X H X L H H L H Deep Power Down 4 4 4 4, 6 X Burst Stop Bank Selection Precharge H X L L H H Entry L H X H H X X X L V V V X 7 X 5 L Active Power Down Exit L L All Banks Entry X V H X X X H X X X L H H H H X X X L V V V X L Precharge Power Down X Exit L DM H No operation (NOP) : Not defined H H X X H X X X L H H H X 8 9 X 9 Note : 1. OP Code : Operand Code. A0 ~ A12 & BA0 ~ BA1 : Program keys. (@EMRS/MRS) 2.EMRS/ MRS can be issued only at all banks precharge state. A new command can be issued 2 clock cycles after EMRS or MRS. 3. Auto refresh functions are same as the CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. 5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected. 6. During burst write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 7. Burst stop command is valid at every burst length. 8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0). 9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM. 20 Revision 0.6 October 2005 Preliminary K4X51323PC - 7(8)E/G Mobile-DDR SDRAM Functional Truth Table Current State CS RAS CAS WE PRECHARGE STANDBY L H H L X Burst Stop ILLEGAL*2 L H L X BA, CA, A10 READ/WRITE ILLEGAL*2 L L H H BA, RA Active Bank Active, Latch RA L L H L BA, A10 PRE/PREA ILLEGAL*4 L L L H X Refresh AUTO-Refresh*5 L L L L Op-Code, Mode-Add MRS Mode Register Set*5 L H H L X Burst Stop NOP ACTIVE STANDBY READ Address Command Action L H L H BA, CA, A10 READ/READA Begin Read, Latch CA, Determine Auto-Precharge L H L L BA, CA, A10 WRITE/WRITEA Begin Write, Latch CA, Determine Auto-Precharge L L H H BA, RA Active Bank Active/ILLEGAL*2 L L H L BA, A10 PRE/PREA Precharge/Precharge All L L L H X Refresh ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL L H H L X Burst Stop Terminate Burst L H L H BA, CA, A10 READ/READA Terminate Burst, Latch CA, Begin New Read, Determine Auto-Precharge*3 L H L L BA, CA, A10 WRITE/WRITEA ILLEGAL L L H H BA, RA Active Bank Active/ILLEGAL*2 L L H L BA, A10 PRE/PREA Terminate Burst, Precharge L L L H X Refresh ILLEGAL L L L L MRS ILLEGAL Op-Code, Mode-Add 21 Revision 0.6 October 2005 Preliminary K4X51323PC - 7(8)E/G Mobile-DDR SDRAM Functional truth table Current State CS RAS CAS WE Address Command Action WRITE L H H L X Burst Stop L H L H BA, CA, A10 READ/READA L H L L BA, CA, A10 Terminate Burst, Latch CA, WRITE/WRITEA Begin new Write, Determine Auto-Precharge*3 L L H H BA, RA Active Bank Active/ILLEGAL*2 L L H L BA, A10 PRE/PREA Terminate Burst With DM=High, Precharge L L L H X Refresh ILLEGAL L L L L Op-Code, Mode-Add MRS L H H L X Burst Stop ILLEGAL L H L H BA, CA, A10 READ/READA *6 L H L L BA, CA, A10 WRITE/WRITEA ILLEGAL L L H H BA, RA Active *6 L L H L BA, A10 PRE/PREA *6 L L L H X Refresh ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL L H H L X Burst Stop ILLEGAL L H L H BA, CA, A10 READ/READA *7 L H L L BA, CA, A10 WRITE/WRITEA *7 L L H H BA, RA Active *7 L L H L BA, A10 PRE/PREA *7 L L L H X Refresh ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL Terminate Burst With DM=High, Latch CA, READ with AUTO PRECHARGE*6 (READA) WRITE with AUTO RECHARGE*7 (WRITEA) 22 Begin Read, Determine Auto-Precharge*3 ILLEGAL ILLEGAL Revision 0.6 October 2005 Preliminary K4X51323PC - 7(8)E/G Mobile-DDR SDRAM Functional truth table Current State CS RAS CAS WE Address Command Action PRECHARGING (DURING tRP) L H H L X Burst Stop ILLEGAL*2 L H L X BA, CA, A10 READ/WRITE ILLEGAL*2 L L H H BA, RA Active ILLEGAL*2 L L H L BA, A10 PRE/PREA NOP*4(Idle after tRP) L L L H X Refresh ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL ROW ACTIVATING (FROM ROW L H H L X Burst Stop ILLEGAL*2 L H L X BA, CA, A10 READ/WRITE ILLEGAL*2 ACTIVE TO tRCD) L L H H BA, RA Active ILLEGAL*2 L L H L BA, A10 PRE/PREA ILLEGAL*2 L L L H X Refresh ILLEGAL WRITE RECOVERING (DURING tWR OR tCDLR) L L L L Op-Code, Mode-Add MRS ILLEGAL L H H L X Burst Stop ILLEGAL*2 L H L H BA, CA, A10 READ ILLEGAL*2 L H L L BA, CA, A10 WRITE WRITE L L H H BA, RA Active ILLEGAL*2 L L H L BA, A10 PRE/PREA ILLEGAL*2 L L L H X Refresh ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL 23 Revision 0.6 October 2005 Preliminary K4X51323PC - 7(8)E/G Mobile-DDR SDRAM Functional truth table Current State CS RAS CAS WE REFRESHING L H H L L H L L L H L L H L BA, A10 PRE/PREA ILLEGAL L L L H X Refresh ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL L H H L X Burst Stop ILLEGAL L H L X BA, CA, A10 READ/WRITE ILLEGAL L L H H BA, RA Active ILLEGAL MODE REGISTER SETTING Address Command Action X Burst Stop ILLEGAL X BA, CA, A10 READ/WRITE ILLEGAL H BA, RA Active ILLEGAL L L H L BA, A10 PRE/PREA ILLEGAL L L L H X Refresh ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL 24 Revision 0.6 October 2005 Preliminary K4X51323PC - 7(8)E/G Mobile-DDR SDRAM Functional truth table Current State CKE n-1 CKE n CS RAS CAS WE Add SELF- L H H X X X X Exit Self-Refresh REFRESHING*8 L H L H H H X Exit Self-Refresh L H L H H L X ILLEGAL L H L H L X X ILLEGAL L H L L X X X ILLEGAL L L X X X X X NOPeration(Maintain Self-Refresh) POWER DOWN L H X X X X X Exit Power Down(Idle after tPDEX) L L X X X X X NOPeration(Maintain Power Down) DEEP POWER DOWN L H H X X X X Exit Deep Power Down*10 L L X X X X X NOPeration(Maintain Deep Power Down) ALL BANKS IDLE*9 H H X X X X X Refer to Function True Table H L L L L H X Enter Self-Refresh H L H X X X X Enter Power Down H L L H H H X Enter Power Down H L L H H L X Enter Deep Power Down H L L H H L X ILLEGAL H L L H L X X ILLEGAL H L L L X X X ILLEGAL L X X X X X X Refer to Current State=Power Down H H X X X X X Refer to Function Truth Table ANY STATE other than listed above Action ABBREVIATIONS : H=High Level, L=Low level, X=Don′t Care Note : 1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle. 2. ILLEGAL to bank in specified state ; function may be legal in the bank indicated by BA, depending on the state of that bank.(ILLEGAL = Device operation and/or data integrity are not guaranteed.) 3. Must satisfy bus contention, bus turn around and write recovery requirements. 4. NOP to bank precharging or in idle sate. May precharge bank indicated by BA. 5. ILLEGAL if any bank is not idle. 6. Refer to "Read with Auto Precharge Timing Diagram" for detailed information. 7. Refer to "Write with Auto Precharge Timing Diagram" for detailed information. 8. CKE Low to High transition will re-enable CK, CK and other inputs asynchronously. A minimum setup time must be satisfied before issuing any command other than EXIT. 9. Power-Down, Self-Refresh and Deep Power Down Mode can be entered only from All Bank Idle state. 10. The Deep Power Down Mode is exited by asserting CKE high and full initialization is required after exiting Deep Power Down Mode. 25 Revision 0.6 October 2005