CMOS SRAM K6T4016C3C Family Document Title 256Kx16 bit Low Power CMOS Static RAM Revision History Revision No. History Draft Data Remark 0.0 Initial draft December 17, 1998 Preliminary 1.0 Finalize April 17, 1999 Finalize The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices. 1 Revision 1.0 April 1999 CMOS SRAM K6T4016C3C Family 256Kx16 bit Low Power CMOS Static RAM FEATURES GENERAL DESCRIPTION • • • • • • The K6T4016C3C families are fabricated by SAMSUNG′s advanced CMOS process technology. The families support various operating temperature ranges and small package types for user flexibility of system design. The families also support low data retention voltage for battery back-up operation with low data retention current. Process Technology: TFT Organization: 256Kx16 Power Supply Voltage: 4.5~5.5V Low Data Retention Voltage: 2V(Min) Three state output and TTL Compatible Package Type: 44-TSOP2-400F/R PRODUCT FAMILY Power Dissipation Product Family Operating Temperature K6T4016C3C-B Commercial(0~70°C) K6T4016C3C-F Industrial(-40~85°C) Vcc Range Speed(ns) 4.5~5.5V 551)/70 Standby (ISB1, Max) Operating (ICC2, Max) PKG Type 90mA 44-TSOP2-400F/R 20µA 50µA 1. The parameter is measured with 50pF test load. FUNCTIONAL BLOCK DIAGRAM PIN DESCRIPTION A4 A3 A2 A1 A0 CS I/OI I/O2 I/O3 I/O4 Vcc Vss I/O5 I/O6 I/O7 I/O8 WE A17 A16 A15 A14 A13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44-TSOP2 Forward 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE UB LB I/O16 I/O15 I/O14 I/O13 Vss Vcc I/O12 I/O11 I/O10 I/O9 NC A8 A9 A10 A11 A12 A5 A6 A7 OE UB LB I/O16 I/O15 I/O14 I/O13 Vss Vcc I/O12 I/O11 I/O10 I/O9 NC A8 A9 A10 A11 A12 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 44-TSOP2 Reverse 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 A4 A3 A2 A1 A0 CS I/OI I/O2 I/O3 I/O4 Vcc Vss I/O5 I/O6 I/O7 I/O8 WE A17 A16 A15 A14 A13 Clk gen. A13 Function Name A0 A1 A15 A16 CS Chip Select Input Vcc Power Output Enable Input Vss Ground WE Write Enable Input UB Upper Byte(I/O9~16) Address Inputs LB Lower Byte (I/O1~8 ) Data Inputs/Outputs NC No Connection A0 ~A17 I/O1 ~I/O16 Row select Memory array 1024 rows 256×16 columns A17 A2 A3 A4 I/O1~I/O8 Data cont I/O Circuit Column select Data cont Data cont Function OE Vcc Vss A14 I/O9~I/O16 Name Precharge circuit. A8 A9 A10 A5 A6 A7 A4 A12 WE OE UB Control logic LB CS SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. 2 Revision 1.0 April 1999 CMOS SRAM K6T4016C3C Family PRODUCT LIST Commercial Temperature Product(0~70°C) Part Name Industrial Temperature Products(-40~85°C) Function Part Name 44-TSOP2-F, 55ns, LL-pwr 44-TSOP2-F, 70ns, LL-pwr 44-TSOP2-R, 55ns, LL-pwr 44-TSOP2-R, 70ns, LL-pwr K6T4016C3C-TB55 K6T4016C3C-TB70 K6T4016C3C-RB55 K6T4016C3C-RB70 K6T4016C3C-TF55 K6T4016C3C-TF70 K6T4016C3C-RF55 K6T4016C3C-RF70 Function 44-TSOP2-F, 55ns, LL-pwr 44-TSOP2-F, 70ns, LL-pwr 44-TSOP2-R, 55ns, LL-pwr 44-TSOP2-R, 70ns, LL-pwr FUNCTIONAL DESCRIPTION CS OE WE LB UB 1) 1) I/O1~8 I/O9~16 Mode Power High-Z High-Z Deselected Standby H X X L H H X X High-Z High-Z Output Disabled Active L X1) X1) H H High-Z High-Z Output Disabled Active L L H L H Dout High-Z Lower Byte Read Active L L H H L High-Z Dout Upper Byte Read Active L L H L L Dout Dout Word Read Active L X1) L L H Din High-Z Lower Byte Write Active L 1) X L H L High-Z Din Upper Byte Write Active L X1) L L L Din Din Word Write Active 1) 1) X 1) X 1) 1. X means don′t care. (Must be in low or high state) ABSOLUTE MAXIMUM RATINGS1) Item Voltage on any pin relative to Vss Voltage on Vcc supply relative to Vss Power Dissipation Storage temperature Operating Temperature Symbol Ratings Unit Remark VIN,VOUT -0.5 to 7.0 V - VCC -0.5 to7.0 V - PD 1.0 W - TSTG -65 to 150 °C - 0 to 70 °C K6T4016C3C-B -40 to 85 °C K6T4016C3C-F TA 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 3 Revision 1.0 April 1999 CMOS SRAM K6T4016C3C Family RECOMMENDED DC OPERATING CONDITIONS1) Symbol Min Typ Max Unit Supply voltage Item Vcc 4.5 5.0 5.5 V Ground Vss 0 0 0 Input high voltage VIH 2.2 - Vcc+0.5 Input low voltage VIL -0.5 3) - 0.8 V V 2) V Note: 1. Commercial Product: TA=0 to 70°C, otherwise specified Industrial Product: TA=-40 to 85°C, otherwise specified 2. Overshoot: VCC+3.0V in case of pulse width ≤ 30ns 3. Undershoot: -3.0V in case of pulse width ≤ 30ns 4. Overshoot and undershoot are sampled, not 100% tested. CAPACITANCE1) (f=1MHz, TA=25°C) Item Symbol Test Condition Min Max Unit Input capacitance CIN VIN=0V - 8 pF Input/Output capacitance CIO VIO=0V - 10 pF 1. Capacitance is sampled, not 100% tested DC AND OPERATING CHARACTERISTICS Item Input leakage current Symbol Test Conditions Min Typ Max Unit 1 µA ILI VIN=Vss to Vcc -1 - Output leakage current ILO CS=VIH or OE=VIH or WE=VIL, VIO=Vss to Vcc -1 - 1 µA Operating power supply ICC IIO=0mA, CS=VIL, VIN=VIL or VIH, Read - - 10 mA ICC1 Cycle time=1µs, 100% duty, IIO=0mA, CS≤0.2V, VIN≤0.2V or VIN≥Vcc-0.2V - - 15 mA ICC2 Cycle time=Min, 100% duty, IIO=0mA, CS=VIL, VIN=VIH or VIL - - 90 mA Output low voltage VOL IOL=2.1mA - - 0.4 V Output high voltage VOH IOH=-1.0mA 2.4 - - V Standby Current (TTL) ISB CS=VIH, Other inputs=VIL or VIH - - 3 mA Standby Current(CMOS) ISB1 CS≥Vcc-0.2V, Other inputs=0~Vcc - - 201) µA Average operating current 1. Industrial Product = 50µA 4 Revision 1.0 April 1999 CMOS SRAM K6T4016C3C Family AC OPERATING CONDITIONS TEST CONDITIONS (Test Load and Test Input/Output Reference) Input pulse level: 0.8 to 2.4V Input rising and falling time: 5ns Input and output reference voltage: 1.5V Output load (See right): CL=100pF+1TTL 50pF+1TTL 1) CL1) 1. Including scope and jig capacitance 1. for 55ns product AC CHARACTERISTICS( Vcc=4.5~5.5V, Commercial product : TA=0 to 70°C, Industrial product : TA=-40 to 85°C) Speed Bins Parameter List Symbol 55ns Min Min Max tRC 55 - 70 - ns Address access time tAA - 55 - 70 ns Chip select to output tCO - 55 - 70 ns Output enable to valid output tOE - 25 - 35 ns tLZ 10 - 10 - ns Output enable to low-Z output tOLZ 5 - 5 - ns LB, UB enable to low-Z output tBLZ 5 - 5 - ns Chip disable to high-Z output Write Max Read cycle time Chip select to low-Z output Read Units 70ns tHZ 0 20 0 25 ns OE disable to high-Z output tOHZ 0 20 0 25 ns Output hold from address change tOH 10 - 10 - ns LB, UB valid to data output tBA - 25 - 35 ns UB, LB disable to high-Z output tBHZ 0 20 0 25 ns Write cycle time tWC 55 - 70 - ns Chip select to end of write tCW 45 - 60 - ns Address set-up time tAS 0 - 0 - ns Address valid to end of write tAW 45 - 60 - ns Write pulse width tWP 45 - 55 - ns Write recovery time tWR 0 - 0 - ns Write to output high-Z tWHZ 0 20 0 25 ns Data to write time overlap tDW 25 - 30 - ns Data hold from write time tDH 0 - 0 - ns End write to output low-Z tOW 5 - 5 - ns LB, UB valid to end of write tBW 45 - 60 - ns DATA RETENTION CHARACTERISTICS Item Symbol Test Condition Vcc for data retention VDR CS≥Vcc-0.2V Vcc=3.0V Data retention current IDR Data retention set-up time tSDR Recovery time tRDR See data retention waveform Min Typ Max Unit 2.0 - 5.5 V 1) - - 15 0 - - 5 - - µA ms 1. Industrial Product: 20µA 5 Revision 1.0 April 1999 CMOS SRAM K6T4016C3C Family TIMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL , WE=VIH, UB or/and LB=VIL ) tRC Address tAA tOH Data Out Data Valid Previous Data Valid TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH) tRC Address tOH tAA tCO CS tHZ tBA UB, LB tBHZ tOE OE tOLZ tBLZ Data out High-Z tOHZ tLZ Data Valid NOTES (READ CYCLE) 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. 6 Revision 1.0 April 1999 CMOS SRAM K6T4016C3C Family TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled) tWC Address tWR(4) tCW(2) CS tAW tBW UB, LB tWP(1) WE tAS(3) tDW Data in High-Z tDH tWHZ Data out High-Z Data Valid tOW Data Undefined TIMING WAVEFORM OF WRITE CYCLE(2) (CS Controlled) tWC Address tAS(3) tCW(2) tWR(4) CS tAW tBW UB, LB tWP(1) WE tDW Data Valid Data in Data out tDH High-Z High-Z 7 Revision 1.0 April 1999 CMOS SRAM K6T4016C3C Family TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB Controlled) tWC Address tCW(2) tWR(4) CS tAW tBW UB, LB tAS(3) tWP(1) WE tDW Data Valid Data in Data out tDH High-Z High-Z NOTES (WRITE CYCLE) 1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition when CS goes high and WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the CS going low to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. t WR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high. DATA RETENTION WAVE FORM CS controlled VCC tSDR Data Retention Mode tRDR 4.5V 2.2V VDR CS≥VCC - 0.2V CS GND 8 Revision 1.0 April 1999 CMOS SRAM K6T4016C3C Family Units: millimeter(inch) PACKAGE DIMENSIONS 44 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400F) 0~8° 0.25 ( ) 0.010 #44 #23 10.16 0.400 0.45 ~0.75 0.018 ~ 0.030 11.76±0.20 0.463±0.008 ( 0.50 ) 0.020 #1 #22 1.00±0.10 0.039±0.004 1.20 MAX. 0.047 ( 0.805 ) 0.032 0.35±0.10 0.014±0.004 0.80 0.0315 0 0.10 0.004 MAX 0.05 MIN. 0.002 18.81 MAX. 0.741 18.41±0.10 0.725±0.004 0 + 0.1 5 - 0.0 04 + 0.0 02 .006 - 0.0 0.15 44 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400R) 0~8° ( #1 0.25 ) 0.010 #22 10.16 0.400 0.45 ~0.75 0.018 ~ 0.030 11.76±0.20 0.463±0.008 ( 0.50 ) 0.020 #44 #23 1.00±0.10 0.039±0.004 1.20 MAX. 0.047 ( 0.805 ) 0.032 0.35±0.10 0.014±0.004 0.05 MIN. 0.002 18.81 MAX. 0.741 18.41±0.10 0.725±0.004 0.80 0.0315 9 0 + 0.1 5 - 0.0 04 .0 0 + 02 .006 - 0.0 0.15 0 0.10 MAX 0.004 Revision 1.0 April 1999