K7M163625M K7M161825M 512Kx36 & 1Mx18 Flow-Through NtRAM TM Document Title 512Kx36 & 1Mx18-Bit Flow Through NtRAMTM Revision History Rev. No. History Draft Date Remark 0.0 1. Initial document. March. 25. 1999 Preliminary 0.1 1. Update ICC & ISB values. May. 27. 1999 Preliminary 0.2 1. Change tOE from 3.5ns to 4.0ns at -8 . 2. Change tOE from 3.5ns to 4.0ns at -9 . 3. Change tOE from 3.5ns to 4.0ns at -10 . June. 22. 1999 Preliminary Sep. 04. 1999 Preliminary 0.3 1. Change ISB value from 60mA to 80mA at -8. 2. Change ISB value from 50mA to 70mA at -9 . 3. Change ISB value from 40mA to 60mA at -10 . 0.4 1. Changed tCYC from 12ns to 10ns at -9 . 2. Changed DC condition at Icc and parameters Icc ; from 300mA to 320mA at -8, from 260mA to 300mA at -9, from 240mA to 280mA at -10 3. Change pin allocation at 119BGA . - A4 ; from NC to A . - B2 ; from A to CS2 - B4 ; from CKE to ADV - B6 ; from A to CS2 - G4 ; from ADV to A - H4 ; from NC to WE - M4 ; from WE toCKE Nov. 19. 1999 Preliminary 1.0 1. Final Spec Release. Dec. 08. 1999 Final 2.0 Add access time 7.5ns bin. Nov. 23. 2000 Final 3.0 1. Remove -10 bin ( tCD=10ns) Feb. 23. 2001 Final The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to c hange the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters. -1- February 2001 Rev 3.0 K7M163625M K7M161825M 512Kx36 & 1Mx18 Flow-Through NtRAM TM 512Kx36 & 1Mx18-Bit Flow Through NtRAMTM FEATURES GENERAL DESCRIPTION • 3.3V+0.165V/-0.165V Power Supply. • I/O Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O or 2.5V+0.4V/-0.125V for 2.5V I/O • Byte Writable Function. • Enable clock and suspend operation. • Single READ/WRITE control pin. • Self-Timed Write Cycle. • Three Chip Enable for simple depth expansion with no data contention . • A interleaved burst or a linear burst mode. • Asynchronous output enable control. • Power Down mode. • TTL-Level Three-State Outputs. • 100-TQFP-1420A /119BGA(7x17 Ball Grid Array Package). The K7M163625M and K7M161825M are 18,874,368-bits Synchronous Static SRAMs. The N tRAM TM , or No Turnaround Random Access Memory utilizes all bandwidth in any combination of operating cycles. Address, data inputs, and all control signals except output enable and linear burst order are synchronized to input clock. Burst order control must be tied "High or Low". Asynchronous inputs include the sleep mode enable(ZZ). Output Enable controls the outputs at any given time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex off-chip write pulse generation and provides increased timing flexibility for incoming signals. For read cycles, Flow-Through SRAM allows output data to simply flow freely from the memory array. The K7M163625M and K7M161825M are implemented with FAST ACCESS TIMES Parameter Symbol -75 -85 -90 Unit Cycle Time tCYC 8.5 10 10 ns Clock Access Time t CD 7.5 8.5 9.0 ns Output Enable Access Time t OE 4.0 4.0 4.0 ns SAMSUNG ′s high performance CMOS technology and is available in 100pin TQFP and 119BGA packages. Multiple power and ground pins minimize ground bounce. LOGIC BLOCK DIAGRAM LBO A [0:18]or A [0:19] CKE ADDRESS REGISTER A2 ~A18 or A2 ~A19 CONTROL LOGIC CLK A 0~A1 ADV WE BWx (x=a,b,c,d or a,b) A′0~A′ 1 512Kx36 , 1Mx18 MEMORY ARRAY WRITE ADDRESS REGISTER K K CONTROL REGISTER CS1 CS2 CS2 BURST ADDRESS COUNTER DATA-IN REGISTER CONTROL LOGIC BUFFER OE ZZ 36 or 18 DQa0 ~ DQd 7 or DQa 0 ~ DQb8 DQPa ~ DQPd NtRAMT M and No Turnaround Random Access Memory are trademarks of Samsung. -2- February 2001 Rev 3.0 K7M163625M K7M161825M 512Kx36 & 1Mx18 Flow-Through NtRAM TM A6 A7 CS1 CS2 BWd BWc BWb BWa CS2 VDD VSS CLK WE CKE OE ADV A18 A17 A8 A9 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 100 Pin TQFP (20mm x 14mm) 47 48 49 50 A13 A14 A15 A16 45 A11 46 44 A10 A12 43 41 VDD N.C. 40 V SS 42 39 N.C. N.C. 38 N.C. 35 A2 37 34 A3 A0 33 A4 36 32 A1 31 K7M163625M(512Kx36) A5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 L BO DQPc DQc 0 DQc 1 VDDQ VSSQ DQc 2 DQc 3 DQc 4 DQc 5 VSSQ VDDQ DQc 6 DQc 7 Vss V DD V DD VSS DQd 0 DQd 1 VDDQ VSSQ DQd 2 DQd 3 DQd 4 DQd 5 VSSQ VDDQ DQd 6 DQd 7 DQPd 100 PIN CONFIGURATION (TOP VIEW) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 DQPb DQb7 DQb6 VDDQ VSSQ DQb5 DQb4 DQb3 DQb2 VSSQ VDDQ DQb1 DQb0 VSS VSS VDD ZZ DQa7 DQa6 VDDQ VSSQ DQa5 DQa4 DQa3 DQa2 VSSQ VDDQ DQa1 DQa0 DQPa PIN NAME SYMBOL A0 - A18 PIN NAME TQFP PIN NO. SYMBOL Address Inputs 32,33,34,35,36,37,44 45,46,47,48,49,50,81 82,83,84,99,100 ADV Address Advance/Load 85 WE Read/Write Control Input 88 CLK Clock 89 CKE Clock Enable 87 CS1 Chip Select 98 CS2 Chip Select 97 CS2 Chip Select 92 BWx(x=a,b,c,d) Byte Write Inputs 93,94,95,96 OE Output Enable 86 ZZ Power Sleep Mode 64 LBO Burst Mode Control 31 PIN NAME TQFP PIN NO. VDD VSS Power Supply(+3.3V) 15,16,41,65,91 Ground 14,17,40,66,67,90 N.C. No Connect 38,39,42,43 DQa0~a 7 DQb0~b 7 DQc 0~c7 DQd0~d 7 DQPa~P d Data Inputs/Outputs Data Inputs/Outputs Data Inputs/Outputs Data Inputs/Outputs Data Inputs/Outputs 52,53,56,57,58,59,62,63 68,69,72,73,74,75,78,79 2,3,6,7,8,9,12,13 18,19,22,23,24,25,28,29 51,80,1,30 VDDQ Output Power Supply 4,11,20,27,54,61,70,77 (2.5V or 3.3V) Output Ground 5,10,21,26,55,60,71,76 VSSQ Notes : 1. A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired. -3- February 2001 Rev 3.0 K7M163625M K7M161825M 512Kx36 & 1Mx18 Flow-Through NtRAM TM A7 CS1 CS2 N.C. N.C. BWb BWa CS2 VDD VSS CLK WE CKE OE ADV A19 A18 A8 A9 98 97 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 96 A6 99 100 Pin TQFP (20mm x 14mm) 45 46 47 48 49 50 A13 A14 A15 A16 A17 44 A11 A12 43 40 V SS N.C. 39 N.C. 42 38 N.C. N.C. 37 A0 41 36 A1 VDD 35 A2 33 A4 34 32 A3 31 K7M161825M(1Mx18) A5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 L BO N.C. N.C. N.C. VDDQ VSSQ N.C. N.C. DQb 8 DQb 7 VSSQ VDDQ DQb 6 DQb 5 VSS V DD V DD VSS DQb 4 DQb 3 VDDQ VSSQ DQb 2 DQb 1 DQb 0 N.C. VSSQ VDDQ N.C. N.C. N.C. 100 PIN CONFIGURATION (TOP VIEW) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A10 N.C. N.C. VDDQ VSSQ N.C. DQa0 DQa1 DQa2 VSSQ VDDQ DQa3 DQa4 VSS VSS VDD ZZ DQa5 DQa6 VDDQ VSSQ DQa7 DQa8 N.C. N.C. VSSQ VDDQ N.C. N.C. N.C. PIN NAME SYMBOL PIN NAME A 0 - A19 Address Inputs ADV WE CLK CKE CS 1 CS 2 CS 2 BW x(x=a,b) OE ZZ LBO Address Advance/Load Read/Write Control Input Clock Clock Enable Chip Select Chip Select Chip Select Byte Write Inputs Output Enable Power Sleep Mode Burst Mode Control TQFP PIN NO. 32,33,34,35,36,37,44 45,46,47,48,49,50,80 81,82,83,84,99,100 85 88 89 87 98 97 92 93,94 86 64 31 SYMBOL PIN NAME TQFP PIN NO. VDD VSS Power Supply(+3.3V) Ground 15,16,41,65,91 14,17,40,66,67,90 N.C. No Connect 1,2,3,6,7,25,28,29,30, 38,39,42,43,51,52,53, 56,57,75,78,79,95,96 DQa0~a 8 DQb0~b 8 Data Inputs/Outputs Data Inputs/Outputs 58,59,62,63,68,69,72,73,74 8,9,12,13,18,19,22,23,24 VDDQ Output Power Supply (2.5V or 3.3V) Output Ground 4,11,20,27,54,61,70,77 VSSQ 5,10,21,26,55,60,71,76 Notes : 1. A0 and A 1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired. -4- February 2001 Rev 3.0 K7M163625M K7M161825M 512Kx36 & 1Mx18 Flow-Through NtRAM TM 119BGA PACKAGE PIN CONFIGURATIONS(TOP VIEW) K7M163625M(512Kx36) 1 2 3 4 5 6 7 A VDDQ A A A A A VDDQ B NC CS2 A ADV A CS2 NC C NC A A V DD A A NC D DQc DQPc V SS NC VSS DQPb DQb E DQc DQc V SS CS1 VSS DQb DQb F VDDQ DQc V SS OE VSS DQb VDDQ G DQc DQc BWc A BW b DQb DQb H DQc DQc V SS WE VSS DQb DQb J VDDQ V DD NC V DD NC V DD VDDQ K DQd DQd V SS CLK VSS DQa DQa L DQd DQd BWd NC BW a DQa DQa M VDDQ DQd V SS CKE VSS DQa VDDQ N DQd DQd V SS A1* VSS DQa DQa P DQd DQPd V SS A0* VSS DQPa DQa R NC A LBO V DD NC A NC T NC NC A A A NC ZZ U VDDQ NC NC NC NC NC VDDQ Note : * A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired. PIN NAME SYMBOL PIN NAME A Address Inputs A0,A1 ADV WE CLK CKE CS1 CS2 CS2 BWx (x=a,b,c,d) Burst Address Inputs Address Advance/Load Read/Write Control Input Clock Clock Enable Chip Select Chip Select Chip Select Byte Write Inputs OE ZZ LBO Output Enable Power Sleep Mode Burst Mode Control SYMBOL PIN NAME VDD VSS Power Supply Ground N.C. No Connect DQa DQb DQc DQd DQPa~Pd Data Data Data Data Data VDDQ Output Power Supply -5- Inputs/Outputs Inputs/Outputs Inputs/Outputs Inputs/Outputs Inputs/Outputs February 2001 Rev 3.0 K7M163625M K7M161825M 512Kx36 & 1Mx18 Flow-Through NtRAM TM 119BGA PACKAGE PIN CONFIGURATIONS(TOP VIEW) K7M161825M(1Mx18) Note : 1 2 3 4 5 6 7 A VDDQ A A A A A VDDQ B NC CS2 A ADV A CS2 NC C NC A A V DD A A NC D DQb NC V SS NC VSS DQPa NC E NC DQb V SS CS1 VSS NC DQa F VDDQ NC V SS OE VSS DQa VDDQ G NC DQb BWb A VSS NC DQa H DQb NC V SS WE VSS DQa NC J VDDQ V DD NC V DD NC V DD VDDQ K NC DQb V SS CLK VSS NC DQa L DQb NC V SS NC BW a DQa NC M VDDQ DQb V SS CKE VSS NC VDDQ N DQb NC V SS A1* VSS DQa NC P NC DQPb V SS A0* VSS NC DQa R NC A LBO V DD NC A NC T NC A A NC A A ZZ U VDDQ NC NC NC NC NC VDDQ * A0 and A 1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired. PIN NAME SYMBOL PIN NAME A Address Inputs A0,A1 ADV WE CLK CKE CS1 CS2 CS2 BWx (x=a,b) Burst Address Inputs Address Advance/Load Read/Write Control Input Clock Clock Enable Chip Select Chip Select Chip Select Byte Write Inputs OE ZZ LBO Output Enable Power Sleep Mode Burst Mode Control SYMBOL PIN NAME VDD VSS Power Supply Ground N.C. No Connect DQa DQb DQPa, Pb Data Inputs/Outputs Data Inputs/Outputs Data Inputs/Outputs VDDQ Output Power Supply -6- February 2001 Rev 3.0 K7M163625M K7M161825M 512Kx36 & 1Mx18 Flow-Through NtRAM TM FUNCTION DESCRIPTION The K7M163625M and K7M161825M are N tRAM TM designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from Read to Write, or vice versa. All inputs (with the exception of OE, LBO and ZZ) are synchronized to rising clock edges. All read, write and deselect cycles are initiated by the ADV input. Subsequent burst addresses can be internally generated by th e burst advance pin (ADV). ADV should be driven to Low once the device has been deselected in order to load a new address for next operation. Clock Enable( CKE) pin allows the operation of the chip to be suspended as long as necessary. When CKE is high, all synchronous inputs are ignored and the internal device registers will hold their previous values. NtRAM T M latches external address and initiates a cycle, when CKE , ADV are driven to low and all three chip enables(CS1, CS 2, CS2) are active . Output Enable( OE) can be used to disable the output at any given time. Read operation is initiated when at the rising edge of the clock, the address presented to the address inputs are latched in the address register, CKE is driven low, all three chip enables(CS 1, CS2, CS 2) are active, the write enable input signals WE are driven high, and ADV driven low. Data appears at the outputs within the same clock cycle as the address for the data. Also during read operation OE must be driven low for the device to drive out the requested data. Write operation occurs when WE is driven low at the rising edge of the clock. BW [d:a] can be used for byte write operation. The Flow Through NtRAMTM uses a late write cycle to utilize 100% of the bandwidth. At the first rising edge of the clock, WE and address are registered, and the data associated with that address is required one cycle later. Subsequent addresses are generated by ADV High for the burst access as shown below. The starting point of the burst seguence is provided by the external address. The burst address counter wraps around to its initial state upon completion. The burst sequence is determined by the state of the LBO pin. When this pin is low, linear burst sequence is selected. And when this pin is high, Interleaved burst sequence is selected. During normal operation, ZZ must be driven low. When ZZ is driven high, the SRAM will enter a Power Sleep Mode after 2 cycles. A t this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM normally operates after 2 cycles of wake up time. BURST SEQUENCE TABLE LBO PIN HIGH First Address Fourth Address (Interleaved Burst, LBO=High) Case 1 Case 2 Case 3 A0 A1 A0 A1 A0 A1 A0 0 0 1 1 0 1 0 1 0 0 1 1 1 0 1 0 1 1 0 0 0 1 0 1 1 1 0 0 1 0 1 0 BQ TABLE LBO PIN Case 4 A1 (Linear Burst, LBO=Low) LOW First Address Fourth Address Case 1 A1 0 0 1 1 Case 2 A0 0 1 0 1 A1 0 1 1 0 Case 3 A0 1 0 1 0 A1 1 1 0 0 Case 4 A0 0 1 0 1 A1 1 0 0 1 A0 1 0 1 0 Note : 1. LBO pin must be tied to High or Low, and Floating State must not be allowed. -7- February 2001 Rev 3.0 K7M163625M K7M161825M 512Kx36 & 1Mx18 Flow-Through NtRAM TM STATE DIAGRAM FOR NtRAMTM WRITE READ READ BEGIN READ BEGIN WRITE DS RE A D W ST BU R I TE B URST R E IT E DS W D R A BURST READ BURST WRITE COMMAND DS WR DESELECT ST RE A DS DS BURST TE RI BU R D DS WRITE BURST ACTION DESELECT READ BEGIN READ WRITE BEGIN WRITE BURST BEGIN READ BEGIN WRITE CONTINUE DESELECT Notes : 1. An IGNORE CLOCK EDGE cycle is not shown is the above diagram. This is because CKE HIGH only blocks the clock(CLK) input and does not change the state of the device. 2. States change on the rising edge of the clock(CLK) -8- February 2001 Rev 3.0 K7M163625M K7M161825M 512Kx36 & 1Mx18 Flow-Through NtRAM TM TRUTH TABLES SYNCHRONOUS TRUTH TABLE CS1 CS2 CS2 ADV WE BWx OE CKE CLK ADDRESS ACCESSED OPERATION H X X L X X X L ↑ N/A Not Selected X L X L X X X L ↑ N/A Not Selected X X H L X X X L ↑ N/A Not Selected X X X H X X X L ↑ N/A Not Selected Continue L H L L H X L L ↑ External Address Begin Burst Read Cycle X X X H X X L L ↑ Next Address Continue Burst Read Cycle L H L L H X H L ↑ External Address NOP/Dummy Read X X X H X X H L ↑ Next Address Dummy Read L H L L L L X L ↑ External Address Begin Burst Write Cycle X X X H X L X L ↑ Next Address Continue Burst Write Cycle L H L L L H X L ↑ N/A NOP/Write Abort X X X H X H X L ↑ Next Address Write Abort X X X X X X X H ↑ Current Address Ignore Clock Notes : 1. X means "Don′t Care". 2. The rising edge of clock is symbolized by (↑). 3. A continue deselect cycle can only be enterd if a deselect cycle is executed first. 4. WRITE = L means Write operation in WRITE TRUTH TABLE. WRITE = H means Read operation in WRITE TRUTH TABLE. 5. Operation finally depends on status of asynchronous input pins(ZZ and OE). WRITE TRUTH TABLE ( x36) WE BWa BWb BWc BWd H X X X X OPERATION READ L L H H H WRITE BYTE a L H L H H WRITE BYTE b L H H L H WRITE BYTE c L H H H L WRITE BYTE d L L L L L WRITE ALL BYTEs L H H H H WRITE ABORT/NOP Notes : 1. X means "Don′t Care". 2. All inputs in this table must meet setup and hold time around the rising edge of CLK(↑ ). WRITE TRUTH TABLE(x18) WE BWa BWb H X X OPERATION READ L L H WRITE BYTE a L H L WRITE BYTE b L L L WRITE ALL BYTEs L H H WRITE ABORT/NOP Notes : 1. X means "Don ′t Care". 2. All inputs in this table must meet setup and hold time around the rising edge of CLK(↑). -9- February 2001 Rev 3.0 K7M163625M K7M161825M 512Kx36 & 1Mx18 Flow-Through NtRAM TM ASYNCHRONOUS TRUTH TABLE Operation ZZ OE I/O STATUS Sleep Mode H X High-Z L L DQ Read L H High-Z Write L X Din, High-Z Deselected L X High-Z Notes 1. X means "Don ′t Care". 2. Sleep Mode means power Sleep Mode of which stand-by current does not depend on cycle time. 3. Deselected means power Sleep Mode of which stand-by current depends on cycle time. ABSOLUTE MAXIMUM RATINGS* SYMBOL RATING UNIT Voltage on VDD Supply Relative to VSS PARAMETER VDD -0.3 to 4.6 V Voltage on Any Other Pin Relative to VSS VIN -0.3 to 4.6 V Power Dissipation PD 1.6 W T STG -65 to 150 °C Storage Temperature Operating Temperature TOPR 0 to 70 °C Storage Temperature Range Under Bias T BIAS -10 to 85 °C *Notes : Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. OPERATING CONDITIONS at 3.3V I/O(0 °C ≤ TA ≤ 70°C) PARAMETER Supply Voltage Ground SYMBOL MIN Typ. MAX UNIT VDD 3.135 3.3 3.465 V V DDQ 3.135 3.3 3.465 V V SS 0 0 0 V OPERATING CONDITIONS at 2.5V I/O(0 °C ≤ TA ≤ 70°C) PARAMETER Supply Voltage Ground SYMBOL MIN Typ. MAX UNIT VDD 3.135 3.3 3.465 V V DDQ 2.375 2.5 2.9 V V SS 0 0 0 V CAPACITANCE* (TA =25°C, f=1MHz) PARAMETER Input Capacitance Output Capacitance SYMBOL TEST CONDITION MIN MAX UNIT CIN V IN=0V - 7 pF COUT V OUT=0V - 9 pF *Note : Sampled not 100% tested. - 10 - February 2001 Rev 3.0 K7M163625M K7M161825M 512Kx36 & 1Mx18 Flow-Through NtRAM TM DC ELECTRICAL CHARACTERISTICS(V DD=3.3V+0.165V/-0.165V, T A =0°C to +70°C) MIN MAX Input Leakage Current(except ZZ) PARAMETER SYMBOL I IL V DD=Max ; VIN=V SS to VDD -2 +2 µA Output Leakage Current IOL Output Disabled, -2 +2 µA -75 - 340 ZZ ≤ VIL , Cycle Time ≥ tCYC Min -85 - 320 -90 - 300 Device deselected, IOUT =0mA, -75 - 90 ZZ ≤ VIL, f=Max, -85 - 80 All Inputs ≤ 0.2V or ≥ V DD -0.2V -90 - 70 - 30 mA - 30 mA Operating Current I CC ISB Standby Current ISB1 ISB2 TEST CONDITIONS Device Selected, IOUT =0mA, Device deselected, IOUT =0mA, ZZ ≤ 0.2V, f=0, All Inputs=fixed (V DD-0.2V or 0.2V) Device deselected, IOUT =0mA, ZZ≥VDD -0.2V, f=Max, All Inputs ≤ VIL or ≥V IH UNIT NOTES mA 1,2 mA Output Low Voltage(3.3V I/O) VOL I OL =8.0mA - 0.4 V Output High Voltage(3.3V I/O) V OH I OH=-4.0mA 2.4 - V Output Low Voltage(2.5V I/O) VOL I OL =1.0mA - 0.4 V Output High Voltage(2.5V I/O) V OH I OH=-1.0mA 2.0 - V Input Low Voltage(3.3V I/O) VIL -0.3* 0.8 V Input High Voltage(3.3V I/O) VIH 2.0 VDD +0.5** V Input Low Voltage(2.5V I/O) VIL -0.3* 0.7 V Input High Voltage(2.5V I/O) VIH 1.7 VDD +0.5** V 3 3 Notes : 1. Reference AC Operating Conditions and Characteristics for input and timing. 2. Data states are all zero. 3. In Case of I/O Pins, the Max. VIH =V D D Q +0.3V. V IH VS S VS S - 1.0V 20% tC Y C (MIN) TEST CONDITIONS (VDD=3.3V+0.165V/-0.165V,VDDQ=3.3V+0.165/-0.165V or VDD=3.3V+0.165V/-0.165V,VDDQ=2.5V+0.4V/-0.125V, TA=0to70°C) PARAMETER VALUE Input Pulse Level(for 3.3V I/O) 0 to 3.0V Input Pulse Level(for 2.5V I/O) 0 to 2.5V Input Rise and Fall Time(Measured at 20% to 80% for 3.3V I/O) 1.0V/ns Input Rise and Fall Time(Measured at 20% to 80% for 2.5V I/O) 1.0V/ns Input and Output Timing Reference Levels for 3.3V I/O 1.5V Input and Output Timing Reference Levels for 2.5V I/O VDDQ/2 Output Load See Fig. 1 - 11 - February 2001 Rev 3.0 K7M163625M K7M161825M 512Kx36 & 1Mx18 Flow-Through NtRAM TM Output Load(A) Output Load(B), (for tLZC, t LZOE, tHZOE & t HZC) +3.3V for 3.3V I/O /+2.5V for 2.5V I/O RL=50Ω Dout Zo=50Ω 30pF* VL=1.5V for 3.3V I/O V DDQ/2 for 2.5V I/O 319Ω / 1667Ω Dout 353Ω / 1538Ω 5pF* * Including Scope and Jig Capacitance Fig. 1 AC TIMING CHARACTERISTICS(V DD=3.3V+0.165V/-0.165V, T A=0 °C to +70°C) -75 PARAMETER SYMBOL -85 -90 MIN MAX MIN MAX MIN MAX UNIT Cycle Time tCYC 8.5 - 10 - 10 - ns Clock Access Time t CD - 7.5 - 8.5 - 9.0 ns Output Enable to Data Valid t OE - 4.0 - 4.0 - 4.0 ns Clock High to Output Low-Z t LZC 2.5 - 2.5 - 2.5 - ns Output Hold from Clock High tOH 2.5 - 2.5 - 2.5 - ns Output Enable Low to Output Low-Z t LZOE 0 - 0 - 0 - ns Output Enable High to Output High-Z t HZOE - 4.0 - 4.0 - 4.0 ns Clock High to Output High-Z t HZC - 5.0 - 5.0 - 5.0 ns Clock High Pulse Width t CH 2.5 - 3.0 - 3.0 - ns Clock Low Pulse Width tCL 2.5 - 3.0 - 3.0 - ns Address Setup to Clock High t AS 2.0 - 2.0 - 2.0 - ns CKE Setup to Clock High t CES 2.0 - 2.0 - 2.0 - ns Data Setup to Clock High t DS 2.0 - 2.0 - 2.0 - ns Write Setup to Clock High ( WE, BW X) t WS 2.0 - 2.0 - 2.0 - ns Address Advance Setup to Clock High t ADVS 2.0 - 2.0 - 2.0 - ns Chip Select Setup to Clock High t CSS 2.0 - 2.0 - 2.0 - ns Address Hold from Clock High t AH 0.5 - 0.5 - 0.5 - ns CKE Hold from Clock High tCEH 0.5 - 0.5 - 0.5 - ns Data Hold from Clock High t DH 0.5 - 0.5 - 0.5 - ns Write Hold from Clock High (WE , BWX ) t WH 0.5 - 0.5 - 0.5 - ns Address Advance Hold from Clock High ns t ADVH 0.5 - 0.5 - 0.5 - Chip Select Hold from Clock High tCSH 0.5 - 0.5 - 0.5 - ns ZZ High to Power Down t PDS 2 - 2 - 2 - cycle ZZ Low to Power Up t PUS 2 - 2 - 2 - cycle Notes : 1. All address inputs must meet the specified setup and hold times for all rising clock(CLK) edges when ADV is sampled low and CS is sampled low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected. 2. Chip selects must be valid at each rising edge of CLK(when ADV is Low) to remain enabled. 3. A write cycle is defined by WE low having been registerd into the device at ADV Low, A Read cycle is defined by WE High with ADV Low, Both cases must meet setup and hold times. 4. To avoid bus contention, At a given vlotage and temperature tL Z C is more than tH Z C . The soecs as shown do not imply bus contention because tL Z C is a Min. parameter that is worst case at totally different test conditions (0°C,3.465V) than tH Z C , which is a Max. parameter(worst case at 70° C,3.135V) It is not possible for two SRAMs on the same board to be at such different voltage and temperatue. - 12 - February 2001 Rev 3.0 K7M163625M K7M161825M 512Kx36 & 1Mx18 Flow-Through NtRAM TM SLEEP MODE SLEEP MODE is a low current, power-down mode in which the device is deselected and current is reduced to I SB2. The duration of SLEEP MODE is dictated by the length of time the ZZ is in a High state. After entering SLEEP MODE, all inputs except ZZ become disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter SLEEP MODE. When the ZZ pin becomes a logic High, ISB2 is guaranteed after the time tZZI is met. Any operation pending when entering SLEEP MODE is not guaranteed to successful complete. Therefore, SLEEP MODE (READ or WRITE) must not be initiated until valid pending operations are completed. similarly, when exiting SLEEP MODE during tPUS, only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SLEEP MODE. SLEEP MODE ELECTRICAL CHARACTERISTICS DESCRIPTION Current during SLEEP MODE CONDITIONS SYMBOL ZZ ≥ VIH ISB2 MIN MAX 10 ZZ active to input ignored t PDS 2 ZZ inactive to input sampled t PUS 2 ZZ active to SLEEP current t ZZI ZZ inactive to exit SLEEP current tRZZI UNITS mA cycle cycle 2 cycle 0 SLEEP MODE WAVEFORM K t PDS ZZ setup cycle tP U S ZZ recovery cycle ZZ t ZZI Isupply I SB2 t RZZI All inputs (except ZZ) Deselect or Read Only Deselect or Read Only Normal operation cycle Outputs (Q) High-Z DON′ T CARE - 13 - February 2001 Rev 3.0 - 14 - Data Out OE ADV CS WRITE Address CKE Clock A1 tLZ OE t OE t ADVH t CSH t WH tAH Q1 -1 t HZOE A2 tCEH Q2- 1 t OH t CD Q 2-2 Q2- 3 NOTES : WRITE = L means WE = L, and BWx = L CS = L means CS 1 = L, CS 2 = H and CS 2 = L CS = H means CS1 = H, or CS1 = L and CS 2 = H, or CS 1 = L, and CS 2 = L tADVS tCSS t WS t AS t CES t CL t CYC tC H Q2 -4 A3 TIMING WAVEFORM OF READ CYCLE Q3- 1 Q3- 2 Q 3-3 Q3-4 t HZC Undefined Don′t Care K7M163625M K7M161825M 512Kx36 & 1Mx18 Flow-Through NtRAM TM February 2001 Rev 3.0 - 15 - Data O ut Data In OE ADV CS WRITE Address CKE Clock tH ZOE D1-1 A2 t CYC D2-1 t CL D2-2 NOT ES : WRITE = L means WE = L, and BWx = L CS = L means CS1 = L, CS 2 = H and CS 2 = L CS = H means CS 1 = H, or CS1 = L and C S2 = H, or CS 1 = L, and CS2 = L Q0- 4 A1 t CES t CEH tC H D2 -3 D2-4 A3 TIMING WAVEFORM OF WRTE CYCLE D3 -1 t DS D3- 2 tD H D3 -3 D3-4 Undefined Don′t Care K7M163625M K7M161825M 512Kx36 & 1Mx18 Flow-Through NtRAM TM February 2001 Rev 3.0 - 16 - Data In Data O ut OE ADV CS WRITE Address CKE Clock Q1 A2 t DS D2 A3 t DH Q3 A4 NOTES : WRITE = L means WE = L, and BWx = L CS = L means C S1 = L, CS 2 = H and CS 2 = L CS = H means CS1 = H, or CS1 = L and CS 2 = H, or CS 1 = L, and CS 2 = L t OE t LZOE A1 t CES tC EH Q4 A5 D5 A6 Q6 A7 TIMING WAVEFORM OF SINGLE READ/WRITE tCH Q7 t CYC t CL Undefined Don′t Care K7M163625M K7M161825M 512Kx36 & 1Mx18 Flow-Through NtRAM TM February 2001 Rev 3.0 - 17 - Data In tCD t LZC A1 t CES t CEH Q1 t HZC A2 t DS D2 A3 t DH NOTES : WRITE = L means WE = L, and BWx = L CS = L means CS 1 = L, CS2 = H and CS2 = L CS = H means CS 1 = H, or CS 1 = L and CS2 = H, or CS1 = L, and CS 2 = L Data Out OE ADV CS WRITE Address CKE Clock Q3 A4 TIMING WAVEFORM OF CKE OPERATION t CH Q4 tCYC t CL A5 Undefined Don′t Care K7M163625M K7M161825M 512Kx36 & 1Mx18 Flow-Through NtRAM TM February 2001 Rev 3.0 - 18 - Data In Data O ut OE ADV CS WRITE Address CKE Clock t OE t LZOE A1 tC EH Q1 A2 Q2 t HZC A3 t DH D3 t DS NOTES : WRITE = L means WE = L, and BWx = L CS = L means CS1 = L, CS 2 = H and CS 2 = L CS = H means CS 1 = H, or CS1 = L and CS 2 = H, or CS 1 = L, and C S2 = L t CES t CD t LZC A4 Q4 TIMING WAVEFORM OF CS OPERATION A5 D5 t CH tCYC t CL Undefined Don′t Care K7M163625M K7M161825M 512Kx36 & 1Mx18 Flow-Through NtRAM TM February 2001 Rev 3.0 K7M163625M K7M161825M 512Kx36 & 1Mx18 Flow-Through NtRAM TM PACKAGE DIMENSIONS 100-TQFP-1420A Units ; millimeters/Inches 0~8° 22.00 ±0 . 3 0 0.127 +- 00..10 05 20.00 ±0 . 2 0 16.00 ±0 . 3 0 14.00 ± 0.20 0.10 MAX (0.83) 0.50 ±0.10 #1 0.65 (0.58) 0.30 ±0 . 1 0 0.10 MAX 1.40 ± 0.10 0.50 ± 0.10 - 19 - 1.60 MAX 0.05 MIN February 2001 Rev 3.0 K7M163625M K7M161825M 512Kx36 & 1Mx18 Flow-Through NtRAM TM 119BGA PACKAGE DIMENSIONS 14.00 ±0.10 1.27 1.27 22.00 ±0.10 Indicator of Ball(1A) Location 20.50±0.10 C0.70 C1.00 0.750±0.15 1.50REF 0.60±0.10 0.60 ±0.10 12.50±0.10 Notes 1. All Dimensions are in Millimeters. 2. Solder Ball to PCB Offset : 0.10 MAX. 3. PCB to Cavity Offset : 0.10 MAX. - 20 - February 2001 Rev 3.0