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Preliminary
FLASH MEMORY
K9L8G08U1A
K9G4G08U0A K9G4G08B0A
K9XXG08XXA
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
1
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Preliminary
FLASH MEMORY
K9L8G08U1A
K9G4G08U0A K9G4G08B0A
Document Title
512M x 8 Bit / 1G x 8 Bit NAND Flash Memory
Revision History
Revision No
History
Draft Date
Remark
0.0
1. Initial issue
May. 2nd 2006
Advance
0.1
1. Add 2.7V part
2. Add note of command set table
3. Add nWP timing guide
4. Endurance 10K -> 5K
Sep. 25st 2006
Preliminary
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near your office.
2
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Preliminary
FLASH MEMORY
K9L8G08U1A
K9G4G08U0A K9G4G08B0A
512M x 8 Bit / 1G x 8 Bit NAND Flash Memory
PRODUCT LIST
Part Number
Vcc Range
K9G4G08B0A
2.5V ~ 2.9V
Organization
MCP(TBD)
K9G4G08U0A-P
K9G4G08U0A-I
PKG Type
X8
2.7V ~ 3.6V
TSOP1
52ULGA
K9L8G08U1A-I
FEATURES
• Voltage Supply
- 2.7V Device(K9G4G08B0A) : 2.5V ~ 2.9V
- 3.3V Device(K9G4G08U0A) : 2.7V ~ 3.6V
• Organization
- Memory Cell Array : (512M + 16M) x 8bit
- Data Register : (2K + 64) x 8bit
• Automatic Program and Erase
- Page Program : (2K + 64)Byte
- Block Erase : (256K + 8K)Byte
• Page Read Operation
- Page Size : (2K + 64)Byte
- Random Read : 60µs(Max.)
- Serial Access : 30ns(Min.)
• Memory Cell : 2bit / Memory Cell
• Fast Write Cycle Time
- Program time : 800µs(Typ.)
- Block Erase Time : 1.5ms(Typ.)
• Command/Address/Data Multiplexed I/O Port
• Hardware Data Protection
- Program/Erase Lockout During Power Transitions
• Reliable CMOS Floating-Gate Technology
- Endurance : 5K Program/Erase Cycles(with 4bit/512byte ECC)
- Data Retention : 10 Years
• Command Register Operation
• Unique ID for Copyright Protection
• Package :
- K9G4G08U0A-PCB0/PIB0 : Pb-FREE PACKAGE
48 - Pin TSOP1(12 x 20 / 0.5 mm pitch)
- K9G4G08U0A-ICB0/IIB0
52 - Pin ULGA (12 x 17 / 1.00 mm pitch)
- K9L8G08U1A-ICB0/IIB0
52 - Pin ULGA (12 x 17 / 1.00 mm pitch)
- K9G4G08B0A : MCP(TBD)
GENERAL DESCRIPTION
Offered in 512Mx8bit, the K9G4G08X0A is a 4G-bit NAND Flash Memory with spare 128M-bit. The device is offered in 2.7V and 3.3V
Vcc. Its NAND cell provides the most cost-effective solution for the solid state mass storage market. A program operation can be performed in typical 800µs on the 2,112-byte page and an erase operation can be performed in typical 1.5ms on a (256K+8K)byte block.
Data in the data register can be read out at 30ns cycle time per byte. The I/O pins serve as the ports for address and data input/output as well as command input. The on-chip write controller automates all program and erase functions including pulse repetition,
where required, and internal verification and margining of data. Even the write-intensive systems can take advantage of the
K9G4G08X0A′s extended reliability of 5K program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out
algorithm. The K9G4G08X0A is an optimum solution for large nonvolatile storage applications such as solid state file storage and
other portable applications requiring non-volatility.
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Preliminary
FLASH MEMORY
K9L8G08U1A
K9G4G08U0A K9G4G08B0A
PIN CONFIGURATION (TSOP1)
K9G4G08U0A-PCB0/PIB0
N.C
N.C
N.C
N.C
N.C
N.C
R/B
RE
CE
N.C
N.C
Vcc
Vss
N.C
N.C
CLE
ALE
WE
WP
N.C
N.C
N.C
N.C
N.C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48-pin TSOP1
Standard Type
12mm x 20mm
N.C
N.C
N.C
N.C
I/O7
I/O6
I/O5
I/O4
N.C
N.C
N.C
Vcc
Vss
N.C
N.C
N.C
I/O3
I/O2
I/O1
I/O0
N.C
N.C
N.C
N.C
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
PACKAGE DIMENSIONS
48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)
Unit :mm/Inch
0.10
MAX
0.004
48 - TSOP1 - 1220AF
#48
#24
#25
12.40
0.488 MAX
12.00
0.472
+0.003
( 0.25 )
0.010
#1
0.008-0.001
0.50
0.0197
0.16 -0.03
+0.075
18.40±0.10
0.724±0.004
0~8°
0.45~0.75
0.018~0.030
+0.003
0.005-0.001
0.25
0.010 TYP
1.00±0.05
0.039±0.002
0.125 0.035
+0.07
0.20 -0.03
+0.07
20.00±0.20
0.787±0.008
( 0.50 )
0.020
4
1.20
0.047MAX
0.05
0.002 MIN
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Preliminary
FLASH MEMORY
K9L8G08U1A
K9G4G08U0A K9G4G08B0A
PIN CONFIGURATION (ULGA)
K9G4G08U0A-ICB0/IIB0
A
NC
C
B
E
D
F
G
H
NC
NC
K
J
NC
L
M
N
NC
NC
7
NC
6
/RE
Vcc
NC
NC
NC
Vss
NC
IO7
NC
NC
IO5
Vcc
5
4
/CE
3
2
R/B
NC
NC
CLE
IO6
IO0
/WE
NC
Vss
NC
IO4
IO2
IO1
/WP
NC
Vss
NC
Vss
IO3
1
NC
NC
ALE
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
PACKAGE DIMENSIONS
52-ULGA (measured in millimeters)
Bottom View
Top View
12.00±0.10
10.00
1.00
1.00
2.00
7
(Datum A)
6
5
4
3
2
1
B
1.00
1.00
1.30
12.00±0.10
A
#A1
A
B
C
17.00±0.10
E
F
1.00
H
1.00
2.50
G
J
2.00
K
0.50
L
M
N
Side View
17.00±0.10
0.10 C
5
41-∅0.70±0.05
∅0.1
M C AB
0.65(Max.)
12-∅1.00±0.05
∅0.1 M C AB
12.00
17.00±0.10
1.00
2.50
D
(Datum B)
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Preliminary
FLASH MEMORY
K9L8G08U1A
K9G4G08U0A K9G4G08B0A
K9L8G08U1A-ICB0/IIB0
A
C
B
NC
E
D
G
F
H
NC
NC
L
K
J
NC
M
N
NC
NC
7
NC
6
/RE1
Vcc
R/B2
/RE2
IO7-2
Vss
IO6-2
IO7-1
NC
IO5-2
IO5-1
Vcc
5
4
/CE1
3
2
CLE1
/CE2
R/B1
CLE2
/WE1
ALE2
Vss
/WP2
IO6-1
IO0-1
IO2-1
IO1-1
/WP1
IO4-1
IO4-2
Vss
IO3-2
Vss
IO3-1
1
NC
NC
ALE1
NC
/WE2
IO0-2
IO1-2
NC
NC
NC
IO2-2
NC
NC
PACKAGE DIMENSIONS
52-ULGA (measured in millimeters)
Bottom View
Top View
12.00±0.10
10.00
1.00
1.00
2.00
7
(Datum A)
6
5
4
3
2
1
B
1.00
1.00
1.30
12.00±0.10
A
#A1
A
B
C
17.00±0.10
E
F
1.00
H
1.00
2.50
G
J
2.00
K
0.50
L
M
N
Side View
17.00±0.10
0.10 C
6
41-∅0.70±0.05
∅0.1
M C AB
0.65(Max.)
12-∅1.00±0.05
∅0.1 M C AB
12.00
17.00±0.10
1.00
2.50
D
(Datum B)
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Preliminary
FLASH MEMORY
K9L8G08U1A
K9G4G08U0A K9G4G08B0A
PIN DESCRIPTION
Pin Name
Pin Function
I/O0 ~ I/O7
DATA INPUTS/OUTPUTS
The I/O pins are used to input command, address and data, and to output data during read operations. The I/
O pins float to high-z when the chip is deselected or when the outputs are disabled.
CLE
COMMAND LATCH ENABLE
The CLE input controls the activating path for commands sent to the command register. When active high,
commands are latched into the command register through the I/O ports on the rising edge of the WE signal.
ALE
ADDRESS LATCH ENABLE
The ALE input controls the activating path for address to the internal address registers. Addresses are
latched on the rising edge of WE with ALE high.
CE
CHIP ENABLE
The CE input is the device selection control. When the device is in the Busy state, CE high is ignored, and
the device does not return to standby mode in program or erase operation. Regarding CE control during
read operation, refer to ’Page read’ section of Device operation.
RE
READ ENABLE
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid
tREA after the falling edge of RE which also increments the internal column address counter by one.
WE
WRITE ENABLE
The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of
the WE pulse.
WP
WRITE PROTECT
The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage
generator is reset when the WP pin is active low.
R/B
READY/BUSY OUTPUT
The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or
random read operation is in process and returns to high state upon completion. It is an open drain output and
does not float to high-z condition when the chip is deselected or when outputs are disabled.
Vcc
POWER
VCC is the power supply for device.
Vss
GROUND
N.C
NO CONNECTION
Lead is not internally connected.
NOTE : Connect all VCC and VSS pins of each device to common power supply outputs.
Do not leave VCC or VSS disconnected.
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Preliminary
FLASH MEMORY
K9L8G08U1A
K9G4G08U0A K9G4G08B0A
Figure 1-1. K9G4G08X0A Functional Block Diagram
VCC
VSS
A12 - A29
X-Buffers
Latches
& Decoders
4,096M + 128M Bit
NAND Flash
ARRAY
A0 - A11
Y-Buffers
Latches
& Decoders
(2,048 + 64)Byte x 262,144
Data Register & S/A
Y-Gating
Command
Command
Register
CE
RE
WE
VCC
VSS
I/O Buffers & Latches
Control Logic
& High Voltage
Generator
Output
Driver
Global Buffers
I/0 0
I/0 7
CLE ALE WP
Figure 2-1. K9G4G08X0A Array Organization
1 Block = 128 Pages
(256K + 8K) Byte
1 Page = (2K + 64)Bytes
1 Block = (2K + 64)B x 128 Pages
= (256K + 8K) Bytes
1 Device = (2K+64)B x 128Pages x 2,048 Blocks
= 4,224 Mbits
256K Pages
(=2,048 Blocks)
8 bit
2K Bytes
64 Bytes
I/O 0 ~ I/O 7
Page Register
2K Bytes
64 Bytes
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
1st Cycle
A0
A1
A2
A3
A4
A5
A6
A7
2nd Cycle
A8
A9
A10
A11
*L
*L
*L
*L
Column Address
Column Address
3rd Cycle
A12
A13
A14
A15
A16
A17
A18
A19
Row Address
4th Cycle
A20
A21
A22
A23
A24
A25
A26
A27
Row Address
5th Cycle
A28
A29
*L
*L
*L
*L
*L
*L
Row Address
NOTE : Column Address : Starting Address of the Register.
* L must be set to "Low".
* The device ignores any additional input of address cycles than required.
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Preliminary
FLASH MEMORY
K9L8G08U1A
K9G4G08U0A K9G4G08B0A
Product Introduction
The K9G4G08X0A is a 4,224Mbit(4,429,185,024bit) memory organized as 262,144 rows(pages) by 2,112x8 columns. Spare 64 columns are located from column address of 2,048~2,111. A 2,112-byte data register is connected to memory cell arrays for accommodating data transfer between the I/O buffers and memory cells during page read and page program operations. The memory array is
made up of 32 cells that are serially connected to form a NAND structure. Each of the 32 cells resides in a different page. A block
consists of two NAND structured strings. A NAND structure consists of 32 cells. A cell has 2-bit data. Total 1,081,344 NAND cells
reside in a block. The program and read operations are executed on a page basis, while the erase operation is executed on a block
basis. The memory array consists of 2,048 separately erasable 256K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the K9G4G08X0A.
The K9G4G08X0A has addresses multiplexed into 8 I/Os. This scheme dramatically reduces pin counts and allows system upgrades
to future densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by
bringing WE to low while CE is low. Those are latched on the rising edge of WE. Command Latch Enable(CLE) and Address Latch
Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. Some commands require one bus cycle. For
example, Reset Command, Status Read Command, etc require just one cycle bus. Some other commands, like page read and block
erase and page program, require two cycles: one cycle for setup and the other cycle for execution. The 528M-byte physical space
requires 30 addresses, thereby requiring five cycles for addressing : 2 cycles of column address, 3 cycles of row address, in that
order. Page Read and Page Program need the same five address cycles following the required command input. In Block Erase operation, however, only three row address cycles are used. Device operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of the K9G4G08X0A.
Table 1. Command Sets
Function
Read
Two-Plane Read
1st Cycle
2nd Cycle
00h
30h
60h----60h
30h
Read ID
90h
-
Reset
FFh
-
Page Program
Two-Plane Page Program (2)
Block Erase
Two-Plane Block Erase
80h
10h
80h----11h
81h----10h
60h
D0h
60h----60h
D0h
Acceptable Command during Busy
O
85h
-
05h
E0h
00h----05h
E0h
Read Status 1
70h
-
O
Read Status 2
F1h
-
O
Random Data Input(1)
Random Data Output
(1)
Two Plane Random Data Output(3)
NOTE : 1. Random Data Input/Output can be executed in a page.
2. Any command between 11h and 81h is prohibited except 70h/F1h and FFh.
3. Two-Plane Random Data Output msut be used after Two-Plane Read operation.
Caution : Any undefined command inputs are prohibited except for above command set of Table 1.
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Preliminary
FLASH MEMORY
K9L8G08U1A
K9G4G08U0A K9G4G08B0A
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
VCC
-0.6 to + 4.6
Voltage on any pin relative to VSS
Temperature Under Bias
K9XXG08XXA-XCB0
V
VIN
-0.6 to + 4.6
VI/O
-0.6 to Vcc+0.3 (<4.6V)
-10 to +125
TBIAS
K9XXG08XXA-XIB0
Storage Temperature
Unit
°C
-40 to +125
K9XXG08XXA-XCB0
TSTG
-65 to +150
°C
Ios
5
mA
K9XXG08XXA-XIB0
Short Circuit Current
NOTE :
1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns.
Maximum DC voltage on input/output pins is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.
2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions
as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltage reference to GND, K9XXG08XXA-XCB0 :TA=0 to 70°C, K9XXG08XXA-XIB0:TA=-40 to 85°C)
Parameter
Symbol
K9G4G08U0A(3.3V)
K9G4G08B0A(2.7V)
Min
Typ.
Max
Min
Typ.
Max
Unit
Supply Voltage
VCC
2.5
2.7
2.9
2.7
3.3
3.6
V
Supply Voltage
VSS
0
0
0
0
0
0
V
DC AND OPERATING CHARACTERISTICS(Recommended operating conditions otherwise noted.)
K9G4G08X0A
Parameter
Symbol
Page Read with
Operating Serial Access
Current
Program
ICC2
Erase
ICC3
ICC1
Stand-by Current(TTL)
ISB1
Stand-by Current(CMOS)
ISB2
Test Conditions
2.7V
3.3V
Unit
Min
Typ
Max
Min
Typ
Max
-
15
30
-
15
30
-
-
15
30
-
15
30
-
-
15
30
-
15
30
-
-
1
-
-
1
-
10
50
-
10
50
tRC=50ns, CE=VIL
IOUT=0mA
CE=VIH, WP=PRE=0V/VCC
CE=VCC-0.2,
WP=PRE=0V/VCC
Input Leakage Current
ILI
VIN=0 to Vcc(max)
-
-
±10
-
-
±10
Output Leakage Current
ILO
VOUT=0 to Vcc(max)
-
-
±10
-
-
±10
Input High Voltage
VIH*
-
2.0
-
Input Low Voltage, All inputs
VIL*
-
Output High Voltage Level
VOH
Output Low Voltage Level
Output Low Current(R/B)
VOL
IOL(R/B)
VCC
-0.4
-0.3
-
0.8
-
-
2.4
-
-
-
-
0.4
-
-
0.4
3
4
-
8
10
-
-0.4
K9G4G08B0A :VOL=0.1V
K9G4G08U0A :VOL=0.4V
NOTE :
1. VIL can undershoot to -0.4V and VIH can overshoot to VCC + 0.4V for durations of 20 ns or less.
2. Typical value is measured at Vcc=2.7V/3.3V, TA=25°C. Not 100% tested.
3. The typical value of the K9L8G08U1A’s ISB2 is 20µA and the maximum value is 100µA.
10
VCC
-0.3
K9G4G08U0A :IOH=-400µA
µA
+0.3
0.5
VCC
K9G4G08U0A :IOL=2.1mA
VCC
+0.3
-
K9G4G08B0A :IOH=-100µA
K9G4G08B0A :IOL=100uA
-
mA
V
mA
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Preliminary
FLASH MEMORY
K9L8G08U1A
K9G4G08U0A K9G4G08B0A
VALID BLOCK
Parameter
Symbol
Min
Typ.
Max
Unit
K9G4G08X0A
NVB
1,998
-
2,048
Blocks
K9L8G08U1A*
NVB
3,996
-
4,096
Blocks
NOTE :
1. The device may include initial invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is
presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or program factory-marked bad blocks. Refer to the attached technical notes for appropriate management of initial invalid blocks.
2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block at the time of shipment.
3. The number of valid block is on the basis of single plane operations, and this may be decreased with two plane operations.
* : Each K9G4G08U0A chip in the K9L8G08U1A has Maximun 50 invalid blocks.
AC TEST CONDITION
(K9XXG08XXA-XCB0 :TA=0 to 70°C, K9XXG08XXA-XIB0:TA=-40 to 85°C,
K9XXG08BXA: Vcc=2.5V~2.9V, K9XXG08UXA: Vcc=2.7V~3.6V unless otherwise)
Parameter
K9G4G08B0A
K9XXG08UXA
0V to Vcc
0V to Vcc
5ns
5ns
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Levels
Output Load
Vcc/2
Vcc/2
1 TTL GATE and CL=30pF
1 TTL GATE and CL=50pF
CAPACITANCE(TA=25°C, VCC=2.7V/3.3V, f=1.0MHz)
Item
Symbol
Test Condition
Min
Max
Unit
Input/Output Capacitance
CI/O
VIL=0V
-
10
pF
Input Capacitance
CIN
VIN=0V
-
10
pF
NOTE : Capacitance is periodically sampled and not 100% tested.
MODE SELECTION
CLE
ALE
CE
RE
WP
H
L
L
WE
H
X
Mode
L
H
L
H
X
H
L
L
H
H
L
H
L
H
H
L
L
L
H
H
Data Input
L
L
L
H
X
Data Output
X
X
X
X
H
X
During Read(Busy)
X
X
X
X
X
H
During Program(Busy)
Read Mode
Command Input
Address Input(5clock)
Write Mode
Command Input
Address Input(5clock)
X
X
X
X
X
H
During Erase(Busy)
X
X(1)
X
X
X
L
Write Protect
X
X
H
X
X
0V/VCC(2)
NOTE : 1. X can be VIL or VIH.
2. WP should be biased to CMOS high or CMOS low for standby.
11
Stand-by
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Preliminary
FLASH MEMORY
K9L8G08U1A
K9G4G08U0A K9G4G08B0A
Program / Erase Characteristics
Symbol
Min
Typ
Max
Unit
Program Time
Parameter
tPROG
-
0.8
3
ms
Dummy Busy Time for Multi Plane Program
tDBSY
0.5
1
µs
Number of Partial Program Cycles in the Same Page
Nop
-
-
1
cycle
Block Erase Time
tBERS
-
1.5
10
ms
NOTE
1. Typical value is measured at Vcc=3.3V, TA=25°C. Not 100% tested.
2. Typical Program time is defined as the time within which more than 50% of the whole pages are programmed at 3.3V Vcc and 25°C temperature.
3. Within a same block, program time(tPROG) of page group A is faster than that of page group B. Typical tPROG is the average program time of the
page group A and B(Table 2).
Page Group A: Page 0, 1, 2, 3, 6, 7, 10, 11, ... , 110, 111, 114, 115, 118, 119, 122, 123
Page Group B: Page 4, 5, 8, 9, 12, 13, 16, 17, ... , 116, 117, 120, 121, 124, 125, 126, 127
AC Timing Characteristics for Command / Address / Data Input
Parameter
Symbol
Min
Max
Unit
CLS(1)
15
-
ns
CLE Hold Time
tCLH
5
-
ns
CE Setup Time
(1)
CLE Setup Time
t
20
-
ns
tCH
5
-
ns
WE Pulse Width
tWP
15
-
ns
ALE Setup Time
tALS(1)
15
-
ns
ALE Hold Time
tALH
5
-
ns
CE Hold Time
tCS
15
-
ns
Data Hold Time
tDH
5
-
ns
Write Cycle Time
tWC
30
-
ns
WE High Hold Time
tWH
10
-
ns
Data Setup Time
Address to Data Loading Time
tDS
(1)
tADL
(2)
100
(2)
NOTES : 1. The transition of the corresponding control pins must occur only once while WE is held low.
2. tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle.
12
ns
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Preliminary
FLASH MEMORY
K9L8G08U1A
K9G4G08U0A K9G4G08B0A
AC Characteristics for Operation
Parameter
Symbol
Min
Max
Unit
Data Transfer from Cell to Register
tR
-
60
µs
ALE to RE Delay
tAR
10
-
ns
CLE to RE Delay
tCLR
10
-
ns
Ready to RE Low
tRR
20
-
ns
RE Pulse Width
tRP
15
-
ns
WE High to Busy
tWB
-
100
ns
Read Cycle Time
tRC
30
-
ns
RE Access Time
tREA
-
20
ns
CE Access Time
tCEA
-
25
ns
RE High to Output Hi-Z
tRHZ
-
100
ns
CE High to Output Hi-Z
tCHZ
-
30
ns
CE High to ALE or CLE Don’t Care
tCSD
10
-
ns
RE High to Output Hold
tRHOH
15
-
ns
RE Low to Output Hold
tRLOH
5
-
ns
CE High to Output Hold
tCOH
15
-
ns
RE High Hold Time
tREH
10
-
ns
tIR
0
-
ns
RE High to WE Low
Output Hi-Z to RE Low
tRHW
100
-
ns
WE High to RE Low
tWHR
60
-
ns
Device Resetting Time(Read/Program/Erase)
tRST
-
5/10/500(1)
µs
NOTE: 1. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5µs.
13
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Preliminary
FLASH MEMORY
K9L8G08U1A
K9G4G08U0A K9G4G08B0A
NAND Flash Technical Notes
Initial Invalid Block(s)
Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by Samsung.
The information regarding the initial invalid block(s) is called the initial invalid block information. Devices with initial invalid block(s)
have the same quality level as devices with all valid blocks and have the same AC and DC characteristics. An initial invalid block(s)
does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a select transistor. The system design must be able to mask out the initial invalid block(s) via address mapping. The 1st block, which is placed on
00h block address, is guaranteed to be a valid block at the time of shipment.
Identifying Initial Invalid Block(s)
All device locations are erased(FFh) except locations where the initial invalid block(s) information is written prior to shipping. The
initial invalid block(s) status is defined by the 1st byte in the spare area. Samsung makes sure that the last page of every initial invalid
block has non-FFh data at the column address of 2,048.The initial invalid block information is also erasable in most cases, and it is
impossible to recover the information once it has been erased. Therefore, the system must be able to recognize the initial invalid
block(s) based on the initial invalid block information and create the initial invalid block table via the following suggested flow
chart(Figure 3). Any intentional erasure of the initial invalid block information is prohibited.
Start
Set Block Address = 0
Increment Block Address
*
Create (or update)
Initial
Invalid Block(s) Table
Check "FFh" at the column address
2048 of the last page in the block
No
Check "FFh" ?
Yes
No
Last Block ?
Yes
End
Figure 3. Flow chart to create initial invalid block table.
14
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Preliminary
FLASH MEMORY
K9L8G08U1A
K9G4G08U0A K9G4G08B0A
NAND Flash Technical Notes (Continued)
Error in write or read operation
Within its life time, additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual
data. Block replacement should be done upon erase or program error.
Failure Mode
Write
Read
ECC
Detection and Countermeasure sequence
Erase Failure
Status Read after Erase --> Block Replacement
Program Failure
Status Read after Program --> Block Replacement
Up to Four Bit Failure
Verify ECC -> ECC Correction
: Error Correcting Code --> RS Code etc.
Example) 4bit correction / 512-byte
Program Flow Chart
Start
Write 80h
Write Address
Write Data
Write 10h
Read Status Register
I/O 6 = 1 ?
or R/B = 1 ?
*
Program Error
No
Yes
No
I/O 0 = 0 ?
Yes
Program Completed
*
15
: If program operation results in an error, map out
the block including the page in error and copy the
target data to another block.
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Preliminary
FLASH MEMORY
K9L8G08U1A
K9G4G08U0A K9G4G08B0A
NAND Flash Technical Notes (Continued)
Erase Flow Chart
Read Flow Chart
Start
Start
Write 60h
Write 00h
Write Block Address
Write Address
Write D0h
Write 30h
Read Status Register
Read Data
ECC Generation
No
I/O 6 = 1 ?
or R/B = 1 ?
No
*
No
Erase Error
Verify ECC
Reclaim the Error
Yes
Yes
I/O 0 = 0 ?
Page Read Completed
Yes
Erase Completed
*
: If erase operation results in an error, map out
the failing block and replace it with another block.
Block Replacement
1st
∼
(n-1)th
nth
{
Block A
1
an error occurs.
(page)
1st
∼
(n-1)th
nth
Buffer memory of the controller.
{
Block B
2
(page)
* Step1
When an error happens in the nth page of the Block ’A’ during erase or program operation.
* Step2
Copy the data in the 1st ~ (n-1)th page to the same location of another free block. (Block ’B’)
* Step3
Then, copy the nth page data of the Block ’A’ in the buffer memory to the nth page of the Block ’B’.
* Step4
Do not erase or program to Block ’A’ by creating an ’invalid block’ table or other appropriate scheme.
16
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Preliminary
FLASH MEMORY
K9L8G08U1A
K9G4G08U0A K9G4G08B0A
NAND Flash Technical Notes (Continued)
Addressing for program operation
Within a block, the pages must be programmed consecutively from the LSB (least significant bit) page of the block to MSB (most significant bit) page of the block. Random page address programming is prohibited. In this case, the definition of LSB page is the LSB
among the pages to be programmed. Therefore, LSB page doesn't need to be page 0.
Page 127
(128)
Page 31
(32)
Page 127
:
:
Page 31
:
Page 2
Page 1
Page 0
(1)
:
(3)
(2)
(1)
Page 2
Page 1
Page 0
Data register
(3)
(32)
(2)
Data register
From the LSB page to MSB page
DATA IN: Data (1)
(128)
Ex.) Random page program (Prohibition)
Data (128)
DATA IN: Data (1)
17
Data (128)
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Preliminary
FLASH MEMORY
K9L8G08U1A
K9G4G08U0A K9G4G08B0A
System Interface Using CE don’t-care.
For an easier system interface, CE may be inactive during the data-loading or serial access as shown below. The internal 2,112byte
data registers are utilized as separate buffers for this operation and the system design gets more flexible. In addition, for voice or
audio applications which use slow cycle time on the order of µ-seconds, de-activating CE during the data-loading and serial access
would provide significant savings in power consumption.
Figure 4. Program Operation with CE don’t-care.
CLE
CE don’t-care
≈
≈
CE
Data Input
Data Input
WE
ALE
I/Ox
80h
Address(5Cycles)
tCS
tCH
10h
tCEA
CE
CE
tREA
tWP
RE
WE
I/O0~7
out
Figure 5. Read Operation with CE don’t-care.
CLE
CE don’t-care
≈
CE
RE
ALE
tR
R/B
WE
I/Ox
00h
Address(5Cycle)
Data Output(serial access)
30h
18
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Preliminary
FLASH MEMORY
K9L8G08U1A
K9G4G08U0A K9G4G08B0A
NOTE
Device
K9G4G08X0A
I/O
DATA
ADDRESS
I/Ox
Data In/Out
Col. Add1
Col. Add2
Row Add1
Row Add2
Row Add3
I/O 0 ~ I/O 7
~2,112byte
A0~A7
A8~A11
A12~A19
A20~A27
A28~A29
Command Latch Cycle
CLE
tCLS
tCLH
tCS
tCH
CE
tWP
WE
tALS
tALH
ALE
tDH
tDS
I/Ox
Command
Address Latch Cycle
tCLS
CLE
CE
tWC
tCS
tWC
tWC
tWP
tWP
tWC
tWP
tWP
WE
tWH
tALH
tALS
tWH
tALS
tALH
tALS
tWH
tALH
tALS
tWH
tALH
tALS
tALH
ALE
tDS
I/Ox
tDH
Col. Add1
tDS
tDH
Col. Add2
19
tDS
tDH
Row Add1
tDS
tDH
Row Add2
tDS
tDH
Row Add3
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Preliminary
FLASH MEMORY
K9L8G08U1A
K9G4G08U0A K9G4G08B0A
Input Data Latch Cycle
tCLH
≈
CLE
tCH
≈
CE
tWC
tALS
tWP
≈
≈
ALE
tWP
tWP
WE
tWH
tDH
tDS
tDH
tDS
tDH
≈
tDS
I/Ox
DIN final
DIN 1
≈
DIN 0
* Serial Access Cycle after Read(CLE=L, WE=H, ALE=L)
tRC
≈
CE
tCHZ(1)
tREH
≈
tREA
tREA
tREA
tCOH
RE
tRHZ(1)
tRHZ(1)
I/Ox
Dout
Dout
≈
tRHOH(2)
Dout
≈
tRR
R/B
NOTES : 1. Transition is measured at ±200mV from steady state voltage with load.
This parameter is sampled and not 100% tested.
2. tRHOH starts to be valid when frequency is lower than 20MHz.
20
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Preliminary
FLASH MEMORY
K9L8G08U1A
K9G4G08U0A K9G4G08B0A
Serial Access Cycle after Read(EDO Type, CLE=L, WE=H, ALE=L)
≈
CE
tRC
tREH
≈
tRP
tCHZ(1)
tCOH
RE
tREA
I/Ox
tRHOH(2)
tRLOH(2)
≈
tCEA
tRHZ(1)
tREA
Dout
≈
Dout
≈
tRR
R/B
NOTES : 1. Transition is measured at ±200mV from steady state voltage with load.
This parameter is sampled and not 100% tested.
2. tRLOH is valid when frequency is higher than 20MHz.
tRHOH starts to be valid when frequency is lower than 20MHz.
Status Read Cycle
tCLR
CLE
tCLS
tCLH
tCS
CE
tCH
tWP
WE
tCEA
tCHZ
tCOH
tWHR
RE
tDS
I/Ox
tDH
tIR
tREA
tRHZ
tRHOH
Status Output
70h/F1h
21
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Preliminary
FLASH MEMORY
K9L8G08U1A
K9G4G08U0A K9G4G08B0A
Read Operation
tCLR
CLE
CE
tWC
WE
tCSD
tWB
tAR
ALE
tR
tRHZ
tRC
≈
RE
I/Ox
00h
Col. Add1
Col. Add2
Row Add1
Column Address
Row Add2 Row Add3
30h
Dout N
Dout N+1
≈ ≈
tRR
Dout M
Row Address
Busy
R/B
Read Operation(Intercepted by CE)
tCLR
CLE
CE
tCSD
WE
tCHZ
tWB
tAR
tCOH
ALE
tRC
tR
RE
tRR
I/Ox
00h
Col. Add1
Col. Add2
Column Address
Row Add1
Row Add2 Row Add3
Dout N
30h
Row Address
Busy
R/B
22
Dout N+1
Dout N+2
23
00h
Col. Add1
Col. Add2
Column Address
Row Add2 Row Add3
Row Address
Row Add1
30h
Busy
tRR
tR
tWB
Dout N
tRC
tAR
Dout N+1
05h
tRHW
Col Add1
Col Add2
Column Address
E0h
tWHR
tCLR
Dout M
tREA
Dout M+1
K9L8G08U1A
K9G4G08U0A K9G4G08B0A
R/B
I/Ox
RE
ALE
WE
CE
CLE
Random Data Output In a Page
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Preliminary
FLASH MEMORY
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Preliminary
FLASH MEMORY
K9L8G08U1A
K9G4G08U0A K9G4G08B0A
Page Program Operation
CLE
CE
tWC
≈
tWC
tWC
WE
tWB
tADL
tPROG
tWHR
ALE
I/Ox
80h
Co.l Add1 Col. Add2
SerialData
Column Address
Input Command
Row Add1
≈ ≈
RE
Din
Din
N
M
1 up to 2112 Byte
Serial Input
Row Add2 Row Add3
Row Address
70h
I/O0=0 Successful Program
I/O0=1 Error in Program
NOTES : tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle.
24
I/O0
Read Status
Command
≈
R/B
10h
Program
Command
25
Col. Add1
Col. Add2
Row Add2 Row Add3
Row Address
Row Add1
tADL
Din
M
Serial Input
Di
Din
NN
Col. Add1
Col. Add2
tADL
Random Data Column Address
Input Command
85h
tWC
Din
K
Serial Input
Din
J
NOTES : tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle.
Serial Data
Column Address
Input Command
80h
tWC
10h
Program
Command
tWB
tPROG
70h
I/O0
I/O0=0 Successful Program
I/O0=1 Error in Program
Read Status
Command
tWHR
K9L8G08U1A
K9G4G08U0A K9G4G08B0A
R/B
I/Ox
RE
ALE
WE
tWC
≈
≈ ≈
CE
≈
≈ ≈
CLE
≈
Page Program Operation with Random Data Input
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Preliminary
FLASH MEMORY
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Preliminary
FLASH MEMORY
K9L8G08U1A
K9G4G08U0A K9G4G08B0A
Block Erase Operation
CLE
CE
tWC
WE
tBERS
tWB
tWHR
ALE
RE
I/Ox
60h
Row Add1
Row Add2 Row Add3
D0h
70h
I/O 0
Busy
R/B
Auto Block Erase
Setup Command
Erase Command
≈
Row Address
Read Status
Command
26
I/O0=0 Successful Erase
I/O0=1 Error in Erase
27
R/B
I/Ox
RE
1
00h
A0~A7
A8~A11 A12~A19 A20~A27 A28~A29
A12 ~ A18 : Fixed ’Low’
: Fixed ’Low’
A19
A20 ~ A29 : Fixed ’Low’
Row Address
A12~A19 A20~A27 A28~A29
A0 ~ A11 : Fixed ’Low’
A12 ~ A18 : Fixed ’Low’
: Fixed ’Low’
A19
A20 ~ A29 : Fixed ’Low’
Column Address Row Address
tW
tWC
60h
tW
tWC
05h
30h
A0 ~ A11
:
E0h
Valid
Column Address
A8~A11
00h
A0~A7
A8~A11 A12~A19 A20~A27 A28~A29
05h
A0~A7
A8~A11
tCLR
Dout
N
Dout
N+1
A0 ~ A11 : Fixed ’Low’
A12 ~ A18 : Fixed ’Low’
A19
: Fixed ’High’
A20 ~ A29 : Fixed ’Low’
Column Address Row Address
A0 ~ A11
:
Valid
Column Address
E0h
tREA
tRHW
Busy
tREA
tRC
tW
tWC
tR
tWHR
tWB
tWHR
tCLR
A12 ~ A18 : Valid
: Fixed ’High’
A19
A20 ~ A29 : Valid
Row Address
A12~A19 A20~A27 A28~A29
A0~A7
60h
tW
tWC
Dout
M
tRC
Dout
M+1
1
K9L8G08U1A
K9G4G08U0A K9G4G08B0A
ALE
WE
CE
CLE
R/B
I/Ox
RE
ALE
WE
CE
CLE
Two-Plane Read Operation with Two-Plane Random Data Out
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Preliminary
FLASH MEMORY
28
R/B
I/Ox
RE
ALE
WE
A0~A7
A8~A11
A20~A27 A28~A29
Din
N
Din
M
80h
A0 ~ A11 : Valid
A12 ~ A18 : Fixed ’Low’
: Fixed ’Low’
A19
A20 ~ A29: Fixed ’Low’
Address & Data Input
11h
tDBSY : typ. 500ns
max. 1µs
Note
tDBSY
81h
A8~A11
81h
A0~A7
A20~A27 A28~A29
Din
N
A0 ~ A11 :
A12 ~ A18 :
A19
:
A20 ~ A29 :
Valid
Valid
Fixed ’High’
Valid
Address & Data Input
A12~A19
Note: Any command between 11h and 81h is prohibited except 70h/F1h and FFh.
I/O0~7
tDBSY
10h
tPROG
Program Confirm
Command
(True)
10h
Din
M
tWB tPROG
I/O 0
70h/F1h
I/O0=0 Successful Program
I/O0=1 Error in Program
Read Status
Command
70h/F1h
tWHR
K9L8G08U1A
K9G4G08U0A K9G4G08B0A
R/B
11h
tWB
Program
Page Row Address 1 up to 2112 Byte Data Command
(Dummy)
Serial Input
A12~A19
≈
≈ ≈
Ex.) Two-Plane Page Program
Serial Data Column Address
Input Command
80h
tWC
≈
CE
≈
≈ ≈
CLE
≈
Two-Plane Page Program Operation
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Preliminary
FLASH MEMORY
29
Row Address
60h
tWC
I/O0~7
R/B
60h
A12 ~ A18 : Fixed ’Low’
: Fixed ’High’
A19
A20 ~ A29 : Valid
A12 ~ A18 : Fixed ’Low’
: Fixed ’Low’
A19
A20 ~ A29 : Fixed ’Low’
D0h
~ A25
A9Address
Row Add1,2,3
60h
Row Add1,2,3
Address
D0h
D0h
tWB
tBERS
Erase Confirm Command
Row Address
Row Add1 Row Add2 Row Add3
Block Erase Setup Command2
Row Add1 Row Add2 RowD0h
Add3
Block Erase Setup Command1
60h
tWC
70h/F1h
Busy
tBERS
I/O 0
Read Status Command
I/O 0 = 0 Successful Erase
I/O 0 = 1 Error in Erase
70h/F1h
tWHR
K9L8G08U1A
K9G4G08U0A K9G4G08B0A
Ex.) Address Restriction for Two-Plane Block Erase Operation
R/B
I/OX
RE
ALE
WE
CE
CLE
Two-Plane Block Erase Operation
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Preliminary
FLASH MEMORY
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Preliminary
FLASH MEMORY
K9L8G08U1A
K9G4G08U0A K9G4G08B0A
Read ID Operation
CLE
CE
WE
tAR
ALE
RE
tREA
I/Ox
00h
90h
Read ID Command
Address. 1cycle
ECh
Device
Code
3rd cyc.
4th cyc.
5th cyc.
Maker Code Device Code
Device
Device Code(2nd Cycle)
3rd Cycle
4th Cycle
5th Cycle
K9G4G08B0A
DCh
14h
25h
54h
K9G4G08U0A
DCh
14h
25h
54h
K9L8G08U1A
Same as each K9G4G08U0A in it
30
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Preliminary
FLASH MEMORY
K9L8G08U1A
K9G4G08U0A K9G4G08B0A
ID Definition Table
90 ID : Access command = 90H
Description
st
1 Byte
2nd Byte
3rd Byte
4th Byte
5th Byte
Maker Code
Device Code
Internal Chip Number, Cell Type, Number of Simultaneously Programed Pages, etc
Page Size, Block Size, Redundant Area Size, Organization, Serial Access Minimum
Plane Number, Plane Size
3rd ID Data
Description
I/O7
I/O6
I/O5 I/O4
I/O3 I/O2
I/O1 I/O0
0
0
1
1
Internal Chip Number
1
2
4
8
Cell Type
2 Level Cell
4 Level Cell
8 Level Cell
16 Level Cell
Number of
Simultaneously
Programmed Pages
1
2
4
8
Interleave Program
Between multiple chips
Not Support
Support
Cache Program
Not Support
Support
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
4th ID Data
Description
Page Size
(w/o redundant area )
1KB
2KB
4KB
8KB
Block Size
(w/o redundant area )
64KB
128KB
256KB
512KB
Redundant Area Size
( byte/512byte)
8
16
Organization
x8
x16
Serial Access Minimum
50ns/30ns
25ns
Reserved
Reserved
I/O7
I/O6
I/O5 I/O4
I/O3
I/O2
I/O1 I/O0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
31
0
0
1
1
0
1
0
1
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Preliminary
FLASH MEMORY
K9L8G08U1A
K9G4G08U0A K9G4G08B0A
5th ID Data
Description
Plane Number
1
2
4
8
Plane Size
(w/o redundant Area)
64Mb
128Mb
256Mb
512Mb
1Gb
2Gb
4Gb
8Gb
I/O7
I/O6 I/O5 I/O4
I/O3 I/O2
0
0
1
1
0
0
0
0
1
1
1
1
Reserved
0
32
0
0
1
1
0
0
1
1
I/O1
I/O0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
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Preliminary
FLASH MEMORY
K9L8G08U1A
K9G4G08U0A K9G4G08B0A
Device Operation
PAGE READ
Page read is initiated by writing 00h-30h to the command register along with five address cycles. After initial power up, 00h command
is latched. Therefore only five address cycles and 30h command initiates that operation after initial power up. The 2,112 bytes of data
within the selected page are transferred to the data registers in less than 60µs(tR). The system controller can detect the completion of
this data transfer(tR) by analyzing the output of R/B pin. Once the data in a page is loaded into the data registers, they may be read
out in 30ns cycle time by sequentially pulsing RE. The repetitive high to low transitions of the RE clock make the device output the
data starting from the selected column address up to the last column address.
The device may output random data in a page instead of the consecutive sequential data by writing random data output command.
The column address of next data, which is going to be out, may be changed to the address which follows random data output command. Random data output can be operated multiple times regardless of how many times it is done in a page.
Figure 6. Read Operation
CLE
CE
WE
ALE
tR
R/B
RE
I/Ox
00h
Address(5Cycle)
Data Output(Serial Access)
30h
Col Add1,2 & Row Add1,2,3
Data Field
Spare Field
33
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Preliminary
FLASH MEMORY
K9L8G08U1A
K9G4G08U0A K9G4G08B0A
Figure 7. Random Data Output In a Page
tR
R/B
RE
I/Ox
Address
5Cycles
00h
Data Output
30h
05h
Address
2Cycles
E0h
Data Output
Col Add1,2 & Row Add1,2,3
Data Field
Data Field
Spare Field
Spare Field
PAGE PROGRAM
The device is programmed basically on a page basis, and the number of consecutive partial page programming operation within the
same page without an intervening erase operation must not exceed 1 time for the page. The addressing should be done in sequential
order in a block. A page program cycle consists of a serial data loading period in which up to 2,112bytes of data may be loaded into
the data register, followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell.
The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the five cycle address inputs and
then serial data loading. The data other than those to be programmed do not need to be loaded. The device supports random data
input in a page. The column address for the next data, which will be entered, may be changed to the address which follows random
data input command(85h). Random data input may be operated multiple times regardless of how many times it is done in a page.
The Page Program confirm command(10h) initiates the programming process. Writing 10h alone without previously entering the
serial data will not initiate the programming process. The internal write state controller automatically executes the algorithms and timings necessary for program and verify, thereby freeing the system controller for other tasks. Once the program process starts, the
Read Status Register command may be entered to read the status register. The system controller can detect the completion of a program cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset
command are valid while programming is in progress. When the Page Program is complete, the Write Status Bit(I/O 0) may be
checked(Figure 8). The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command
register remains in Read Status command mode until another valid command is written to the command register.
Figure 8. Program & Read Status Operation
tPROG
R/B
"0"
I/Ox
80h
Address & Data Input
10h
70h
Pass
I/O0
Col Add1,2 & Row Add1,2,3
"1"
Data
Fail
34
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Preliminary
FLASH MEMORY
K9L8G08U1A
K9G4G08U0A K9G4G08B0A
Figure 9. Random Data Input In a Page
tPROG
R/B
"0"
I/Ox
Address & Data Input
80h
85h
Address & Data Input
10h
70h
Col Add1,2
Data
Col Add1,2 & Row Add1,2,3
Data
Pass
I/O0
"1"
Fail
Table 2. Paired Page Address Information
Paired Page Address
Paired Page Address
00h
04h
01h
05h
02h
08h
03h
09h
06h
0Ch
07h
0Dh
0Ah
10h
0Bh
11h
0Eh
14h
0Fh
15h
12h
18h
13h
19h
16h
1Ch
17h
1Dh
1Ah
20h
1Bh
21h
1Eh
24h
1Fh
25h
22h
28h
23h
29h
26h
2Ch
27h
2Dh
2Ah
30h
2Bh
31h
2Eh
34h
2Fh
35h
32h
38h
33h
39h
36h
3Ch
37h
3Dh
3Ah
40h
3Bh
41h
3Eh
44h
3Fh
45h
42h
48h
43h
49h
46h
4Ch
47h
4Dh
4Ah
50h
4Bh
51h
4Eh
54h
4Fh
55h
52h
58h
53h
59h
56h
5Ch
57h
5Dh
5Ah
60h
5Bh
61h
5Eh
64h
5Fh
65h
62h
68h
63h
69h
66h
6Ch
67h
6Dh
6Ah
70h
6Bh
71h
6Eh
74h
6Fh
75h
72h
78h
73h
79h
76h
7Ch
77h
7Dh
7Ah
7Eh
7Bh
7Fh
Note: When program operation is abnormally aborted (ex. power-down), not only page data under program but also paired
page data may be damaged(Table 2).
35
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Preliminary
FLASH MEMORY
K9L8G08U1A
K9G4G08U0A K9G4G08B0A
BLOCK ERASE
The Erase operation is done on a block basis. Block address loading is accomplished in three cycles initiated by an Erase Setup
command(60h). Only address A19 to A29 is valid while A12 to A18 is ignored. The Erase Confirm command(D0h) following the block
address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that
memory contents are not accidentally erased due to external noise conditions.
At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-verify. When
the erase operation is completed, the Write Status Bit(I/O 0) may be checked. Figure 10 details the sequence.
Figure 10. Block Erase Operation
tBERS
R/B
"0"
60h
I/Ox
Address Input(3Cycle)
Pass
I/O0
70h
D0h
"1"
Row Add. : A12 ~ A29
Fail
Two-Plane Read
Two-Plane Read is an extension of Read, for a single plane with 2,112 byte page registers. Since the device is equipped with two
memory planes, activating the two sets of 2,112 byte page registers enables a random read of two pages. Two-Plane Read is initiated by repeating command 60h followed by three address cycles twice. In this case only same page of same block can be selected
from each plane.
After Read Confirm command(30h) the 4,224 bytes of data within the selected two page are transferred to the data registers in less
than 60us(tR). The system controller can detect the completion of data transfer(tR) by monitoring the output of R/B pin.
Once the data is loaded into the data registers, the data output of first plane can be read out by issuing command 00h with Five
Address Cycles, command 05h with two column address and finally E0h. The data output of second plane can be read out using the
identical command sequences. The restrictions in addressing with Two-Plane Read are shown in Figure 11. Two-Plane Read must
be used in the block which has been programmed with Two-Plane Page Program.
Figure 11. Two-Plane Page Read Operation with Two-Plane Random Data Out
tR
R/B
I/OX
60h
Address (3 Cycle)
60h
Row Add.1,2,3
A12 ~ A18 : Fixed ’Low’
: Fixed ’Low’
A19
A20 ~ A29 : Fixed ’Low’
30h
Address (3 Cycle)
Row Add.1,2,3
A12 ~ A18 : Valid
: Fixed ’High’
A19
A20 ~ A29 : Valid
1
R/B
I/Ox
00h
Address (5 Cycle)
05h
Col. Add. 1,2 & Row Add.1,2,3
A0 ~ A11 : Fixed ’Low’
A12 ~ A18 : Fixed ’Low’
: Fixed ’Low’
A19
A20 ~ A29 : Fixed ’Low’
1
Address (2 Cycle)
E0h
Data Output
Col. Add.1,2
A0 ~ A11
:
Valid
2
R/B
I/Ox
00h
Address (5 Cycle)
05h
Col. Add. 1,2 & Row Add.1,2,3
2
A0 ~ A11 : Fixed ’Low’
A12 ~ A18 : Fixed ’Low’
: Fixed ’High’
A19
A20 ~ A29 : Fixed ’Low’
Address (2 Cycle)
Col. Add.1,2
A0 ~ A11
36
:
Valid
E0h
Data Output
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Preliminary
FLASH MEMORY
K9L8G08U1A
K9G4G08U0A K9G4G08B0A
Two-Plane Page Program
Two-Plane Page Program is an extension of Page Program, for a single plane with 2112 byte page registers. Since the device is
equipped with two memory planes, activating the two sets of 2112 byte page registers enables a simultaneous programming of two
pages.
After writing the first set of data up to 2112 byte into the selected page register, Dummy Page Program command (11h) instead of
actual Page Program command(10h) is inputted to finish data-loading of the first plane. Since no programming process is involved,
R/B remains in Busy state for a short period of time(tDBSY). Read Status command (70h) may be issued to find out when the device
returns to Ready state by polling the Ready/Busy status bit(I/O 6). Then the next set of data for the other plane is inputted after the
81h command and address sequences. After inputting data for the last plane, actual True Page Program command(10h) instead of
dummy Page Program command (11h) must be followed to start the programming process. The operation of R/B and Read Status is
the same as that of Page Program. Status bit of I/O 0 is set to "1" when any of the pages fails. Restriction in addressing with TwoPlane Page Program is shown in Figure12.
Figure 12. Two-Plane Page Program
tDBSY
R/B
I/O0 ~ 7
80h
Address & Data Input
11h
tPROG
81h
Address & Data Input
"0"
10h
70h/F1h
I/O0
Note2
A0 ~ A11 : Valid
A12 ~ A18 : Fixed ’Low’
: Fixed ’Low’
A19
A20 ~ A29: Fixed ’Low’
A0 ~ A11 :
A12 ~ A18 :
:
A19
A20 ~ A29 :
Valid
Valid
Fixed ’High’
Valid
NOTE : 1. It is noticeable that physically same row address is applied to two planes .
2. Any command between 11h and 81h is prohibited except 70h/F1h and FFh.
Data
Input
80h
11h
81h
10h
Plane 0
(1024 Block)
Plane 1
(1024 Block)
Block 0
Block 1
Block 2
Block 3
Block 2044
Block 2046
Block 2045
Block 2047
37
"1"
Fail
Pass
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Preliminary
FLASH MEMORY
K9L8G08U1A
K9G4G08U0A K9G4G08B0A
Two-Plane Block Erase
Basic concept of Two-Plane Block Erase operation is identical to that of Two-Plane Page Program. Up to two blocks, one from each
plane can be simultaneously erased. Standard Block Erase command sequences (Block Erase Setup command(60h) followed by
three address cycles) may be repeated up to twice for erasing up to two blocks. Only one block should be selected from each plane.
The Erase Confirm command(D0h) initiates the actual erasing process. The completion is detected by monitoring R/B pin or Ready/
Busy status bit (I/O 6).
Figure 13. Two-Plane Erase Operation
tBERS
R/B
I/OX
60h
Address (3 Cycle)
A12 ~ A18 : Fixed ’Low’
: Fixed ’Low’
A19
A20 ~ A29 : Fixed ’Low’
60h
Address (3 Cycle)
A12 ~ A18 : Fixed ’Low’
: Fixed ’High’
A19
A20 ~ A29 : Valid
38
D0h
70h/F1h
"0"
I/O0
"1"
Fail
Pass
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Preliminary
FLASH MEMORY
K9L8G08U1A
K9G4G08U0A K9G4G08B0A
READ STATUS
The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether
the program or erase operation is completed successfully. After writing 70h or F1h command to the command register, a read cycle
outputs the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control
allows the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or
CE does not need to be toggled for updated status. Refer to Table 3 for specific 70h Status Register definitions and Table 4 for for
specific F1h Status Register definitions. The command register remains in Status Read mode until further commands are issued to it.
Therefore, if the status register is read during a random read cycle, the read command(00h) should be given before starting read
cycles.
Table 3. 70h Read Status Register Definition
I/O No.
Page Program
Block Erase
Read
Definition
I/O 0
Pass/Fail
Pass/Fail
Not use
Pass : "0"
I/O 1
Not use
Not use
Not use
Don’t -cared
I/O 2
Not use
Not use
Not use
Don’t -cared
I/O 3
Not Use
Not Use
Not Use
Don’t -cared
I/O 4
Not Use
Not Use
Not Use
Don’t -cared
I/O 5
Not Use
Not Use
Not Use
I/O 6
Ready/Busy
Ready/Busy
Ready/Busy
Busy : "0"
I/O 7
Write Protect
Write Protect
Write Protect
Protected : "0"
Fail : "1"
Don’t -cared
Ready : "1"
Not Protected : "1"
NOTE : 1. I/Os defined ’Not use’ are recommended to be masked out when Read Status is being executed.
Table 4. F1h Read Status Register Definition
I/O No.
Page Program
Block Erase
Read
Definition
I/O 0
Chip Pass/Fail
Chip Pass/Fail
Not use
Pass : "0"
Fail : "1"
I/O 1
Plane0 Pass/Fail
Plane0 Pass/Fail
Not use
Pass : "0"
Fail : "1"
I/O 2
Plane1 Pass/Fail
Plane1 Pass/Fail
Not use
Pass : "0"
Fail : "1"
I/O 3
Not Use
Not Use
Not Use
Don’t -cared
I/O 4
Not Use
Not Use
Not Use
Don’t -cared
I/O 5
Not Use
Not Use
Not Use
Don’t -cared
I/O 6
Ready/Busy
Ready/Busy
Ready/Busy
Busy : "0"
I/O 7
Write Protect
Write Protect
Write Protect
Protected : "0"
NOTE : 1. I/Os defined ’Not use’ are recommended to be masked out when Read Status is being executed.
39
Ready : "1"
Not Protected : "1"
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Preliminary
FLASH MEMORY
K9L8G08U1A
K9G4G08U0A K9G4G08B0A
Read ID
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of
00h. Five read cycles sequentially output the manufacturer code(ECh), and the device code and 3rd cycle ID, 4th cycle ID, 5th cycle
ID respectively. The command register remains in Read ID mode until further commands are issued to it. Figure 14 shows the operation sequence.
Figure 14. Read ID Operation
tCLR
CLE
tCEA
CE
WE
tAR
ALE
RE
tWHR
I/OX
90h
00h
tREA
ECh
Address. 1cycle
Maker code
Device
Code
3rd Cyc.
4th Cyc.
5th Cyc.
Device code
Device
Device Code(2nd Cycle)
3rd Cycle
4th Cycle
5th Cycle
K9G4G08B0A
DCh
14h
25h
54h
K9G4G08U0A
DCh
14h
25h
54h
K9L8G08U1A
Same as each K9G4G08X0A in it
RESET
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random
read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no
longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and
the Status Register is cleared to value C0h when WP is high. Refer to Table 5 for device status after reset operation. If the device is
already in reset state a new reset command will be accepted by the command register. The R/B pin changes to low for tRST after the
Reset command is written. Refer to Figure 15 below.
Figure 15. RESET Operation
tRST
R/B
I/OX
FFh
Table 5. Device Status
Operation mode
After Power-up
After Reset
00h Command is latched
Waiting for next command
40
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Preliminary
FLASH MEMORY
K9L8G08U1A
K9G4G08U0A K9G4G08B0A
READY/BUSY
The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random
read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command register or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin is
an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. Because pull-up resistor value is related to tr(R/B) and
current drain during busy(ibusy) , an appropriate value can be obtained with the following reference chart(Fig 16). Its value can be
determined by the following guidance.
Rp
VCC
ibusy
Ready Vcc
2.7V device - VOL : 0.4V, VOH : Vcc-0.4V
3.3V device - VOL : 0.4V, VOH : 2.4V
R/B
open drain output
VOH
CL
VOL
Busy
tf
GND
Device
41
tr
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Preliminary
FLASH MEMORY
K9L8G08U1A
K9G4G08U0A K9G4G08B0A
Figure 16. Rp vs tr ,tf & Rp vs ibusy
@ Vcc = 2.7V, Ta = 25°C , CL = 30pF
2.3
Ibusy
2m
1.1
Ibusy [A]
tr,tf [s]
200n
120
90
100n
tr
30
2.3
60
0.75
2.3
2.3
2K
3K
Rp(ohm)
4K
2.3
tf
1K
1m
0.55
@ Vcc = 3.3V, Ta = 25°C , CL = 50pF
2.4
200
tr,tf [s]
2m
Ibusy [A]
Ibusy
200n
150
1.2
100
100n
0.6
50
3.6
tf
1K
1m
0.8
tr
3.6
3.6
2K
3K
Rp(ohm)
4K
3.6
Rp value guidance
Rp(min, 2.7V part) =
Rp(min, 3.3V part) =
2.4V
VCC(Max.) - VOL(Max.)
IOL + ΣIL
=
3.2V
VCC(Max.) - VOL(Max.)
IOL + ΣIL
3mA + ΣIL
=
8mA + ΣIL
where IL is the sum of the input currents of all devices tied to the R/B pin.
Rp(max) is determined by maximum permissible limit of tr
42
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Preliminary
FLASH MEMORY
K9L8G08U1A
K9G4G08U0A K9G4G08B0A
Data Protection & Power up sequence
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector
disables all functions whenever Vcc is below about 1.8V(2.7V device), 2V(3.3V device). WP pin provides hardware protection and is
recommended to be kept at VIL during power-up and power-down. A recovery time of minimum 100µs is required before internal circuit gets ready for any command sequences as shown in Figure 17. The two step command sequence for program/erase provides
additional software protection.
≈
Figure 17. AC Waveforms for Power Transition
2.7V device : ~ 2.0V
3.3V device : ~ 2.5V
High
≈
VCC
WE
100µs
≈
≈
WP
43
2.7V device : ~ 2.0V
3.3V device : ~ 2.5V
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Preliminary
FLASH MEMORY
K9L8G08U1A
K9G4G08U0A K9G4G08B0A
nWP AC Timing guide
Enabling nWP during erase and program busy is progibited.
The erase and program operations are enabled and disabled as follows:
Figure 18. Program Operation
≈
1. Enable Mode
nWE
80h
I/O
10h
nWP
RnB
tww(min.100ns)
≈
2. Disable Mode
nWE
80h
I/O
10h
nWP
RnB
tww(min.100ns)
Figure 19. Erase Operation
≈
1. Enable Mode
nWE
60h
I/O
D0h
nWP
RnB
tww(min.100ns)
≈
2. Disable Mode
nWE
60h
I/O
D0h
nWP
RnB
tww(min.100ns)
44