PRELIMINARY CMOS SRAM KM641001A Document Title 256Kx 4 High Speed Static RAM(5V Operating), Evolutionary Pin Out. Operated at Commercial Temperature Range. Revision History Rev. No. History Draft Data Rev. 0.0 Initial release with Design Target. Jan. 18th, 1995 Design Target Rev. 1.0 Release to Preliminary Data Sheet. 1.1. Replace Design Target to Preliminary Apr. 22th, 1995 Preliminary Rev. 2.0 Release to final Data Sheet. 2.1. Delete Preliminary Feb. 29th, 1996 Final Rev. 3.0 Update D.C and A.C parameters. 3.1. Update D.C parameters Previous spec. Items (15/17/20ns part) Icc 190/180/170mA Isb 30mA Isb1 10mA 3.2. Update A.C parameters Previous spec. Items (15/17/20ns part) tCW 12/12/13ns tAW 12/12/13ns tWP1(OE=H) 12/12/13ns tDW 8/9/10ns Jul. 16th, 1996 Final Remark Updated spec. (15/17/20ns part) 145/145/140mA 25mA 8mA Updated spec. (15/17/20ns part) 10/11/12ns 10/11/12ns 10/11/12ns 7/8/9ns Rev. 4.0 Update D.C and A.C parameters 4.1. Update D.C and A.C parameters. Previous spec. Updated spec. Items (15/17/20ns part) (15/17/20ns part) Icc 145/145/140mA 125/125/120mA tOW 3/4/5ns 3/3/3ns 4.2. Add the test condition for VOH1 with VCC=5V±5% at 25°C 4.3. Add timing diagram to define tWP as ″(Timing Wave Form of Write Cycle(CS=Controlled)″ Jun. 2nd, 1997 Final Rev. 5.0 5.1. Delete 17ns Part Feb. 25th, 1998 Final The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters. -1- Rev 5.0 February 1998 PRELIMINARY CMOS SRAM KM641001A 256K x 4 Bit (with OE)High-Speed CMOS Static RAM FEATURES GENERAL DESCRIPTION • Fast Access Time 15, 20ns(Max.) • Low Power Dissipation Standby (TTL) : 25mA(Max.) (CMOS) : 8mA(Max.) Operating KM641001A - 15 : 125mA(Max.) KM641001A - 20 : 120mA(Max.) • Single 5.0V±10% Power Supply • TTL Compatible Inputs and Outputs • I/O Compatible with 3.3V Device • Fully Static Operation - No Clock or Refresh required • Three State Outputs • Standard Pin Configuration KM641001AJ : 28-SOJ-400A The KM641001A is a 1,048,576-bit high-speed Static Random Access Memory organized as 262,144 words by 4 bits. The KM641001A uses 4 common input and output lines and has an output enable pin which operates faster than address access time at read cycle. The device is fabricated using SAMSUNG′s advanced CMOS process and designed for high-speed circuit technology. It is particularly well suited for use in high-density high-speed system applications. The KM641001A is packaged in a 400 mil 28-pin plastic SOJ. PIN CONFIGURATION(Top View) FUNCTIONAL BLOCK DIAGRAM A2 A3 A4 A5 A6 A7 A8 A9 A10 I/O1 ~ I/O4 Pre-Charge Circuit Row Select Clk Gen. Memory Array 512 Rows 512x4 Columns Data Cont. A0 1 28 Vcc A1 2 27 A17 A2 3 26 A16 A3 4 25 A15 A4 5 24 A14 A5 6 23 A13 A6 7 A7 8 21 A11 A8 9 20 N.C 22 A12 SOJ A9 10 19 I/O4 A10 11 18 I/O3 CS 12 17 I/O2 OE 13 16 I/O1 Vss 14 15 WE I/O Circuit & Column Select CLK Gen. PIN FUNCTION A1 A0 A12 A11 A14 A13 A16 A15 A17 Pin Name A0 - A17 Pin Function Address Inputs CS WE Write Enable WE CS Chip Select OE Output Enable OE I/O1 ~ I/O 4 -2- Data Inputs/Outputs VCC Power(+5.0V) VSS Ground N.C No Connection Rev 5.0 February 1998 PRELIMINARY CMOS SRAM KM641001A ABSOLUTE MAXIMUM RATINGS* Parameter Voltage on Any Pin Relative to V SS Symbol Rating Unit VIN, VOUT -0.5 to 7.0 V VCC -0.5 to 7.0 V Voltage on VCC Supply Relative to VSS Power Dissipation Storage Temperature Operating Temperature PD 1.0 W TSTG -65 to 150 °C TA 0 to 70 °C * Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. RECOMMENDED DC OPERATING CONDITIONS(TA=0 to 70°C) Symbol Min Typ Max Unit Supply Voltage Parameter VCC 4.5 5.0 5.5 V Ground VSS 0 0 0 V Input High Voltage VIH 2.2 - VCC + 0.5** V Input Low Voltage VIL -0.5* - 0.8 V * VIL (Min)=-2.0V a.c(Pulse Width ≤ 10ns) for I ≤ 20mA ** VIH(Max)=VCC + 2.0V a.c (Pulse Width ≤ 10ns) for I ≤ 20mA DC AND OPERATING CHARACTERISTICS(TA=0 to 70°C, Vcc=5.0V±10%, unless otherwise specified) Parameter Symbol Test Conditions Min Max Unit Input Leakage Current ILI VIN = VSS to VCC -2 2 µA Output Leakage Current ILO CS=VIH or OE=VIH or WE=VIL VOUT=VSS to VCC -2 2 µA Operating Current ICC Min. Cycle, 100% Duty CS=VIL, VIN = VIH or VIL, IOUT=0mA 15ns - 125 mA 20ns - 120 Standby Current ISB Min. Cycle, CS=VIH - 25 mA ISB1 f=0MHz, CS≥VCC-0.2V, VIN≥VCC-0.2V or VIN≤ 0.2V - 8 mA VOL IOL=8mA - 0.4 V VOH IOH=-4mA 2.4 - V - 3.95 V Output Low Voltage Level Output High Voltage Level VOH1* IOH1=-0.1mA * VCC=5.0V, Temp =25°C CAPACITANCE*(TA=25°C, f=1.0MHz) Item Symbol Test Conditions MIN Max Unit Input/Output Capacitance CI/O VI/O=0V - 8 pF Input Capacitance CIN VIN=0V - 6 pF * NOTE : Capacitance is sampled and not 100% tested. -3- Rev 5.0 February 1998 PRELIMINARY CMOS SRAM KM641001A AC CHARACTERISTICS (TA=0 to 70°C, VCC=5.0V±10%, unless otherwise noted.) TEST CONDITIONS Parameter Value Input Pulse Levels 0V to 3V Input Rise and Fall Times 3ns Input and Output timing Reference Levels 1.5V Output Loads See below Output Loads(A) Output Loads(B) for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ +5.0V +5.0V 480Ω 480Ω DOUT 255Ω DOUT 255Ω 30pF* 5pF* * Including Scope and Jig Capacitance READ CYCLE Parameter Symbol KM641001A-15 Min KM641001A-20 Max Min Max Unit Read Cycle Time tRC 15 - 20 - ns Address Access Time tAA - 15 - 20 ns Chip Select to Output tCO - 15 - 20 ns Output Enable to Valid Output tOE - 8 - 10 ns tLZ 3 - 3 - ns tOLZ 0 - 0 - ns Chip Enable to Low-Z Output Output Enable to Low-Z Output Chip Disable to High-Z Output tHZ 0 6 0 8 ns Output Disable to High-Z Output tOHZ 0 6 0 8 ns Output Hold from Address Change tOH 3 - 3 - ns Chip Selection to Power Up Time tPU 0 - 0 - ns Chip Selection to Power DownTime tPD - 15 - 20 ns -4- Rev 5.0 February 1998 PRELIMINARY CMOS SRAM KM641001A WRITE CYCLE Parameter KM641001A-15 Symbol KM641001A-20 Min Max Min Max Unit Write Cycle Time tWC 15 - 20 - ns Chip Select to End of Write tCW 10 - 12 - ns Address Set-up Time tAS 0 - 0 - ns Address Valid to End of Write tAW 10 - 12 - ns Write Pulse Width(OE High) tWP 10 - 12 - ns Write Pulse Width(OE Low) tWP1 15 - 20 - ns Write Recovery Time tWR 0 - 0 - ns Write to Output High-Z tWHZ 0 8 0 10 ns Data to Write Time Overlap tDW 7 - 9 - ns Data Hold from Write Time tDH 0 - 0 - ns End Write to Output Low-Z tOW 3 - 3 - ns TIMMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL , WE=VIH) tRC Address tAA tOH Data Out Valid Data Previous Valid Data TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH) tRC Address tAA tCO CS tHZ(3,4,5) tOHZ tOE OE tOH tOLZ tLZ(4,5) Data out Valid Data VCC ICC Current ISB tPU tPD 50% 50% -5- Rev 5.0 February 1998 PRELIMINARY CMOS SRAM KM641001A NOTES(READ CYCLE) 1. WE is high for read cycle. 2. All read cycle timing is referenced from the last valid address to the first transition address. 3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or VOL levels. 4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device. 5. Transition is measured ±200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested. 6. Device is continuously selected with CS=VIL. 7. Address valid prior to coincident with CS transition low. 8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. TIMING WAVEFORM OF WRITE CYCLE(1) (OE= Clock) tWC Address tWR(5) tAW OE tCW(3) CS tWP(2) tAS(4) WE tDW Data in High-Z tDH Valid Data tOHZ(6) High-Z(8) Data out TIMING WAVEFORM OF WRITE CYCLE(2) (OE=Low Fixed) tWC Address tAW tWR(5) tCW(3) CS tAS(4) tWP1(2) WE tDW Data in High-Z tDH Valid Data tWHZ(6) tOW High-Z(8) Data out -6- (10) (9) Rev 5.0 February 1998 PRELIMINARY CMOS SRAM KM641001A TIMING WAVEFORM OF WRITE CYCLE(3) (CS=Controlled) tWC Address tAW tWR(5) tCW(3) CS tWP(2) tAS(4) WE tDW High-Z Data in Valid Data tLZ High-Z tWHZ(6) High-Z(8) High-Z Data out tDH NOTES(WRITE CYCLE) 1. All write cycle timing is referenced from the last valid address to the first transition address. 2. A write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low ; A write ends at the earliest transition CS going high or WE going high. tWP is measured from the beginning of write to the end of write. 3. tCW is measured from the later of CS going low to end of write. 4. tAS is measured from the address valid to the beginning of write. 5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high. 6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state. 9. Dout is the read data of the new address. 10.When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied. FUNCTIONAL DESCRIPTION CS WE OE Mode I/O Pin Supply Current H X L H X* Not Select High-Z ISB, ISB1 H Output Disable High-Z ICC L L H L Read DOUT ICC L X Write DIN ICC * NOTE : X means Don′t Care. -7- Rev 5.0 February 1998 PRELIMINARY CMOS SRAM KM641001A PACKAGE DIMENSIONS Units:millimeters/Inches 28-SOJ-400A #15 10.16 0.400 #28 11.18 ±0.12 0.440 ±0.005 9.40 ±0.25 0.370 ±0.010 0.20 #1 18.82 MAX 0.741 0.69 MIN 0.027 18.41 ±0.12 0.725 ±0.005 ( 1.27 ) 0.050 3.76 MAX 1.32 ( ) 0.148 0.052 0.43 ( 0.95 ) 0.0375 +0.10 -0.05 0.008 +0.10 -0.002 #14 0.10 0.004 MAX +0.10 -0.05 0.017 +0.004 -0.002 1.27 0.050 0.71 +0.10 -0.05 0.028+0.004 -0.002 -8- Rev 5.0 February 1998