SCLS072D − NOVEMBER 1988 − REVISED SEPTEMBER 2003
D Operating Voltage Range of 4.5 V to 5.5 V
D High-Current 3-State Outputs Interface
Directly With System Bus
D Typical tpd = 17 ns
D Low Power Consumption, 80-µA Max ICC
D ±6-mA Output Drive at 5 V
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
1A
A/B
NC
VCC
OE
VCC
OE
4A
4B
4Y
3A
3B
3Y
1B
1Y
NC
2A
2B
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
4A
4B
NC
4Y
3A
2Y
GND
NC
3Y
3B
1
D
Sources in High-Performance Systems
Buffered Inputs and Outputs
SN54HCT257 . . . FK PACKAGE
(TOP VIEW)
SN54HCT257 . . . J PACKAGE
SN74HCT257 . . . D OR N PACKAGE
(TOP VIEW)
A/B
1A
1B
1Y
2A
2B
2Y
GND
D Low Input Current of 1 µA Max
D Inputs Are TTL-Voltage Compatible
D Provide Bus Interface From Multiple
NC − No internal connection
description/ordering information
The ’HCT257 devices are designed to multiplex signals from 4-bit data sources to 4-output data lines in
bus-organized systems. The 3-state outputs do not load the data lines when the output-enable (OE) input is at
the high logic level.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
PACKAGE†
TA
PDIP − N
−40°C to 85°C
SOIC − D
CDIP − J
ORDERABLE
PART NUMBER
Tube of 25
SN74HCT257N
Tube of 40
SN74HCT257D
Reel of 2500
SN74HCT257DR
Reel of 250
SN74HCT257DT
Tube of 25
SNJ54HCT257J
TOP-SIDE
MARKING
SN74HCT257N
HCT257
SNJ54HCT257J
−55°C to 125°C
LCCC − FK
Tube of 55
SNJ54HCT257FK
SNJ54HCT257FK
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
!"#$%&' #"'(' ')"*%("' #$**&' ( ") +$,-#("' !(&. *"!$# #"')"*% "
+&#)#("' +&* & &*% ") &/( '*$%&' ('!(*! 0(**('1.
*"!$#"' +*"#&'2 !"& '" '&#&(*-1 '#-$!& &'2 ") (-+(*(%&&*.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SCLS072D − NOVEMBER 1988 − REVISED SEPTEMBER 2003
FUNCTION TABLE
INPUTS
OUTPUT
Y
DATA
OE
SELECT
A/B
A
B
H
X
X
X
Z
L
L
L
X
L
L
L
H
X
H
L
H
X
L
L
L
H
X
H
H
logic diagram (positive logic)
OE
A/B
1A
1B
2A
2B
3A
3B
4A
4B
15
1
2
4
3
5
7
2Y
6
11
9
3Y
10
14
12
13
Pin numbers shown are for the D, J, and N packages.
2
1Y
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
4Y
SCLS072D − NOVEMBER 1988 − REVISED SEPTEMBER 2003
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±70 mA
Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
SN54HCT257
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.5
5
5.5
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
Input voltage
0
VO
tt
Output voltage
0
High-level input voltage
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
SN74HCT257
2
2
Input transition (rise and fall) time
V
V
0.8
VCC
VCC
UNIT
0
0
500
0.8
V
VCC
VCC
V
500
ns
V
TA
Operating free-air temperature
−55
125
−40
85
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
VOH
VI = VIH or VIL
IOH = −20 µA
IOH = −6 mA
4.5 V
VOL
VI = VIH or VIL
IOL = 20 µA
IOL = 6 mA
4.5 V
II
IOZ
VI = VCC or 0
VO = VCC or 0,
ICC
∆ICC‡
VI = VIH or VIL
VI = VCC or 0,
IO = 0
One input at 0.5 V or 2.4 V,
Other inputs at 0 or VCC
Ci
TA = 25°C
MIN
TYP
MAX
SN54HCT257
MIN
MAX
SN74HCT257
MIN
4.4
4.499
4.4
4.4
3.98
4.3
3.7
3.84
MAX
UNIT
V
0.001
0.1
0.1
0.1
0.17
0.26
0.4
0.33
5.5 V
±0.1
±100
±1000
±1000
nA
5.5 V
±0.01
±0.5
±10
±5
µA
8
160
80
µA
1.4
2.4
3
2.9
mA
3
10
10*
10
pF
5.5 V
5.5 V
4.5 V
to 5.5 V
V
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
‡ This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC.
3 ')"*%("' #"'#&*' +*"!$# ' & )"*%(4& "*
!&2' +(& ") !&4&-"+%&'. (*(#&*# !(( ('! "&*
+&#)#("' (*& !&2' 2"(-. &/( '*$%&' *&&*4& & *2 "
#('2& "* !#"''$& && +*"!$# 0"$ '"#&.
POST OFFICE BOX 655303
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3
SCLS072D − NOVEMBER 1988 − REVISED SEPTEMBER 2003
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
A or B
Y
tpd
Y
A/B
ten
OE
Y
tdis
OE
Y
tt
Any
VCC
MIN
TA = 25°C
TYP
MAX
SN54HCT257
MIN
MAX
SN74HCT257
MIN
MAX
4.5 V
20
30
45
38
5.5 V
17
27
40
34
4.5 V
20
30
45
38
5.5 V
17
27
40
34
4.5 V
20
30
45
38
5.5 V
17
27
40
34
4.5 V
20
30
45
38
5.5 V
17
27
40
34
4.5 V
8
15
22
19
5.5 V
7
14
21
17
UNIT
ns
ns
ns
ns
switching characteristics over recommended operating free-air temperature range, CL = 150 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
A or B
Y
tpd
ten
A/B
Y
OE
Y
tt
Any
VCC
MIN
TA = 25°C
TYP
MAX
SN54HCT257
MIN
MAX
SN74HCT257
MIN
MAX
4.5 V
22
38
57
48
5.5 V
19
35
53
44
4.5 V
22
38
57
48
5.5 V
19
35
53
44
4.5 V
23
40
60
50
5.5 V
20
38
57
48
4.5 V
17
42
63
53
5.5 V
14
38
57
48
UNIT
ns
ns
ns
operating characteristics, TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance
No load
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!&2' +(& ") !&4&-"+%&'. (*(#&*# !(( ('! "&*
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#('2& "* !#"''$& && +*"!$# 0"$ '"#&.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TYP
13
UNIT
pF
SCLS072D − NOVEMBER 1988 − REVISED SEPTEMBER 2003
PARAMETER MEASUREMENT INFORMATION
VCC
From Output
Under Test
CL
(see Note A)
PARAMETER
S1
Test
Point
tPZH
ten
RL
S2
1 kΩ
tPZL
tPHZ
tdis
3V
1.3 V
0V
tPLH
In-Phase
Output
1.3 V
10%
tPHL
90%
90%
tr
tPHL
Out-ofPhase
Output
90%
VOH
1.3 V
10% V
OL
tf
tPLH
1.3 V
10%
1.3 V
10%
tf
S2
50 pF
or
150 pF
Open
Closed
Closed
Open
Open
Closed
Closed
Open
Open
Open
50 pF
tPLZ
−−
LOAD CIRCUIT
1.3 V
S1
1 kΩ
tpd or tt
Input
CL
RL
Output
Control
(Low-Level
Enabling)
50 pF
or
150 pF
3V
1.3 V
1.3 V
0V
tPZL
Output
Waveform 1
(See Note B)
tPLZ
≈VCC
1.3 V
10%
tPZH
90%
VOH
VOL
tr
VOLTAGE WAVEFORMS
OUTPUT AND 3-STATE BIDIRECTIONAL I/O
PROPAGATION DELAY TIME
Output
Waveform 2
(See Note B)
VOL
tPHZ
1.3 V
90%
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS
NOTES: A. CL includes probe and test-fixture capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
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5
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN74HCT257D
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HCT257DE4
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HCT257DR
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HCT257DRE4
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HCT257DT
ACTIVE
SOIC
D
16
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HCT257DTE4
ACTIVE
SOIC
D
16
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74HCT257N
ACTIVE
PDIP
N
16
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
SN74HCT257NE4
ACTIVE
PDIP
N
16
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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to Customer on an annual basis.
Addendum-Page 1
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