SN54LVC07A, SN74LVC07A HEX BUFFERS/DRIVERS WITH OPEN-DRAIN OUTPUTS SCAS595N – OCTOBER 1997 – REVISED JULY 2003 D D Operate From 1.65 V to 5 V Inputs and Open-Drain Outputs Accept Voltages Up to 5.5 V 2 13 3 12 4 5 6 7 11 10 9 8 VCC 6A 6Y 5A 5Y 4A 4Y 1Y 2A 2Y 3A 3Y 14 1Y 1A NC VCC 6A 1 2 13 6A 3 12 6Y 4 11 5A 5 10 5Y 9 4A 6 7 8 SN54LVC07A . . . FK PACKAGE (TOP VIEW) 2A NC 2Y NC 3A 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 6Y NC 5A NC 5Y 3Y GND NC 4Y 4A 14 VCC 1 4Y 1A 1Y 2A 2Y 3A 3Y GND Max tpd of 2.6 ns at 5 V Latch-Up Performance Exceeds 250 mA Per JESD 17 SN74LVC07A . . . RGY PACKAGE (TOP VIEW) 1A SN54LVC07A . . . J OR W PACKAGE SN74LVC07A . . . D, DB, DGV, NS, OR PW PACKAGE (TOP VIEW) GND D D NC – No internal connection description/ordering information These hex buffers/drivers are designed for 1.65-V to 5.5-V VCC operation. The outputs of the ’LVC07A devices are open drain and can be connected to other open-drain outputs to implement active-low wired-OR or active-high wired-AND functions. The maximum sink current is 24 mA. Inputs can be driven from 1.8-V, 2.5-V, 3.3-V (LVTTL), or 5-V (CMOS) devices. This feature allows the use of these devices as translators in a mixed-system environment. ORDERING INFORMATION PACKAGE† TA QFN – RGY SN74LVC07ARGYR Tube of 50 SN74LVC07AD Reel of 2500 SN74LVC07ADR Reel of 250 SN74LVC07ADT SOP – NS Reel of 2000 SN74LVC07ANSR LVC07A SSOP – DB Reel of 2000 SN74LVC07ADBR LC07A Tube of 90 SN74LVC07APW Reel of 2000 SN74LVC07APWR Reel of 250 SN74LVC07APWT TVSOP – DGV Reel of 2000 SN74LVC07ADGVR LC07A CDIP – J Tube of 25 SNJ54LVC07AJ SNJ54LVC07AJ CFP – W Tube of 150 SNJ54LVC07AW SNJ54LVC07AW LCCC – FK Tube of 55 SNJ54LVC07AFK SNJ54LVC07AFK TSSOP – PW –55°C to 125°C TOP-SIDE MARKING Reel of 1000 SOIC – D –40°C 40°C to 85°C ORDERABLE PART NUMBER LC07A LVC07A LC07A † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2003, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54LVC07A, SN74LVC07A HEX BUFFERS/DRIVERS WITH OPEN-DRAIN OUTPUTS SCAS595N – OCTOBER 1997 – REVISED JULY 2003 FUNCTION TABLE (each buffer/driver) INPUT A OUTPUT Y H H L L logic diagram, each buffer/driver (positive logic) A Y absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V Output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W (see Note 2): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W (see Note 2): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W (see Note 2): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W (see Note 3): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. 3. The package thermal impedance is calculated in accordance with JESD 51-5. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54LVC07A, SN74LVC07A HEX BUFFERS/DRIVERS WITH OPEN-DRAIN OUTPUTS SCAS595N – OCTOBER 1997 – REVISED JULY 2003 recommended operating conditions (see Note 4) SN54LVC07A VCC VIH Supply voltage High level input voltage High-level SN74LVC07A MIN MAX 1.65 5.5 0.65 × VCC VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V MIN MAX 1.65 5.5 V 0.65 × VCC 1.7 1.7 2 2 0.7 × VCC V 0.7 × VCC 0.35 × VCC VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V UNIT 0.35 × VCC 0.7 0.7 0.8 0.8 VIL Low level input voltage Low-level VI VO Input voltage 0 5.5 0 5.5 V Output voltage 0 5.5 0 5.5 V VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V 0.3 × VCC VCC = 1.65 V VCC = 2.3 V IOL Low-level output current V 0.3 × VCC 4 4 12 12 VCC = 2.7 V VCC = 3 V 12 12 24 24 VCC = 4.5 V 24 24 mA TA Operating free-air temperature –55 125 –40 85 °C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOL = 100 µA IOL = 4 mA VOL IOL = 12 mA IOL = 24 mA II ICC ∆ICC VCC SN54LVC07A TYP† MAX MIN SN74LVC07A TYP† MAX MIN UNIT 1.65 V to 5.5 V 0.2 0.2 1.65 V 0.45 0.45 2.3 V 0.7 0.7 2.7 V 0.4 0.4 3V 0.55 0.55 3.6 V ±5 ±5 µA 3.6 V 10 10 µA 500 500 µA V 4.5 V VI = 5.5 V or GND VI = VCC or GND, IO = 0 One input at VCC – 0.6 V, Other inputs at VCC or GND Ci VI = VCC or GND † All typical values are at VCC = 3.3 V, TA = 25°C. 2.7 V to 3.6 V 3.3 V 5 5 pF PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54LVC07A, SN74LVC07A HEX BUFFERS/DRIVERS WITH OPEN-DRAIN OUTPUTS SCAS595N – OCTOBER 1997 – REVISED JULY 2003 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 4) SN54LVC07A PARAMETER tpd FROM (INPUT) A TO (OUTPUT) VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V MIN MAX MIN MAX 1 3.5 1 2.8 Y VCC = 2.7 V MIN VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V MAX MIN MAX MIN MAX 3 1 2.9 1 2.6 UNIT ns switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 4) SN74LVC07A PARAMETER tpd FROM (INPUT) A TO (OUTPUT) VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V MIN MAX MIN MAX 1 3.5 1 2.8 Y VCC = 2.7 V MIN VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V MAX MIN MAX MIN MAX 3 1 2.9 1 2.6 UNIT ns operating characteristics, TA = 25°C Cpd PARAMETER TEST CONDITIONS Power dissipation capacitance per buffer/driver f = 10 MHz VCC = 1.8 V TYP VCC = 2.5 V TYP 1.8 PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2 VCC = 3.3 V TYP 2.5 VCC = 5 V TYP UNIT 3.78 pF SN54LVC07A, SN74LVC07A HEX BUFFERS/DRIVERS WITH OPEN-DRAIN OUTPUTS SCAS595N – OCTOBER 1997 – REVISED JULY 2003 PARAMETER MEASUREMENT INFORMATION VCC = 1.8 V ± 0.15 V 2 × VCC S1 1 kΩ From Output Under Test Open TEST S1 tPZL (see Note F) 2 × VCC tPLZ (see Note G) 2 × VCC tPHZ/tPZH 2 × VCC GND CL = 30 pF (see Note A) 1 kΩ LOAD CIRCUIT tw VCC Timing Input VCC/2 VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 VCC/2 0V tPLH Output Control (low-level enabling) tPLZ VCC VCC/2 tPZH VCC VCC/2 VOL VCC/2 0V Output Waveform 1 S1 at 2 × VCC (see Note B) tPHL VCC/2 VCC VCC/2 tPZL VCC Input VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 0V 0V tsu Output VCC VCC/2 Input Output Waveform 2 S1 at 2 × VCC (see Note B) VOL + 0.15 V VOL tPHZ VCC/2 VCC VCC – 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. Since this device has open-drain outputs, tPLZ and tPZL are the same as tpd. F. tPZL is measured at VCC/2. G. tPLZ is measured at VOL + 0.15 V. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN54LVC07A, SN74LVC07A HEX BUFFERS/DRIVERS WITH OPEN-DRAIN OUTPUTS SCAS595N – OCTOBER 1997 – REVISED JULY 2003 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.2 V 2 × VCC S1 500 Ω From Output Under Test Open TEST S1 tPZL (see Note F) 2 × VCC tPLZ (see Note G) 2 × VCC tPHZ/tPZH 2 × VCC GND CL = 30 pF (see Note A) 500 Ω LOAD CIRCUIT tw VCC Timing Input VCC/2 VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 VCC/2 0V tPLH Output Control (low-level enabling) tPLZ VCC VCC/2 tPZH VCC VCC/2 VOL VCC/2 0V Output Waveform 1 S1 at 2 × VCC (see Note B) tPHL VCC/2 VCC VCC/2 tPZL VCC Input VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 0V 0V tsu Output VCC VCC/2 Input Output Waveform 2 S1 at 2 × VCC (see Note B) VOL + 0.15 V VOL tPHZ VCC/2 VCC VCC – 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. Since this device has open-drain outputs, tPLZ and tPZL are the same as tpd. F. tPZL is measured at VCC/2. G. tPLZ is measured at VOL + 0.15 V. H. All parameters and waveforms are not applicable to all devices. Figure 2. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54LVC07A, SN74LVC07A HEX BUFFERS/DRIVERS WITH OPEN-DRAIN OUTPUTS SCAS595N – OCTOBER 1997 – REVISED JULY 2003 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPZL (see Note F) 6V tPLZ (see Note G) 6V tPHZ/tPZH 6V LOAD CIRCUIT tw 2.7 V 2.7 V Timing Input 0V 0V 2.7 V 1.5 V 1.5 V 0V 1.5 V 1.5 V 0V tPLH Output Control (low-level enabling) tPLZ 3V 1.5 V tPZH 3V 1.5 V VOL 1.5 V 0V Output Waveform 1 S1 at 6 V (see Note B) tPHL 1.5 V 2.7 V 1.5 V tPZL 2.7 V Output VOLTAGE WAVEFORMS PULSE DURATION th VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Input 1.5 V 1.5 V tsu Data Input 1.5 V Input Output Waveform 2 S1 at 6 V (see Note B) VOL + 0.3 V VOL tPHZ 3V 1.5 V 2.7 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. Since this device has open-drain outputs, tPLZ and tPZL are the same as tpd. F. tPZL is measured at 1.5 V. G. tPLZ is measured at VOL + 0.3 V. H. All parameters and waveforms are not applicable to all devices. Figure 3. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN54LVC07A, SN74LVC07A HEX BUFFERS/DRIVERS WITH OPEN-DRAIN OUTPUTS SCAS595N – OCTOBER 1997 – REVISED JULY 2003 PARAMETER MEASUREMENT INFORMATION VCC = 5 V ± 0.5 V 2 × VCC S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPZL (see Note F) 2 × VCC tPLZ (see Note G) 2 × VCC tPHZ/tPZH 7V LOAD CIRCUIT tw 3V 3V Timing Input 0V 0V 3V 1.5 V 1.5 V 0V 1.5 V 1.5 V 0V tPLH Output Control (low-level enabling) tPLZ VCC VCC/2 tPZH 3.5 V 1.5 V VOL VCC/2 0V Output Waveform 1 S1 at 2 × VCC (see Note B) tPHL 1.5 V VCC VCC/2 tPZL 3V Output VOLTAGE WAVEFORMS PULSE DURATION th VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Input 1.5 V 1.5 V tsu Data Input 1.5 V Input Output Waveform 2 S1 at 7 V (see Note B) VOL + 0.3 V VOL tPHZ 3.5 V 1.5 V 3.2 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. Since this device has open-drain outputs, tPLZ and tPZL are the same as tpd. F. tPZL is measured at VCC/2. G. tPLZ is measured at VOL + 0.3 V. H. All parameters and waveforms are not applicable to all devices. Figure 4. Load Circuit and Voltage Waveforms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°–8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MSOI002B – JANUARY 1995 – REVISED SEPTEMBER 2001 D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 8 PINS SHOWN 0.020 (0,51) 0.014 (0,35) 0.050 (1,27) 8 0.010 (0,25) 5 0.008 (0,20) NOM 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81) Gage Plane 1 4 0.010 (0,25) 0°– 8° A 0.044 (1,12) 0.016 (0,40) Seating Plane 0.010 (0,25) 0.004 (0,10) 0.069 (1,75) MAX PINS ** 0.004 (0,10) 8 14 16 A MAX 0.197 (5,00) 0.344 (8,75) 0.394 (10,00) A MIN 0.189 (4,80) 0.337 (8,55) 0.386 (9,80) DIM 4040047/E 09/01 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). Falls within JEDEC MS-012 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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