Ordering number : EN8767A Monolithic Linear IC LA6548ND For CD Players and Recorders Four-Channel Driver IC Overview The LA6548ND is a four-channel driver IC for CD players and recorders (four BTL amplifier channels). Functions • Four BTL connection power amplifier channels • IO max 0.7A • Built-in level shifters • Muting circuit (on/off control of all outputs) (This circuit applies to the BTL amplifier circuits. It does not control operation of the regulator.) • Built-in regulator (provides a 3.3V output using an external pnp transistor) • Thermal protection circuit (thermal shutdown circuit) Specifications Maximum Ratings at Ta = 25°C Parameter Supply voltage Symbol Conditions VCC max Maximum output current IO max Maximum input voltage VIN Ratings Unit 14 For each of the channel 1 to 4 outputs V 0.7 A 13 V Muting pin application voltage VMUTE 13 V Allowable power dissipation Pd max 1.5 W Operating temperature Topr -20 to +75 °C Storage temperature Tstg -55 to +150 °C Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. 42507 TI PC B8-7473 No.8767-1/7 LA6548ND Recommended Operating Conditions at Ta = 25°C Parameter Symbol Supply voltage 1 VCC1 Supply voltage 2 VCC2 Conditions Ratings Only used by the BTL amplifiers Unit 4.6 to 13 V 3.9 to 13 V (Not used by the 3.3V regulator circuit) Electrical Characteristics at Ta = 25°C, VCC1 = VCC2 = 6V, VREF = 1.65V, unless otherwise specified. Parameter Symbol Ratings Conditions min typ Unit max Overall Characteristics No-load current drain, on state ICCON All outputs on, MUTE : high No-load current drain, off state ICCOFF All outputs off, MUTE : low Thermal shutdown circuit TSD 20 (Design guarantee value *1) 150 The voltage difference between each of the -50 40 mA 15 35 mA 175 200 °C 50 mV operating temperature Output Amplifier Block Output offset voltage VOFF + or - outputs. VREF input voltage range VINVREF Output voltage VO Voltage gain, input to output VG 1.3 The voltage across the outputs when 2.6 VCC-1.5 V 3 V 9 dB RL = 8Ω The voltage gain from an input to the corresponding +/- outputs.*2 Slew rate Muting on voltage SR VMUTE (Design guarantee value *1) The voltage at which the output on/off state 0.15 V/μs 1.2 V changes Power Supply Block (Using a 2SB632K) 3.3V power supply voltage 3.3 3.47 V Line regulation ΔVOLIN 4.6V ≤ VCC ≤ 12V IO = 200mA 3.13 40 100 mV Load regulation ΔVOLOAD 5mA ≤ IO ≤ 200mA 50 150 mV 3.25 3.42 V 100 200 mV 160 mV Reset Block RESET pin high-level voltage VORH RESET pin low-level voltage VORL RESET pin threshold voltage RESET pin hysteresis RESET pin output delay time 3.08 ISRL = 2mA, Cd-GND VRT *4 VHYS *5 td Cd = 0.1μF 2.8 40 80 10 V ms *1 : These parameters are not tested. *2 : The gain from input to output when only the VIN* pins are used. *3 : The MUTE pin voltage when the output changes between the on and off states. When the MUTE pin is high, all the BTL amplifiers will be on, and the when MUTE is low, all the BTL amplifiers will be off. *4 : The 3.3V regulator voltage when the RESET pin goes from high to low. *5 : The 3.3V regulator voltage difference between the RESET pin going from high to low the RESET pin going from low to high. That is, the hysteresis. No.8767-2/7 LA6548ND Package Dimensions unit : mm (typ) 3307 Pd max – Ta 27.0 10.16 16 8.6 30 0.25 15 (3.25) 0.95 0.51 min 3.0 3.95 max 1 (1.04) 0.48 Allowable power dissipation, Pd max – W 2.0 1.5 Independent IC 1.5 1 0.9 0.5 0 – 20 1.78 0 20 40 60 80 100 Ambient temperature, Ta – °C SANYO : DIP30SDLF(400mil) Block Diagram VCC1 1 MUTE 2 Mute (output on/off control) 30 VCC2 29 VREF 15.4kΩ 15.4kΩ 11kΩ 11kΩ 28 VIN4 VG1 4 27 VG4 VO1+ 5 26 VO4+ VO1- 6 25 VO4- GND 7 24 GND GND 8 23 GND GND 9 22 GND VO2- 10 21 VO3- VO2+ 11 20 VO3+ VG2 12 19 VG3 18 VIN3 17 CD 16 RESET Level shifter Level shifter Level shifter 3 Level shifter VIN1 15.4kΩ 15.4kΩ 11kΩ 11kΩ VIN2 13 REG_C 14 REG_B 15 Connect to the external pnp transistor collector. 3.3VREG Connect to the external pnp transistor base. RESET No.8767-3/7 LA6548ND Pin Functions Pin No. Pin 1 VCC1 Power supply (This pin is shorted to VCC2 (pin 30) Description 2 MUTE Output on/off control 3 VIN1 Channel 1 input 4 VG1 Channel 1 input (Gain setting) 5 Channel 1 output (+) 6 VO1+ VO1- 7 GND GND pin 8 GND GND pin 9 GND GND pin 10 VO2- Channel 2 output (-) 11 VO2+ Channel 2 output (+) 12 VG2 Channel 2 input (Gain setting) 13 VIN2 Channel 2 input 14 REG_C Connect this pin to the external pnp transistor collector. (This is the 3.3V regulator output) 15 REG_B Connect this pin to the external pnp transistor base. 16 RESET Reset output 17 CD 18 VIN3 Channel 1 output (-) Connection for the reset delay time setting capacitor Channel 3 input 19 VG3 Channel 3 input (Gain setting) 20 Channel 3 output (+) 21 VO3+ VO3- 22 GND GND pin 23 GND GND pin 24 GND GND pin 25 Channel 4 output (-) 26 VO4VO4+ 27 VG4 Channel 4 input (Gain setting) 28 VIN4 Channel 4 input 29 VREF Reference voltage input 30 VCC2 Power supply (This pin is shorted to VCC1 (pin 1) Channel 3 output (-) Channel 4 output (+) Equivalent Circuits Pin No. 3 4 13 12 18 19 28 27 Pin VIN1 VG1 Description Input pins. Equivalent circuit VG* VCC VIN2 VG2 VIN3 VG3 VIN* GND VCC GND VIN4 VG4 Continued on next page No.8767-4/7 LA6548ND Continued from preceding page. Pin No. 5 6 11 10 20 21 26 25 Pin VO1+ VO1VO2+ VO2VO3+ VO3VO4+ VO4- Description Equivalent circuit Output pins. VCC 33kΩ VCC VO*-/+ GND GND 2 MUTE Muting control input. VCC The outputs will be on when the MUTE pin VCC is at the high level. The outputs will be off when the MUTE pin MUTE is at the low level ; in particular, the outputs 40kΩ go to the high-impedance state at this GND time. 30kΩ 29 VREF Reference voltage input. VREF VCC GND VCC GND 16 RESET Reset output. VCC When REG C (3.3VREG) is high, RESET will be high. REG_C (3.3VREG) When REG C (3.3VREG) is low, RESET GND will be low. Details of Operating voltage see section Reset operation. RESET GND 17 CD Reset output delay time setting. The delay time until the point the reset output switches from low to high is set by the capacitor connected between this pin and ground. Reference to Reset operation. VCC GND GND CD No.8767-5/7 LA6548ND Application Circuit Example VCC 1 VCC1 VCC2 30 VREF input (Reference voltage) MUTE 2 MUTE 3 VREF 29 VIN1 VIN4 28 4 VG1 VG4 27 5 VO1+ VO4+ 26 SPINDLE input FOCUS input FOCUS M SPINDLE 6 VO1- VO4- 25 7 GND GND 24 8 GND GND 23 LA6548ND SLED 9 GND GND 22 10 VO2- VO3- 21 TRACKING M 11 VO2+ VO3+ 20 12 VG2 VG3 19 13 VIN2 VIN3 18 CD 17 SPINDLE input TRACKING input 3.3V input 100μF + 14 REG_C Reset delay time setting 15 REG_B RESET 16 VCC No.8767-6/7 LA6548ND Reset Operation REG_C (3.3VREG) 3.3V (2.88V) 2.80V 80mV T RESET td T td *1 : td is the delay time. It is set by an external capacitor connected between the CD pin and ground). *2 : The voltage at which RESET changes state is a typical value (voltage). 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Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of April, 2007. Specifications and information herein are subject to change without notice. PS No.8767-7/7