Ordering number : ENA0367A Monolithic Digital IC LB11872V For Polygonal Mirror Motors Scanner Driver IC Overview The LB11872V is a three-phase brushless motor driver developed for driving the motors used for the polygonal mirror in laser printers and similar applications. It can implement, with a single IC chip, all the circuits required for polygonal mirror drive, including speed control and driver functions. The LB11872V can implement motor drive within minimal drive noise due to its use of current linear drive. Note that the LB11872V differs from the LB11872H only in the package. Functions and features • Three-phase bipolar current linear drive + midpoint control circuit • PLL speed control circuit • Speed is controlled by an external clock signal. • Supports Hall FG operation. • Built-in output saturation prevention circuit • Phase lock detection output (with masking function) • Includes current limiter, thermal protection, rotor constraint protection, and low-voltage protection circuits on chip. • On-chip output diodes. Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. 21407 MS IM 20060614-S00001 / 81006 MH IM 20060213-S00001 No.A0367-1/12 LB11872V Specifications Absolute Maximum Ratings at Ta = 25°C Parameter Supply voltage Output current Symbol Conditions Ratings VCC max IO max Unit 30 T ≤ 500ms Allowable power dissipation 1 Pd max1 Independent IC Allowable power dissipation 2 Pd max2 Mounted on a circuit board *2 V (*1) 1.5 A 0.6 W 1.7 W Topr -20 to +80 °C Storage temperature Tstg -55 to +150 °C Junction temperature Tj max 150 °C Operating temperature Note *1: This device must be used derated by at least 20% from the rated values. Note *2: Mounted on a specified board: 114.3mm×76.1mm×1.6mm, glass epoxy Allowable Operating Ranges at Ta = 25°C Parameter Symbol Conditions Ratings Unit Supply voltage range VCC 10 to 28 V 6.3 V regulator-voltage output current IREG 0 to -20 mA LD pin applied voltage VLD 0 to 28 V LD pin output current ILD 0 to 15 mA FGS pin applied voltage VFG 0 to 28 V FGS pin output current IFG 0 to 10 mA Electrical Characteristics at Ta = 25°C, VCC = VM = 24V Parameter Symbol Ratings Conditions min Unit typ max Supply current 1 ICC1 Stop mode 5 7 mA Supply current 2 ICC2 Start mode 17 22 mA SOURCE(1) VSAT1-1 IO = 0.5A, RF = 0Ω 1.7 2.2 V SOURCE(2) VSAT1-2 IO = 1.0A, RF = 0Ω 2.0 2.7 V SINK(1) VSAT2-1 IO = 0.5A, RF = 0Ω 0.4 0.9 V SINK(2) VSAT2-2 IO = 1.0A, RF = 0Ω 1.0 1.7 V Output leakage current IO(LEAK) VCC = 28V 100 µA [Output Saturation Voltages VAGC=3.5V] [6.3 V Regulator-Voltage Output] Output voltage VREG 6.25 6.60 V Voltage regulation ∆VREG1 VCC = 9.5 to 28V 50 100 mV Load regulation ∆VREG2 Iload = -5 to -20mA 10 60 Temperature coefficient ∆VREG3 Design target value* 0 Input bias current IB(HA) Differential input: 50mVp-p Differential input voltage range VHIN SIN wave input Common-phase input voltage range VICM Input offset voltage VIOH 5.90 mV mV/°C [Hall Amplifier Block] 2 10 50 (*3) 600 Differential input: 50mVp-p 2.0 VCC-2.5 Design target value* -20 20 µA mVp-p V mV [FG Amplifier and Schmitt Block (IN1)] Input amplifier gain GFG 5 Input hysteresis (high to low) VSHL 0 mV Input hysteresis (low to high) VSLH -10 mV Hysteresis width VFGL Input conversion 4 7 times 12 mV *: These value are design guarantee values, and are not tested. Note *3: Since kickback can occur in the output waveform if the Hall input amplitude is too large, the Hall input amplitudes should be held to under 350mVp-p. Continued on next page. No.A0367-2/12 LB11872V Continued from preceding page. Parameter Symbol Ratings Conditions min unit typ max [Low-Voltage Protection Circuit] Operating voltage VSD 8.4 8.8 9.2 V Hysteresis width ∆VSD 0.2 0.4 0.6 V 150 180 °C 40 °C [Thermal Protection Circuit] Thermal shutdown operating TSD temperature Hysteresis width Design target value* (junction temperature) ∆TSD Design target value* (junction temperature) [Current Limiter Operation] Acceleration limit voltage VRF1 0.53 0.59 0.65 V Deceleration limit voltage VRF2 0.32 0.37 0.42 V [Error Amplifier] Input offset voltage VIO(ER) Input bias current IB(ER) Design target value* High-level output voltage VOH(ER) IOH = -500µA Low-level output voltage VOL(ER) IOL = 500µA DC bias level VB(ER) -10 10 mV -1 1 µA VREG-1.2 VREG-0.9 V 0.9 1.2 V -5% 1/2VREG 5% V VREG-0.2 VREG-0.1 0.3 V -500 µA [Phase Comparator Output] High-level output voltage VPDH IOH = -100µA Low-level output voltage VPDL IOL = 100µA Output source current IPD+ VPD = VREG/2 Output sink current IPD- VPD = VREG/2 0.2 V 1.5 mA [Lock Detection Output] Output saturation voltage VLD(SAT) ILD = 10mA Output leakage current ILD(LEAK) VLD = 28V 0.15 0.5 V 10 µA [FG Output] Output saturation voltage VFG(SAT) IFG = 5mA Output leakage current IFG(LEAK) VFG = 28V Dead zone width VDZ With phase locked Output idling voltage VID Forward gain 1 GDF+1 With phase locked 0.4 0.5 0.6 times Forward gain 2 GDF+2 With phase unlocked 0.8 1.0 1.2 times Reverse gain 1 GDF-1 With phase locked -0.6 -0.5 -0.4 times Reverse gain 2 GDF-2 With phase unlocked -0.8 -1.0 -1.2 times Acceleration command voltage VSTA 5.0 5.6 Deceleration command voltage VSTO Forward limiter voltage VL1 Rf = 22Ω Reverse limiter voltage VL2 Rf = 22Ω Oscillation frequency fOSC C = 0.022µF High-level pin voltage 0.15 0.5 V 10 µA 300 mV 6 mV [Drive Block] 50 100 V 0.8 1.5 V 0.53 0.59 0.65 V 0.32 0.37 0.42 V VCSDH 4.3 4.8 5.3 V Low-level pin voltage VCSDL 0.75 1.15 1.55 V External capacitor charge and ICHG 3 5 7 µA 0.80 V [CSD Oscillator Circuit] discharge current Lock detection delay count CSDCT1 Clock cutoff protection operating CSDCT2 count Lock protection count CSDCT3 Initial reset voltage VRES 31 Hz 7 2 31 0.60 *: These value are design guarantee values, and are not tested. Continued on next page. No.A0367-3/12 LB11872V Continued from preceding page. Parameter Symbol Ratings Conditions min typ unit max [Clock Input Block] External input frequency fCLK 400 10000 Hz High-level input voltage VIH(CLK) Design target value* 2.0 VREG V Low-level input voltage VIL(CLK) Design target value* 0 1.0 V Input open voltage VIO(CLK) 3.3 V Hysteresis width VIS(CLK) Design target value* High-level input current IIH(CLK) V(CLK) = VREG Low-level input current IIL(CLK) V(CLK) = 0V 2.7 0.1 -185 3.0 0.2 0.3 V 140 185 µA µA -140 [S/S Pin] High-level input voltage VIH(S/S) 2.0 VREG Low-level input voltage VIL(S/S) 0 1.0 V Input open voltage VIO(S/S) 2.7 3.3 V Hysteresis width VIS(S/S) High-level input current IIH(S/S) V(S/S) = VREG Low-level input current IIL(S/S) V(S/S) = 0V 0.1 -185 3.0 V 0.2 0.3 V 140 185 µA -140 µA *: These value are design guarantee values, and are not tested. Package Dimensions unit : mm (typ) 3285 TOP VIEW BOTTOM VIEW Exposed Die-Pad 15.0 23 0.5 5.6 7.6 44 1 0.22 0.65 22 0.2 1.7max (0.68) (1.5) SIDE VIEW SANYO : SSOP44J(275mil) Pd max - Ta Allowable Power Dissipation, Pd max - W 2.0 Mounted on a specified board: 114.3mm×76.1mm×1.6mm glass epoxy 1.70 1.5 1.0 0.95 Independent IC 0.60 0.5 0.34 0 -20 0 20 40 60 Ambient Temperature, Ta -°C 80 100 ILB01790 No.A0367-4/12 LB11872V Three-Phase Logic Truth Table OUT1 to OUT3 (H: Source, L: Sink) IN1 IN2 IN3 OUT1 OUT2 OUT3 H L H L H M H L L L M H H H L M L H L H L H L M L H H H M L L L H M H L For IN1 to IN3, “H” means that IN+ is greater than IN-, and “L” means IN- is greater than IN+. For OUT1 to OUT3, “H” means the output is a source, and “L” means that it is a sink. NC NC NC NC NC FC EO EI PD LD CLK S/S FG CSD NC MN AGC NC NC NC NC GND Pin Assignment 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 VCC NC NC NC NC NC SUB RF OUT1 OUT2 OUT3 IN2+ IN2- IN1+ IN1- IN3+ IN3- NC NC 21 22 NC 2 NC 1 VREG LB11872V Top view No.A0367-5/12 LB11872V Equivalent Circuit Block Diagram CLK CLK PD 34 36 EI 37 EO 38 VREG 1 VCC 6.3VREG TSD CSD 31 OSC LD S/S 33 RESET LD 35 PLL LOCK DET LVSD PD CLOCK DET V-AMP FG 32 39 9 OCL FG ×5 10 OUTPUT FILTER MN 11 12 29 HALL AMP & MATRIX S/S FC LD RESTRICT DET FG VCC 2 RF OUT1 OUT2 OUT3 AGC IN1 IN3 IN2 15 16 13 14 17 18 8 28 AGC SUB 23 GND No.A0367-6/12 LB11872V Pin Functions Pin No. Symbol 1 VREG Pin Description Equivalent Circuit Stabilized power supply (6.3 V). VCC Insert a capacitor (about 0.1µF) between this pin and ground for stabilization. 22 2 VCC 8 SUB Power supply SUB pin. Connect this pin to ground. 9 RF Motor drive outputs. VCC If the output oscillates, insert a capacitor (about 0.1µF) between this pin and ground. VREG 26 27 28 10 OUT1 Output current detection. 11 OUT2 Insert low-valued resistors (Rf) between these pins 12 OUT3 and ground. The output current will be limited to the value set by 300Ω the equation IOUT = VL/RF. 13 IN2+ Hall effect sensor signal inputs. 14 IN2- These inputs are high when IN+ is greater than IN- 15 IN1+ and low when IN- is greater than IN+. 16 IN1- The logic high state indicates that VIN+ has a lever 17 IN3+ higher than VIN-. 18 IN3- Insert capacitors between the IN+ and IN- pins to 25 VCC reduce noise. An amplitude of over 50mA p-p and under 350mVp-p 300Ω 300Ω 3 5 2 7 4 6 is desirable for the Hall input signals. Kickback can occur in the output waveform if the Hall input amplitude is over 350mVp-p. 23 GND 28 AGC Ground AGC amplifier frequency characteristics correction. Insert a capacitor (about 0.022µF) between this pin VREG and ground. 300Ω 8 Continued on next page. No.A0367-7/12 LB11872V Continued from preceding page. Pin No. Symbol 29 MN 31 CSD Pin Description Equivalent Circuit Monitor pin. This pin should be left open in normal operation. Used for both initial reset pulse generation and as the reference time for constraint protection circuits. VREG Insert a capacitor between this pin and ground. 300Ω 12 32 FG FG pulse output. This is an open-collector output. VREG 14 33 S/S Start/stop control. Low: Start 0V to 1.0V VREG 33kΩ High: Stop 2.0V to VREG This pin goes to the high level when open. 5kΩ 30kΩ 15 34 CLK Clock input. Low: 0V to 1.0V VREG 33kΩ High: 2.0V to VREG This pin goes to the high level when open. 5kΩ 30kΩ 16 35 LD Phase locked state detection output. This output goes to the on state when the PLL locked VREG state is detected. This is an open-collector output. 17 Continued on next page. No.A0367-8/12 LB11872V Continued from preceding page. Pin No. Symbol 36 PD Pin Description Phase comparator output (PLL output). This pin output the phase error as a pulse signal with Equivalent Circuit VREG varying duty. The output current increases as the duty becomes smaller. 18 37 EI Error amplifier in put pin. VREG 300Ω 19 38 EO Error amplifier output pin. VREG The output current increases when this output is high. 300Ω 40kΩ 20 39 FC Control amplifier frequency correction. VREG Inserting a capacitor (about 5600pF) between this pin and ground will stop closed loop oscillation in the current control system. The output current response characteristics will be degraded if the capacitor is too large. 3 to 7, 19 to 22, NC 21 No connection (NC) pins. These pins may be used for wiring connections. 24 to 27, 30, 40 to 44 No.A0367-9/12 LB11872V Overview of the LB11872V 1. Speed Control Circuit This IC adopts a PLL speed control technique and provides stable motor operation with high precision and low jitter. This PLL circuit compares the phase error at the edges of the CLK signal (falling edges) and FG signal (rising edges (low to high transitions) on the IN1 input), and the IC uses the detected error to control the motor speed. During this control operation, the FG servo frequency will be the same as the CLK frequency. fFG (servo) = fCLK 2. Output Drive Circuit To minimize motor noise, this IC adopts three-phase full-wave current linear drive. This IC also adopts a midpoint control technique to prevent ASO destruction of the output transistors. Reverse torque braking is used during motor deceleration during speed switching and lock pull-in. In stop mode, the drive is cut and the motor is left in the free-running state. Since the output block may oscillate depending on the motor actually used, capacitors (about 0.1µF) must be inserted between the OUT pins and ground. 3. Hall Input Signals This IC includes an AGC circuit that minimizes the influence on the output of changes in the Hall signal input amplitudes due to the motor used. However, note that if there are discrepancies in the input amplitudes between the individual phases, discrepancies in the output phase switching timing may occur. An amplitude (differential) of at least 50mVp-p is required in the Hall input signals. However, if the input amplitude exceeds 350mVp-p, the AGC circuit control range will be exceeded and kickback may occur in the output. If Hall signal input frequencies in excess of 1 kHz (the frequency in a single Hall input phase) are used, internal IC heating during startup and certain other times (that is, when the output transistors are saturated) may increase. Reducing the number of magnetic poles can be effective in dealing with problem. The IN1 Hall signal is used as the FG signal for speed control internally to the IC. Since noise can easily become a problem, a capacitor must be inserted across this input. However, since this could result in differences between the signal amplitudes of the three phases, capacitors must be inserted across all of the three input phases. Although VCC can be used as the Hall element bias power supply, using VREG can reduce the chances of problems occurring during noise testing and at other times. If VREG is used, since there is no longer any need to be concerned with the upper limit of the Hall amplifier common-mode input voltage range, bias setting resistors may be used only on the low side. 4. Power Saving Circuit This IC goes into a power saving state that reduces the current drain in the stop state. The power saving state is implemented by removing the bias current from most of the circuits in the IC. However, the 6.3V regulator output is provided in the power saving state. 5. Reference Clock Care must be taken to assure that no chattering or other noise is present on the externally input clock signal. Although the input circuit does have hysteresis, if problems do occur, the noise must be excluded with a capacitor. This IC includes an internal clock cutoff protection circuit. If a signal with a frequency below that given by the formula below is input, the IC will not perform normal control, but rather will operate in intermittent drive mode. f (Hz) ≈ 0.64 ÷ CCSD CCSD (µF): The capacitor inserted between the CSD pin and ground. When a capacitor of 0.022µF is used, the frequency will be about 29Hz. If the IC is set to the start state when the reference clock signal is completely absent, the motor will turn somewhat and then motor drive will be shut off. After the motor stops and the rotor constraint protection time elapses, drive will not be restarted, even if the clock signal is then reapplied. However, drive will restart if the clock signal is reapplied before the rotor constraint protection time elapses. No.A0367-10/12 LB11872V 6. Rotor Constraint Protection Circuit This IC provides a rotor constraint protection circuit to protect the IC itself and the motor when the motor is constrained physically, i.e. prevented from turning. If the FG signal (edges of one type (rising or falling edges) on the IN1 signal) does not switch within a fixed time, output drive will be turned off. The time constant is determined by the capacitor connected to the CSD pin. <time constant (in seconds)> ≈ 30.5×1.57×CCSD (µF) If a 0.022µF capacitor is used, the protection time will be about 1.05 seconds. To clear the rotor constraint protection state, the IC must be set to the stopped state or the power must be turned off and reapplied. If there is noise present on the FG signal during the constraint time, the rotor constraint protection circuit may not operate normally. 7. Phase Lock Signal (1) Phase lock range Since this IC does not include a counter or similar functionality in the speed control system, the speed error range in the phase locked state cannot be determined solely by IC characteristics. (This is because the acceleration of the changes in the FG frequency influences the range.) When it is necessary to stipulate this characteristic for the motor, the designer must determine this by measuring the actual motor state. Since speed errors occur easily in states where the FG acceleration is large, it is thought that the speed errors will be the largest during lock pull-in at startup and when unlocked due to switching clock frequencies. (2) Masking function for the phase lock state signal A stable lock signal can be provided by masking the short-term low-level signals due to hunting during lock pullin. However, this results in the lock state signal output being delayed by the masking time. The masking time is determined by the capacitor inserted between the CSD pin and ground. <masking time (seconds)> ≈ 6.5×1.57×CCSD (µF) When a 0.022µF capacitor is used, the masking time will be about 225ms. In cases where complete masking is required, a masking time with fully adequate margin must be used. 8. Initial Reset To initially reset the logic circuits in start mode, the IC goes to the reset state when the CSD pin voltage goes to zero until it reaches 0.63V. Drive output starts after the reset state is cleared. The reset time can be calculated to a good approximation using the following formula. <reset time (seconds)> ≈ 0.13×CCSD (µF) A reset time of over 100µs is required. 9. Current Limiter Circuit The current limit value is determined by the resistor Rf inserted between the RF pin and ground. ILIM = VL/Rf VL = 0.6V (typical) (during acceleration) and 0.37V (typical) (during deceleration) 10. Power Supply Stabilization An adequately large capacitor must be inserted between the VCC pin and ground for power supply stabilization. If diodes are inserted in the power supply lines to prevent destruction of the device if the power supply is connected with reverse polarity, the power supply line levels will be even more easily disrupted, and even larger capacitors must be used. If high-frequency noise is a problem, a ceramic capacitor of about 0.1µF must also be inserted in parallel. 11. VREG Stabilization A capacitor of at least 0.1µF must be used to stabilize the VREG voltage, which is the control circuit power supply. The capacitor must be connected as close as possible to the pins. No.A0367-11/12 LB11872V 12. Error Amplifier External Component Values To prevent adverse influence from noise, the error amplifier external components must be located as close to the IC as possible. 13. Heat sink Area Thermal dissipation can be improved significantly by tightly bonding the metallic surface of the back of the IC package to the PCB with, for example, a solder with good thermal conductivity. 14. CSD Pin The capacitor connected to the CSD pin influences several operational aspects of this IC, including the rotor constraint protection time and the phase lock signal mask time. The following are possible ways of determining the value of this capacitor. (1) If removing chattering from the phase lock state signal is most important: Select a capacitance that can assure an adequate mask time. (2) If startup time is more important than chattering: Select a capacitance such that the rotor constraint protection circuit does not operate at startup time and verify that there are no problems with the clock cutoff protection circuit and initial reset time. Operation of the rotor constraint protection circuit may hinder the study of motor characteristics in the uncontrolled state. It is possible to only operate the initial reset function and not operate the rotor constraint protection circuit by inserting a resistor (about 390kΩ) in parallel with the capacitor between the CSD pin and ground. 15. FC Pin The capacitor connected to the FC pin is required for current limiter loop phase compensation. If the value is too low, the output will oscillate. If the value is too large, it will be easier for currents in excess of the limit value to flow during the current limit time (time before the circuit operates) in states where the output is saturated. (This is because the control response characteristics become worse.) 16. AGC Pin A capacitance that allows a certain amount of smoothing of the AGC pin voltage in the motor speed range used must be selected for the capacitor connected to the AGC pin. It is also desirable to use a capacitance that allows the AGC voltage to reach an essentially stabilized voltage before the initial reset is cleared. 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Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of February, 2007. Specifications and information herein are subject to change without notice. PS No.A0367-12/12