SANYO LB11873

Ordering number : ENA0081B
Monolithic Digital IC
LB11873
For Polygonal Mirror Motors
Three-Phase Brushless Motor Driver
Overview
The LB11873 is a 3-phase brushless motor driver developed for driving the polygonal mirror motor used in plain-paper
copiers and similar products. This IC can implement the circuits required for polygonal mirror motor drive (speed control
and driver circuits) in a single chip.
The LB11873 implements low-noise/low-vibration PWM drive by changing the current at phase switching gradually to
reduce motor noise.
Functions
• Three-phase bipolar drive (quiet direct PWM)
• PLL speed control circuit
• Hall sensor FG support
• Dedicated external clock
• Brake mode switching circuit (free running and reverse braking)
• Phase lock detection output (with masking function)
• Built-in current limiter, constraint protection, undervoltage protection, thermal protection, and CLK line disconnection
protection circuits
• Input pins support 3V system microcontrollers
Specifications
Absolute Maximum Ratings at Ta = 25°C
Parameter
Symbol
Supply voltage
VCC max
Output current
IO max
Conditions
Ratings
Unit
30
V
T ≤ 500ms
1.8
A
Allowable power dissipation 1
Pd max1
Independent IC
0.9
W
Allowable power dissipation 2
Pd max2
When mounted on a circuit board *1
2.1
W
*1 Specified circuit board : 114.3 × 76.1 × 1.6mm3, glass epoxy.
Continued on next page.
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,
communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be
intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace
instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety
equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case
of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee
thereof. If you should intend to use our products for applications outside the standard applications of our
customer who is considering such use and/or outside the scope of our intended standard applications, please
consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our
customer shall be solely responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer' s products or
equipment.
71107 TI PC 20070621-S00004/41807 TI PC B8-9144 No.A0081-1/14
LB11873
Continued from preceding page.
Parameter
Symbol
Conditions
Ratings
Unit
Operating temperature
Topr
-20 to +80
°C
Storage temperature
Tstg
-55 to +150
°C
Allowable Operating Ranges at Ta = 25°C
Parameter
Symbol
Conditions
Ratings
Unit
Supply voltage range
VCC
9.5 to 28
V
5V constant voltage output
IREG
0 to -30
mA
LD pin apply voltage
VLD
0 to 28
V
LD pin output current
ILD
0 to 15
mA
FGS pin apply voltage
VFGS
0 to 28
V
FGS pin output current
IFGS
0 to 10
mA
HB pin apply voltage
VHBS
0 to 28
V
HB pin output current
IHBS
0 to 30
mA
Electrical Characteristics at Ta = 25°C, VCC = VM = 24V
Parameter
Symbol
Ratings
Conditions
min
Supply current 1
ICC1
Supply current 2
ICC2
Unit
typ
Stop mode
max
22
28
mA
4.0
6.0
mA
5V constant voltage output (VREG pin)
Output voltage
VREG
5.0
5.35
V
Line regulation
ΔVREG1
VCC = 9.5 to 28V
4.65
80
130
mV
Load regulation
ΔVREG2
IO = -5 to -20mA
10
60
Temperature coefficient
ΔVREG3
Design target*
0
mV
mV/°C
Output Block
Output saturation voltage 1
VOsat1
IO = 0.5A, VO (sink) + VO (source)
1.4
1.9
Output saturation voltage 2
VOsat2
IO = 1.2A, VO (sink) + VO (source)
2.0
2.6
V
V
Output leakage current
IOleak
100
μA
High side diode forward voltage
VD2-1
ID = 0.5A
1.0
1.5
V
VD2-2
ID = 1.2A
1.5
2.0
V
2
10
μA
1
High side diode forward voltage
2
Hall Sensor Amplifier Block
Input bias current
IHB
Differential input range
VIHIN
Common-mode input voltage
VICM
Sine wave input
50
350
1.5
VREG –
range
Input offset voltage
V
1.0
VIOH
Design target value*
-20
20
mV
IHB = 10mA
1.5
2.0
V
10
μA
Hall Sensor Bias
Output saturation voltage
Output leakage current
VOL (HB)
IL (HB)
VO = VCC, stop mode
FG Schmitt Trigger Block (IN1)
Input amplifier gain
GFG
Design target value*
5
Times
Input hysteresis (high → low)
VSHL
Design target value*
0
mV
Input hysteresis (low → high)
VSLH
Design target value*
Hysteresis
VFGL
Input conversion, design target value *
-10
mV
4
7
12
mV
PWM Oscillator
High-level output voltage
VOH (PWM)
2.65
2.95
3.25
Low-level output voltage
VOL (PWM)
0.9
1.2
1.5
V
External capacitor charge
ICHG
-60
-45
-30
μA
1.45
1.75
2.05
Vp-p
VPWM = 2V
V
current
Oscillator frequency
f (PWM)
Amplitude
V (PWM)
C = 680pF
34
kHz
* The design specification items are design guarantees and are not measured.
Continued on next page.
No.A0081-2/14
LB11873
Continued from preceding page.
Parameter
Symbol
Ratings
Conditions
min
Unit
typ
max
FGS Pin
Output saturation voltage
Output leakage current
VOL (FGS)
IFGS = 7mA
IL (FGS)
VO = VCC
f (CSD)
C = 0.033μF
0.15
0.5
V
10
μA
CSD Oscillator Circuit
Oscillator frequency
31
Hz
High-level output voltage
VOH (CSD)
3.50
3.75
4.00
Low-level output voltage
VOL (CSD)
1.00
1.30
1.60
V
V (CSD)
2.20
2.45
2.80
Vp-p
Amplitude
External capacitor charge
V
ICHG1
VCSD = 2V
-7
-5
-3
μA
ICHG2
VCSD = 2V
3
5
7
μA
0.8
V
current
External capacitor discharge
current
Lock detection delay counts
CSDCT1
7
Clock disconnected protection
CSDCT2
2
CSDCT3
31
VRES
0.6
counts
Constraint protection operation
counts
Initial reset voltage
Phase Comparator Output
High-level input voltage
VPDH
IOH = -100μA
Low-level input voltage
VPDL
IOL = 100μA
Input source current
IPD+
VPD = VREG/2
Input sink current
IPD-
VPD = VREG/2
VREG - 0.2
V
VREG - 0.1
0.2
0.3
V
-0.5
mA
1.5
mA
Phase Lock Detection Output
Output saturation voltage
Output leakage current
VOL (LD)
IL (LD)
ILD = 10mA
0.15
0.5
V
10
μA
-10
10
mV
-1
1
μA
4.3
V
VO = VCC
Error Amplifier Block
Input offset voltage
Input bias current
VIO (ER)
Design target value*
IB (ER)
High-level output voltage
VOH (ER)
IEI = -0.1mA, no load
Low-level output voltage
VOL (ER)
IEI = 0.1mA, no load
DC bias level
VB (ER)
3.7
4.0
0.7
1.0
1.3
V
-5%
VREG/2
5%
V
0.4
0.5
0.6
Times
Current Llimiter Circuit
Drive gain 1
GDF1
In the phase locked state
Drive gain 2
GDF2
In the unlocked state
0.8
1.0
1.2
Times
Llimiter voltage 1
VRF1
VCC - VM, forward mode
0.45
0.5
0.55
V
Llimiter voltage 2
VRF2
VCC - VM, reverse mode
0.225
0.25
0.275
V
150
170
°C
40
°C
Thermal shutdown circuit
Thermal shutdown operating
TSD
temperature
Thermal shutdown temperature
Design target value* (junction
temperature)
ΔTSD
hysteresis
Design target value* (junction
temperature)
Low Voltage Protection Circuit
Operating voltage
VSDL
8.1
8.45
8.9
V
Hysteresis
ΔVSD
0.2
0.35
0.5
V
External input frequency
fI (CLK)
0.1
10
kHz
High-level input voltage
VIH (CLK)
2.0
VREG
V
Low-level input voltage
VIL (CLK)
0
1.0
V
Input open voltage
VIO (CLK)
Hysteresis
VIS (CLK)
High-level input current
IIH (CLK)
VCKIN = VREG
Low-level input current
IIL (CLK)
VCKIN = 0V
CLK pin
3.0
V
0.25
115
-220
-175
V
150
μA
μA
Continued on next page.
Note : * The design specification items are design guarantees and are not measured.
No.A0081-3/14
LB11873
Continued from preceding page.
Parameter
Symbol
Ratings
Conditions
min
typ
Unit
max
S/S pin
High-level input voltage
VIH (SS)
2.0
Low-level input voltage
VIL (SS)
0
Input open voltage
VIO (SS)
Hysteresis
VIS (SS)
High-level input current
IIH (SS)
VS/S = VREG
Low-level input current
IIL (SS)
VS/S = 0V
VREG
V
1.0
V
3.0
0.21
V
0.25
115
-220
0.29
V
150
μA
μA
-175
BRSEL pin
High-level input voltage
VIH (BRSEL)
2.0
Low-level input voltage
VIL (BRSEL)
0
Input open voltage
VIO (BRSEL)
Hysteresis
VIS (BRSEL)
High-level input current
IIH (BRSEL)
VBRSEL = VREG
Low-level input current
IIL (BRSEL)
VBRSEL = 0V
VREG
V
1.0
V
3.0
0.21
-220
V
0.25
0.29
V
115
150
μA
μA
-175
Package Dimensions
unit : mm (typ)
3235A
Allowable power dissipation, Pd max – W
0.65
17.8
(6.2)
2.7
10.5
7.9
(4.9)
36
1
0.25
(0.5)
Pd max – Ta
2.5
2.0
0.3
Specified circuit board : 114.3×76.1×1.6mm3
glass epoxy board
0.9W
Independent IC
2.0
1.5
1.18W
1.0
0.5
2.45max
(2.25)
0.8
2.1W
0
– 20
0
20
40
60
80
100
0.1
Ambient temperature, Ta – °C
SANYO : HSOP36(375mil)
Three-Phase Logic Truth Table (The input "H" state is the state where IN+ > IN-)
IN1
IN2
IN3
OUT1
OUT2
OUT3
H
L
H
L
H
M
H
L
L
L
M
H
H
H
L
M
L
H
L
H
L
H
L
M
L
H
H
H
M
L
L
L
H
M
H
L
S/S pin
Input state
State
High or open
Stop
Low
Start
BRESEL pin
Input state
During deceleration
High or open
Free running
Low
Reverse braking
No.A0081-4/14
LB11873
BRSEL
CLK
S/S
LD
FGS
27
26
25
24
23
22
21
20
19
10
11
12
13
14
15
16
17
18
PD
EI
EO
FGFIL
CSD
28
PH
VM
29
FCP
VCC
30
FCS
NC
31
PWM
NC
32
TM
NC
33
GND1
GND2
34
VREG
NC
35
HB
OUT3
36
FRAME
NC
Pin Assignment
2
3
4
5
6
7
8
9
OUT1
NC
IN3+
IN3-
IN2+
IN2-
IN1+
IN1-
FRAME
1
OUT2
LB11873
Top view
Hall sensor input waveforms and output current waveform
(1) When the Hall sensor input amplitude is small or when the input waveform slope is low
High
IN1
Low
IN2
IN3
Source
IOUT1
Sink
IOUT2
IOUT3
180° drive: Current flows during all periods; there are on off periods (180° drive)
(2) When the Hall sensor input amplitude is larger or when the input waveform slope is steep
High
IN1
Low
IN2
IN3
IOUT1
Source
Sink
IOUT2
IOUT3
In this case, periods in which drive is off will occur (the off periods vary depending on the Hall sensor inputs).
No.A0081-5/14
LB11873
Internal Equivalent Circuit Block Diagram and External Reference Circuit
TM
PWM
PD
TSD
CSD
CSD
OSC
Count
PWM
OSC
VREG
EI
+
S/S
EO
S/S
BRSEL
BRSEL
CONT
AMP
COMP
LD
LD
Peak
hold
FCP
PH
PLL
VREG
CLK
CLK
VREG
Control
circuit
VCC
VCC
FGS
FG
FGFIL
Filter
Rf
CURR
LIM
VM
-
-
+
+
OUT1
Driver
OUT2
Hall amplifier
HB
IN1+ IN1-
IN2+ IN2-
IN3+ IN3-
HB
OUT3
FCS
GND2
GND1
VREG
No.A0081-6/14
LB11873
Pin Functions
Pin No.
Pin
2
OUT1
1
OUT2
35
OUT3
Description
Equivalent Circuit
Motor drive outputs
VCC
VM
300Ω
28
33
GND2
Output block ground
1
28
VM
35
2
Motor drive output power supply and output current
detection
Connect a resistor (Rf) between this pin and VCC.
The output current will be limited to the value IOUT
= VRF/Rf.
8
IN1+
Hall sensor inputs
9
IN1-
"H" is the state where IN+ > IN-, and "L" is the
6
IN2+
reverse state.
7
IN2-
It is desirable that the Hall sensor signals have an
4
IN3+
amplitude greater than 50 mVpp
5
IN3-
If noise on the Hall sensor signals is a problem,
connect capacitors between the IN+ and IN- inputs.
10
HB
33
VREG
300Ω
5
7
Hall sensor element bias current
300Ω
9
4
6
8
VREG
This circuit is turned off in stop mode.
10
11
GND1
12
PWM
Control circuit block ground
Sets the PWM oscillator frequency.
Connect a capacitor between this pin and ground.
VREG
A 680pF capacitor sets the oscillator frequency to
be about 34kHz.
200Ω
12
2kΩ
Continued on next page.
No.A0081-7/14
LB11873
Continued from preceding page.
Pin No.
Pin
13
FCP
Description
Current limiter circuit frequency characteristics
correction
Equivalent Circuit
VREG
Connect a capacitor (about 0.01μF to 0.1μF)
between this pin and ground.
The output duty is determined by comparing the
voltage at this pin with the PWM oscillator
300Ω
waveform.
13
14
PD
Phase comparator output
VREG
The phase error is converted to a pulse duty and
output from this pin.
300Ω
14
15
EI
Error amplifier input
VREG
300Ω
15
16
EO
Error amplifier output
VREG
16
40kΩ
17
FGFIL
FG filter
This pin is normally left open. If noise on the FG
VREG
signal is a problem, connect a capacitor (about
20pF or smaller) between this pin and ground.
300Ω
17
Continued on next page.
No.A0081-8/14
LB11873
Continued from preceding page.
Pin No.
Pin
Description
18
CSD
Initial reset pulse generation and protection circuit
Equivalent Circuit
VREG
reference oscillator
Connect a capacitor between this pin and ground.
300Ω
18
19
FGS
FG Schmitt trigger output
VREG
19
20
LD
Phase lock detection output
This output goes to the on state (low-level output)
VREG
in the phase locked state.
20
21
S/S
Start/stop control
Low : 0V to 1.0V
VREG
High : 2.0V to VREG
Hysteresis : about 0.25V
20kΩ
This pin goes to the high level when open.
5kΩ
A low level specifies the start state.
21
30kΩ
22
CLK
Clock input
Low : 0V to 1.0V
VREG
High : 2.0V to VREG
Hysteresis : about 0.25V
fCLK = 10kHz max.
20kΩ
If there is noise on this signal, insert a noise
5kΩ
rejection capacitor at this input.
22
30kΩ
Continued on next page.
No.A0081-9/14
LB11873
Continued from preceding page.
Pin No.
Pin
23
BRSEL
Description
Equivalent Circuit
Deceleration (braking) control selection
Low : 0V to 1.0V
VREG
High : 2.0V to VREG
This pin goes to the high level when open.
20kΩ
A low level selects reverse torque control and a
high level selects free running braking. If reverse
5kΩ
torque control is used, an external Schottky barrier
23
diode will be required on the low side of the output.
30kΩ
24
PH
RF waveform smooth
Connect a capacitor between this pin and ground.
VREG
500Ω
25
FCS
Control loop frequency characteristics correction
Connect a capacitor between this pin and ground.
34
VREG
300Ω
25
26
TM
Monitor output
This pin is normally left open.
VREG
300Ω
26
Continued on next page.
No.A0081-10/14
LB11873
Continued from preceding page.
Pin No.
Pin
27
VREG
Description
Stabilized power supply output (5V output)
Connect a capacitor between this pin and ground
Equivalent Circuit
VCC
for power supply stabilization.
(About 0.1μF)
27
29
VCC
Power supply.
Connect a capacitor (a few tens of μF or larger)
between this pin and ground so that noise does not
enter the IC.
3, 30
NC
31, 32
Since this pin is not connected internally to the
chip, it can be used for wiring connections.
34, 36
FRAME
Connect this pin to ground.
LB11873 Overview
1. Speed control circuit
Since the LB11873 adopts PLL speed control, it provides precise, low-jitter, and stable motor operation. This PLL
circuit compares the falling edge of the CLK signal with the FG signal (edges on which the IN1 input changes from low
to high and FGS output rising edges) and controls motor operation based on the difference.
During control operation, the FG servo frequency is the same as the CLK signal frequency.
fFG (servo) = fCLK
2. Output drive circuit
This IC minimizes motor vibration and noise by changing the output current smoothly during phase switching. Since
the change (slope) imposed on the output current during phase switching uses the slope of the Hall sensor input
waveform, the changes in the output waveforms at phase switching will become too steep if the Hall sensor input
waveform slope is steep. This will reduce the noise and vibration reducing effect of this technique. Thus care is
required concerning the slope of the Hall sensor input waveform.
Low side output transistor PWM switching is used for motor speed control and the drive output is adjusted by changing
the duty. The diode between OUT and VM used for the regenerative current when the PWM is off is built into this IC.
Due to the parasitic diode between OUT and ground, if reverse control mode (torque braking) is selected for braking, an
external Schottky barrier diode must be used. Also, if there are problems when the output current is large (for example,
incorrect operation or waveform disruption during low side kickback) a Schottky barrier diode must be connected
between OUT and ground.
Note that if it is necessary to reduce IC thermal dissipation during constant-speed operation, it may be effective to insert
a Schottky barrier diode between OUT and VM. This effect occurs because the regenerative current during PWM
switching will be dissipated in the external diode instead of the IC's internal diode.
3. Current limiter circuit
The current limiter circuit limits the drive current to a current determined by the equation I = VRF/RF, where VRF =
0.5V (typical) and Rf is the current detection resistor. The limiting operation works by reducing other output on duty to
suppress the drive current.
The current limiter circuit detects the reverse recovery current due to PWM operation and, to assure that the current
limiting operation is not performed incorrectly, provides a delay of about 2µs before it operates. Since the changes in
the current levels at startup (the state where there is no counterelectromotive force from the motor) will be rapid if
either the motor coil resistance is low or if the inductance is low, there are cases where current limiter will operates at a
current level above that set due to this delay. In these cases, it will be necessary to take the amount of current increase
due to the delay into account when setting the current limit value.
No.A0081-11/14
LB11873
4. Power saving circuit
This IC goes into a power saving state in which current drain is reduced when set to the stop state. This power saving
state is implemented by cutting the bias current to most of the circuits in the IC. The 5V regulator output, however, is
still output when the IC is in the power saving state.
5. Reference clock
Care must be taken to assure that no noise due to chattering or other problems appears on the externally input clock
signal. While the input circuit is designed with hysteresis, noise must be rejected by, for example, inserting capacitors
in the clock line if noise problems occur.
The LB11873 provides a built-in clock disconnection protection circuit. At clock frequencies lower than the frequency
determined by the following equation, the LB11873 will not perform its normal control operation, but rather will
operate in an intermittent mode.
f (Hz) ≈ 1.02 ÷ CCSD
CCSD (µF) : the capacitor connected between the CSD pin and ground.
If a 0.033µF capacitor is used, the frequency will be about 31Hz.
If the IC is set to the start state with absolutely no clock signal provided, the motor will first start to turn somewhat and
then the drive will be turned off.
If motor rotation stops, a time in excess of the constraint protection operating time elapses, and then the clock signal is
applied again, drive operation will not be restarted. However, if the clock signal is reapplied before the constraint
protection circuit operates, drive operation will restart.
6. PWM frequency
The PWM frequency is determined by the capacitance of the capacitor (C) connected to the PWM pin.
fPWM ≈ 1/(43000 × C)
If a 680pF capacitor is used, the circuit will oscillate at about 34kHz. If the PWM frequency is too low the motor will
emit switching noise, and if it is too high the power loss in the output will increase. A frequency in the range 15kHz to
50kHz is desirable. This capacitor must be connected between this pin and the GND pin by lines that are as short as
possible to make this circuit immune to noise.
The capacitor ground side must be connected as close as possible to the IC control block ground (the GND1 pin), to
minimize the influence of the output.
7. Hall sensor input signals
The Hall sensor input signals must have an amplitude (differential) of over 50mVpp. If disruption of the output
waveforms occurs due to noise on these signals, capacitors must be connected between the Hall sensor inputs (between
the + and - sides).
8. FCS pin
The capacitor (about 0.1µF) connected to the FC pin is required for correction of the control loop frequency
characteristics.
9. Constraint protection circuit
The LB11873 includes a built-in constraint protection circuit to protect the IC and the motor if the motor is physically
constrained from turning.
If FG signal (one side edge of IN1) does not switch states for a period in excess of a certain fixed time in the start state,
the PWM drive side output is turned off.
The time is set by the capacitor connected to the CSD pin.
Set time (seconds) ≈ 30.5 × 0.98 × CCSD (μF)
If a 0.033µF capacitor is used, the protection operation time will be about 0.99 seconds.
The constraint protection state can be cleared by either switching to the stop state (and remaining for over 100μs) or
turning the power off and then on again. Note that the constraint protection circuit may not operate correctly if there is
noise on the FG signal when the motor is physically constrained.
No.A0081-12/14
LB11873
10. Phase lock signal
(1) Phase lock range
Since this IC does not have a speed system counter, the speed error range in the phase locked state cannot be
determined by the IC characteristics alone. (This is because the range is affected by the acceleration with changes in the
FG frequency.) If it is necessary to stipulate this in conjunction with a motor, it will be necessary to measure the range
with the actual motor state. Since speed errors occur easily in states where the FG acceleration is large, it is thought that
the lock pull-in time at startup and the unlock time due to clock switching will be the cases where the speed error is the
largest.
(2) Phase lock signal mask function
It is possible to assure that the lock signal is output in stable states by masking the short-term low levels due to hunting
during lock pull-in. Note, however, that the lock signal output will be delayed by the amount of the mask time.
The mask time is set by the capacitor connected between the CLD pin and ground.
Mask time (s) ≈ 6.5 × 0.98 × CCSD (μF)
When a 0.033µF capacitor is used, the mask time will be about 210ms. If full masking is required, the mask time must
be set with an adequate margin.
11. Initial reset
To apply an initial reset to the logic circuit, the IC goes to the reset state until the CSD pin voltage changes from 0V to
about 0.63V. After the reset is cleared, drive will start. The reset time can be calculated quite closely with the following
equation.
Reset time (s) ≈ 0.13 × CCSD (μF)
A reset time of over 100µs is required.
12. Power supply stabilization
Since this IC is used in switching drive applications with large output currents, the power supply line is easily
disrupted.
Therefore it is necessary to connect an adequately large capacitor between the VCC pin and ground.
The capacitor ground side is connected to the GND2 pin, which is the power system ground, and must be connected as
close as possible to the pin.
If the capacitor (an electrolytic capacitor) cannot be connected close to the pin, a ceramic capacitor of about 0.1µF must
be connected close to the pin.
If reverse control mode (torque braking) is selected for braking, since there will be states where the current returns to
the power supply, the power supply line level will be especially subject to disruption. Since the power supply line is
most easily disrupted during lock pull-in at high speeds, designers must analyze this case carefully and select an
adequately large capacitor.
Since the power supply line is particularly susceptible to disruption if a diode is inserted in the power supply line to
prevent destruction of the IC by reverse connection, an even larger capacitor must be selected in this case.
13. VREG stabilization
Connect a capacitor with a value over 0.1µF to stabilize the VREG voltage, which is the IC's control circuit power
supply. This capacitor's ground side must be connected as close as possible to the IC's control block ground (the GND1
pin).
14. Error amplifier system components
The external components for the error amplifier block must be located as close as possible to the IC to minimize the
influence of noise. These components must also be located as far from the motor as possible.
15. FRAME pin
An electrolytic capacitor must be connected between the FRAME pin and GND2 with the capacitor's ground side is
connected to GND2.
No.A0081-13/14
LB11873
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to change without notice.
PS No.A0081-14/14