SANYO LC723481W

Ordering number : ENN7253
CMOS IC
LC723481W,723482W,723483W
Low-Voltage ETR-Controller
Overview
Package Dimensions
The LC723481W, 723482W, and 723483W are lowvoltage electronic tuning radio microcontrollers that
include a PLL that operates up to 250 MHz and a 1/4 duty
1/2 bias LCD driver on chip. These ICs include an on-chip
DC-DC converter, making it is easy to create the supply
voltages required for tuning and allowing cost reductions
in end products.
These ICs are optimal for use in low-voltage portable
audio equipment that includes a radio receiver.
unit: mm
3190A-SQFP64
[LC723481W/2W/3W]
48
0.5
12.0
10.0
33
32
10.0
12.0
49
Function
64
17
1
16
(0.5)
0.15
0.18
1.7max
(1.5)
(1.25)
0.1
• Program memory (ROM):
— 2048 × 16 bits (4K bytes)
LC723481W
— 3072 × 16 bits (6K bytes)
LC723482W
— 4096 × 16 bits (8K bytes)
LC723483W
• Data memory (RAM):
— 128 × 4 bits
LC723481W
— 192 × 4 bits
LC723482W
— 256 × 4 bits
LC723483W
• Cycle time: 40 µs (all 1-word instructions) at 75kHz
crystal oscillation
• Stack: 4 levels (8 levels)
LC723481W(LC723482W/3W)
• LCD driver: 48 to 80 segments (1/4 duty, 1/2 bias drive)
• Interrupts: One external interrupt
Timer interrupts (1, 5, 10, and 50 ms)
• A/D converter: Three input channels
(5-bit successive approximation
conversion)
• Input ports: 7 ports (of which 3 can be switched for use
as A/D converter inputs)
• Output ports: 6 ports (of which 1 can be switched for use
as the beep tone output and 2 are opendrain ports)
SANYO: SQFP64
Continued on next page.
Any and all SANYO products described or contained herein do not have specifications that can handle
applications that require extremely high levels of reliability, such as life-support systems, aircraft’s
control systems, or other applications whose failure can be reasonably expected to result in serious
physical and/or material damage. Consult with your SANYO representative nearest you before using
any SANYO products described or contained herein in such applications.
SANYO assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other
parameters) listed in products specifications of any and all SANYO products described or contained
herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
N2002RM (OT) No. 7253-1/15
LC723481W/2W/3W
Continued from preceding page.
•
•
•
•
•
•
•
•
•
I/O ports: 16 pins (Of these 8 can be switched over to
function as LCD ports as a mask options.)
PLL: Dead band control is supported. (Four types)
Reference frequencies: 1, 3, 3.125, 5, 6.25, 12.5,
and 25 kHz
Input frequencies: FM band: 10 to 250 MHz
AM band: 0.5 to 40 MHz
Input sensitivity:
FM band: 35 mVrms (50 mVrms at 130 MHz or higher
frequency)
AM band: 35 mVrms
IF counting: Using the HCTR input pin for 0.4 to
12 MHz signals
External reset input: During CPU and PLL operations,
instruction execution is started from
location 0.
Built-in power-on reset circuit:
The CPU starts execution from location 0 when power is
first applied.
Halt mode: The controller-operating clock is stopped.
Backup mode: The crystal oscillator is stopped.
Static power-on function: Backup state is cleared with
the PF port
• Beep tone: 1.5625 and 3.125 kHz
• Built-in low-pass filter amplifier: This circuit obviates
the need for an external amplifier for the PLL circuit and
contributes to reduced end product costs.
• Built-in DC/DC converter:
Cost reduced in tuner-use power supply circuit
• Memory retention voltage: 0.9 V at least
• VDD voltage
— PLL: 1.8 to 3.6 V
— CPU: 1.4 to 3.6 V
— ADC: 1.6 to 3.6 V
• Optional function switches:
— PH0 to PH3/S13 to S16
— PG0 to PG3/S17 to S20
— PG0 to PG3 (open-drain output/general-purpose
output)
— PH0 to PH3 (open-drain output/general-purpose
output)
— FM DC/DC clock (75 kHz or 1/256 times the local
FM oscillator frequency)
— AM DC/DC clock (1/2, 1/4, 1/8, or 1/16 times the
AM local oscillator frequency)
• Package: SQFP-64 (0.5-mm pitch)
49 TU
50 DBR4
51 DBR3
52 DBR2
53 DBR1
54 BRES
55 HCTR
56 VDD
57 FMIN
58 AMIN
59 VSS
60 EO
61 AIN
62 AOUT
63 TEST1
64 XIN
Pin Assignment
XOUT
1
48
COM1
TEST2
2
47
COM2
PA3
3
46
COM3
PA2
4
45
COM4
PA1
5
44
S1
PA0
6
43
S2
PB3
7
42
S3
PB2
8
41
S4
PB1
9
40
S5
PB0
10
39
S6
PC3
11
38
S7
PC2
12
37
S8
36
S9
35
S10
34
S11
33
S12
General-purpose
inputs
22
23
24
25
26
27
28
29
30
31
32
ADI1/PF1
ADI0/PF0
VSS
S20/PG3
S19/PG2
S18/PG1
S17/PG0
S16/PH3
S15/PH2
S14/PH1
S13/PH0
General-purpose I/O,
open drain outputs,
segment outputs
21
ADI3/PF2
General-purpose I/O,
open drain outputs,
segment outputs
20
16
BEEP/PE0
PD2
Generalpurpose
I/O
19
15
PE1
PD3
18
14
INT/PD0
PC0
17
13
PD2
PC1
Open drain
outputs
General-purpose I/O
General-purpose inputs/
A/D converter inputs
General-purpose unbalanced outputs
Open drain outputs
No. 7253-2/15
LC723481W/2W/3W
Specifications
Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V
Parameter
Maximum supply voltage
Input voltage
Symbol
VIN
Output voltage
Output current
Allowable power dissipation
Conditions
Ratings
VDD max
All input pins
Unit
–0.3 to +4.0
V
–0.3 to VDD +0.3
V
–0.3 to +15
V
VOUT(1)
AOUT, PE, TU
VOUT(2)
All output pins except VOUT(1)
IOUT(1)
PC, PD, PG, PH, EO
0 to 3
mA
–0.3 to VDD + 0.3
V
IOUT(2)
PB
0 to 1
mA
IOUT(3)
AOUT, PE, TU
0 to 2
mA
IOUT(4)
S1 to S20
IOUT(5)
COM1 to COM4
Pdmax
Ta = –20 to +70°C
300
µA
3
mA
300
mW
Operating temperature
Topr
–20 to +70
°C
Storage temperature
Tstg
–45 to +125
°C
Allowable Operating Ranges at Ta = –20 to +70°C, VDD = 1.8 to 3.6 V
Parameter
Supply voltage
Input high-level voltage
Input low-level voltage
Input amplitude
Input voltage range
Input frequency
Symbol
Conditions
Ratings
min
typ
max
Unit
VDD(1)
PLL operating voltage
1.8
VDD(2)
Memory retention voltage
1.0
VDD(3)
CPU operating voltage
VDD(4)
A/D converter operating voltage
VIH(1)
Input ports other than VIH(2), VIH(3), AMIN,
FMIN, HCTR, and XIN
0.7 VDD
VDD
V
VIH(2)
BRES port
0.8 VDD
VDD
V
VIH(3)
Port PF
0.6 VDD
VDD
V
VIL(1)
Input ports other than VIL(2), VIL(3), AMIN,
FMIN, HCTR, and XIN
0
0.3 VDD
V
VIL(2)
BRES port
0
0.2 VDD
V
VIL(3)
Port PF
0
0.2 VDD
VIN(1)
XIN
0.5
0.6
Vrms
3.0
3.6
1.4
3.0
3.6
1.6
3.0
3.6
V
V
VIN(2)
FMIN, AMIN
0.035
0.35
Vrms
VIN(3)
FMIN
0.05
0.35
Vrms
VIN(4)
HCTR
0.035
0.35
Vrms
VIN(5)
ADIO, ADI1, ADI3
0
VDD
FIN(1)
XIN: CI ≤ 35 kΩ
70
75
V
80
kHz
MHz
FIN(2)
FMIN: VIN(2), VDD(1)
10
130
FIN(3)
FMIN: VIN(3), VDD(1)
130
250
MHz
FIN(4)
AMIN(H): VIN(2), VDD(1)
2
40
MHz
FIN(5)
AMIN(L): VIN(2), VDD(1)
0.5
10
MHz
FIN(6)
HCTR: VIN(4), VDD(1)
0.4
12
MHz
No. 7253-3/15
LC723481W/2W/3W
Electrical Characteristics within the allowable operating ranges
Parameter
Symbol
IIH(1)
XIN: VI = VDD = 3.0 V
IIH(2)
FMIN, AMIN, HCTR: VI = VDD = 3.0 V
IIH(3)
PA/PF (without pull-down resistors), the PC,
PD, PG, PH, ports,
and BRES: VI = VDD = 3.0 V
IIL(1)
XIN: VDD = VSS
IIL(2)
FMIN, AMIN, HCTR: VI = VDD = VSS
IIL(3)
PA/PF (without pull-down resistors), the PC,
PD, PG, PH, ports,
and BRES: VI = VDD = VSS
Input high-level current
Input low-level current
Input floating voltage
Pull-down resistor values
Hysteresis
Voltage doubler reference voltage
Voltage doubler step-up voltage
Output high-level voltage
Output low-level voltage
Output off leakage current
VIF
PA/PF (with pull-down resistors), VDD = 3.0 V
RPD(2)
TEST1, TEST2
VH
DBR4
DBR1, 2, 3
Ratings
min
typ
3
–3
Unit
max
8
–8
PA/PF (with pull-down resistors)
RPD(1)
3
µA
20
µA
3
µA
–3
µA
–20
µA
–3
µA
0.05 VDD
200
V
75
100
0.1 VDD
0.2 VDD
Referenced to VDD, C(3) = 0.47 µF,
Ta = 25°C *1
1.3
1.5
1.7
V
C(1) = 0.47 µF
C(2) = 0.47 µF, without loading, Ta = 25°C *1
2.7
3.0
3.3
V
VDD –
0.3 VDD
V
10
BRES
kΩ
kΩ
V
VOH(1)
PB: IO = –1 mA
VDD –
0.7 VDD
VOH(2)
PC, PD, PG, PH, : IO = –1 mA
VDD –
0.3 VDD
V
VOH(3)
EO: IO = –500 µA
VDD –
0.3 VDD
V
VOH(4)
XOUT: IO = 200 µA
VDD –
0.3 VDD
V
2.0
V
2.0
V
*1
VOH(5)
S1 to S20: IO = –20 µA
VOH(6)
COM1, COM2, COM3, COM4:
IO = –100 µA *1
VOL(1)
PB: IO = –50 µA
0.7 VDD
V
VOL(2)
PC, PD, PG, PH, PE: IO = –1 mA
0.3 VDD
V
VOL(3)
EO: IO = –500 µA
0.3 VDD
V
VOL(4)
XOUT: IO = –200 µA
0.3 VDD
V
VOL(5)
S1 to S20: IO = –20 µA *1
1.0
V
VOL(6)
COM1, COM2, COM3, COM4:
IO = –100 µA *1
1.0
V
0.3 VDD
V
VOL(7)
PE: IO = 2 mA
1.0
VOL(8)
AOUT (AIN = 1.3 V), TU: IO = 1 mA, VDD = 3 V
0.5
V
IOFF(1)
Ports PB, PC, PD, PG, PH and EO
–3
+3
µA
IOFF(2)
AOUT, PE and port TU
–100
+100
nA
ADI0, ADI1, ADI3, VDD(4)
–1/2
+1/2
LSB
A/D converter error
Current drain
Conditions
IDD(1)
VDD(1): FIN(2) 130 MHz, Ta = 25°C
IDD(2)
VDD(2): In HALT mode, Ta = 25°C *2
5
mA
0.1
mA
IDD(3)
VDD = 3.6 V, with the oscillator stopped,
Ta = 25°C *3
1
µA
IDD(4)
VDD = 1.8 V, with the oscillator stopped,
Ta = 25°C *3
0.5
µA
Note: The halt mode current is due to the CPU executing 20 instruction steps every 125 ms.
No. 7253-4/15
LC723481W/2W/3W
Note: * C(1), C(2), and C(3) must be connected even if an LCD is not used.
DBR1
0.1 to 1 µF
C(C1)
0.1 to 1 µF
DBR2
DBR3
C(C2)
0.1 to 1 µF
DBR4
C(C3)
Notes: *1. The capacitors C(1), C(2), and C(3) must be connected to the DBR pins.
*2. Halt mode current measurement circuit
*3. Backup mode current measurement circuit
7 pF
7 pF
A
75 kHz
75 kHz
XOUT VDD BRESDBR1
XIN
7pF
FMIN
AMIN
HCTR
TEST1, 2
A
DBR2
DBR3
DBR4
VSS
0.1 µF
0.1 µF
7pF
XOUT VDD BRES DBR1
XIN
DBR2
DBR3
0.1 µF
DBR4
0.1 µF
0.1 µF
PA, PF
AIN
With all ports other than those specified above left open.
With output mode selected for PC and PD.
With segments S13 to S20 selected.
FMIN
AMIN
HCTR
TEST1, 2
0.1 µF
VSS
AIN
With all ports other than those specified above left open.
With output mode selected for PC and PD.
With segments S13 to S20 selected.
No. 7253-5/15
LC723481W/2W/3W
Block Diagram
XIN
DIVIDER
PHASE
DETECTOR
REFERENCE DIVIDER
SYSTEM CLOCK
GENERATOR
XOUT
FMIN
1/2
1/16, 1/17
EO
75kHz
PROGRAMMBLE DIVIDER
1/8
TU
FM LOCAL 1/256
AM LOCAL 1/2, 1/4, 1/8, 1/16
AMIN
DIVIDER
PLL CONTROL
PLL DATA LATCH
S1
LCDA/B
VDD
VSS
HCTR
BRES
1/2
TIME BASE COUNT
END
CONTROL
UNIVERSAL
COUNTER
(20bits)
SEG
4 LA 7
80
LCPA/B
*
S12
P-ON
RESET
TEST1
TEST2
PA0
PA1
PA2
PA3
PB0
PB1
PB2
PB3
BUS
DRIVER
*
DATA
LATCH
/
BUS
DRIVER
PC0
PC1
PC2
PC3
DATA
LATCH
/
BUS
DRIVER
INT/PD0
PD1
PD2
PD3
DATA
LATCH
/
BUS
DRIVER
AIN
AOUT
LCD
PORT
DRIVER
RAM
ADDRESS
128 × 4bits(LC723481) DECODER
192 × 4bits(LC723482)
256 × 4bits(LC723483) BANK
BUS
CONTROL
ROM
2k × 16bits(LC723481)
3k × 16bits(LC723482)
4k × 16bits(LC723483)
INSTRUCTION
DECODER
SKIP
ADDRESS DECODER
14
ADDRESS COUNTER
14
STACK
JMP
CAL
RETURN
INTERRUPT
RESET
BANK CF
JUDGE
LATCH
A
DATA
LATCH
/
BUS
DRIVER
S13/PH3
S14/PH2
S15/PH1
S16/PH0
DATA
LATCH
/
BUS
DRIVER
S17/PG3
S18/PG2
S19/PG1
S20/PG0
DOUBLER
CIRCUIT
COMMON
DRIVER
DBR1
DBR2
DBR3
DBR4
COM4
COM3
COM2
COM1
BEEP TONE
DATA
LATCH
/
BUS
DRIVER
PE0/BEEP
MPX
PE1
ALU
LATCH
B
MPX
TIMER 0
MPX
(5bits)
DATA
LATCH
/
BUS
DRIVER
PF0/ADI0
PF1/ADI1
PF2/ADI3
DATA BUS
No. 7253-6/15
LC723481W/2W/3W
Pin Functions
Pin No.
Pin
I/O
64
XIN
I
1
XOUT
O
63
TEST1
I
2
TEST2
I
Function
I/O circuit
75 kHz oscillator connections
IC testing. These pins must be connected to ground during normal operation.
—
Input with built-in
pull-down resistor
6
PA0
5
PA1
4
PA2
3
PA3
I
Special-purpose key return signal input ports designed with a low threshold voltage.
When used in conjunction with port PB to form a key matrix, up to 3 simultaneous key
presses can be detected. The four pull-down resistors are selected together in a
single operation using the IOS instruction (PWn = 2, b1); they cannot be specified
individually. Input is disabled in backup mode, and the pull-down resistors are
disabled after a reset.
General-purpose CMOS and n-channel open-drain output shared-function ports.
Unbalanced CMOS push-pull
The IOS instruction (Pwn = 2) is used for function switching.
10
PB0
9
PB1
8
PB2
7
PB3
(b0: PB0, b2: PB1, b3: PB2, PB3) (0: general-purpose CMOS, 1: n-channel opendrain)
O
Special-purpose key source signal output ports. Since unbalanced CMOS output
transistor circuits are used, diodes to prevent short-circuits when multiple keys are
pressed are not required. These ports go to the output high-impedance state in
backup mode. These ports go to the output high-impedance state after a reset and
remain in that state until an output instruction (OUT, SPB, or RPB) is executed.
*: Verify the output impedance conditions carefully if these pins are used for functions
other than key source outputs.
CMOS push-pull
14
PC0
13
PC1
12
PC2
11
PC3
18
INT0/PD0
17
PD1
16
PD2
15
PD3 *2
General-purpose I/O ports.
I/O
PD0 can be used as an external interrupt port. Input or output mode can be set
individually using the IOS instruction (Pwn = 4, 5) by the bit . A value of 0 specifies
input, and 1 specifies output. These ports go to the input disabled high-impedance
state in backup mode. They are set to function as general-purpose input ports after a
reset.
General-purpose output and BEEP output (PE0 shared function ports).
The BEEP instruction is used to switch the BEEP/PE0 port between the generalpurpose output port and the BEEP output functions.
20
BEEP/PE0
19
PE1
O
N-channel open-drain
A BEEP instruction with b2 = 0 will set the BEEP/PE0 port to function as a generalpurpose output port. If b2 is set to 1, the instruction will select the BEEP output
function. Bits b0 and b1 switch the frequency of the BEEP output. This IC supports
two BEEP frequencies.
*: When the PE0 port is set to function as the BEEP output, executing an output
instruction for PE0 will only change the value of the internal output latch; it will have
no effect on the output. Only the PE0 pin can be switched between the generalpurpose output port and BEEP output functions; the PE1 pin is a dedicated generalpurpose output port. In backup mode, these ports go to the high-impedance state.
These ports will remain in that state until either an output instruction or a BEEP
instruction is executed. Since these ports are open drain ports, a resistor must be
inserted between each port and VDD. At reset, they are set to the general-purpose
output port function.
Continued on next page.
No. 7253-7/15
LC723481W/2W/3W
Continued from preceding page.
Pin No.
Pin
23
PF0/ADI0
22
PF1/ADI1
21
PF2/ADI3
I/O
I
Function
I/O circuit
General-purpose input and A/D converter input shared function ports. The IOS
instruction (Pwn = FH) is used to switch between the general-purpose input and A/D
converter port functions. The general-purpose input and A/D converter port functions
can be switched by the bit, with 0 specifying general-purpose input, and 1 specifying
the A/D converter input function. To select the A/D converter function, set up the A/D
converter pin with an IOS instruction with Pwn set to 1. The A/D converter is started
with the UCC instruction (b3 = 1, b2 = 1). The ADCE flag is set when the conversion
completes. The INR instruction is used to read in the data.
CMOS input/analog input
*: If an input instruction is executed for one of these pins which is set up for analog
input, the read in data will be at the low level since CMOS input is disabled. In
backup mode these pins go to the input disabled high-impedance state. These
ports are set to their general-purpose input port function after a reset. The A/D
converter is a 5-bit successive approximation type converter, and features a
conversion time of 1.28 ms. Note that the full-scale A/D converter voltage (1FH) is
(62/96) VDD.
CMOS push-pull
Shared function ports that function either as LCD driver segment outputs or generalpurpose I/O ports.
The IOS instruction is used to switch between the segment output and the generalpurpose I/O port functions.
25
PG3/S20
26
PG2/S19
27
PG1/S18
28
PG0/S17
29
PH3/S16
30
PH2/S15
31
PH1/S14
32
PH0/S13
O
• When used as segment output ports
The IOS (Pwn=8) instruction is used to set the general-purpose I/O port.
b0 to 3 = S17 to S20/PG0 to PG3
(0: Segment output, 1: PG0 to PG3)
The IOS (Pwn=9) instruction is used to set the general-purpose I/O port.
b0 to 3 = S13 to S16/PH0 to PH3
(0: Segment output, 1: PH0 to PH3)
• When used as general-purpose I/O ports
The IOS instruction (Pwn=6, 7) is used to switch the I/O direction. The directions
of these pins can be set individually in 1-bit units.
b0 = PG0
b1 = PG1
b2 = PG2
b3 = PG3
*2
0: Input
1: Output
b0 = PH0
b1 = PH1
b2 = PH2
b3 = PH3
0: Input
1: Output
In backup mode, if used as general-purpose I/O ports, they will be in the input
disabled high-impedance state. If used as segment outputs, they will be held fixed at
the low level.
Although the general-purpose port/LCD port setting is a mask option, the setup with
the IOS instruction described above is also necessary.
CMOS push-pull
LCD driver segment output pins.
33 to
44
A 1/4-duty 1/2-bias drive technique is used.
S12 to S1
O
The frame frequency is 75 Hz.
In backup mode, the outputs are fixed at the low level.
After a reset, the outputs are fixed at the low level.
45
COM4
46
COM3
47
COM2
48
COM1
50
DBR4
51
DBR3
52
DBR2
53
DBR1
LCD driver common output pins.
A 1/4-duty 1/2-bias drive technique is used.
O
The frame frequency is 75 Hz.
In backup mode, the outputs are fixed at the low level.
After a reset, the outputs are fixed at the low level.
I
LCD power supply step-up voltage inputs.
Continued on next page.
No. 7253-8/15
LC723481W/2W/3W
Continued from preceding page.
Pin No.
Pin
I/O
54
BRES
I
Function
I/O circuit
System reset input.
In CPU operating mode or halt mode, applications must apply a low level for at least
one full machine cycle to reset the system and restart execution with the PC set to
location 0. This pin is connected in parallel with the internal power on reset circuit.
N-channel open-drain
Tuning voltage generation circuit outputs.
49
TU
O
These pins include a n-ch transistor, and a tuning voltage can be generated by
connecting external coil, diode, and capacitor components.
Special-purpose universal counter input port
• To measure a frequency, set up HCTR frequency measurement mode and the
measurement time with a UCS instruction (b3 = 0, b2 = 0) and start the count with
a UCC instruction.
UCS b3 b2
55
HCTR
I
0
0
Input pin
Measurement
mode
HCTR
Frequency
measurement
0
1
—
—
1
0
—
—
UCS b1 b0
CMOS amplifier input
Measurement time
0
0
1 ms
0
1
4 ms
1
0
8 ms
1
1
32 ms
The CNTEND flag is set when the count completes. Since the input circuit functions
as an AC amplifier in this mode, the input must be capacitance coupled.
This pin goes to the input disabled state in backup mode, halt mode, PLL stop mode,
and after a reset.
CMOS amplifier input
FM VCO (local oscillator) input.
This pin is selected with the PLL instruction CW1.
57
FMIN
I
CW1 b1, b0
0
0
Bandwidth
10 to 250 MHz
The input must be capacitor coupled.
Input is disabled in backup mode, in halt mode, after a reset, and in PLL stop mode.
AM VCO (local oscillator) input.
This pin and the bandwidth are selected with the PLL instruction CW1.
CW1 b1, b0
58
AMIN
I
CMOS amplifier input
Bandwidth
1
0
2 to 40 MHz (SW)
1
1
0.5 to 10 MHz (MW, LW)
The input must be capacitor coupled.
Input is disabled in backup mode, in halt mode, after a reset, and in PLL stop mode.
Continued on next page.
No. 7253-9/15
LC723481W/2W/3W
Continued from preceding page.
Pin No.
Pin
I/O
Function
I/O circuit
CMOS push-pull
60
EO
O
Main charge pump output. When the local oscillator frequency divided by N is higher
than the reference frequency a high level is output, when lower, a low level is output.
The pin is set to the high-impedance state when the frequencies match.
Output goes to the high-impedance state in backup mode, in halt mode, after a reset,
and in PLL stop mode.
61
AIN
62
AOUT
24
VSS
59
VSS
56
VDD
Note 2:
O
Connections for the built-in transistor used to form a low-pass filter.
Power supply pin.
—
This pin must be connected to ground.
This pin must be connected to ground.
—
This pin must be connected to VDD.
When a pin in an I/O switching port is used as an output, applications must first set up the data with an OUT, SPB, or RPB instruction and then set
up output mode with an IOS instruction.
No. 7253-10/15
LC723481W/2W/3W
Sample Application for Tuning Voltage
Generation Circuit
Sample Application for Low-Pass Filter
Amplifier
XIN
64
XOUT
1
75k Hz
V DD
Mask
option
56
EO
FMIN
57
FM T
1/256
60
AIN
AMIN
58
63
1/2 to 1/16
AM T
AOUT
Varactor
49
62
RADIO ON
TU+B
LC723481 DC-DC converter load = 100 kW (When VDD = 1.8 V)
12
Clock frequency during
FM reception
(When 75 kHz is selected)
Clock frequency range
during AM reception
10
VT voltage - V
8
6
220µH
180µH
150µH
4
100µH
2
0
1
100
1000
10000
Clock frequency - kHz
No. 7253-11/15
LC723481W/2W/3W
LC723481W, 723482W and 723483W Series Instruction Set
Terminology
ADDR
b
C
DH
DL
I
M
N
Rn
Pn
PW
r
( ), [ ]
M (DH, DL)
Instructions
Mnemonic
Subtraction instructions
Addition instructions
AD
: Program memory address
: Borrow
: Carry
: Data memory address High (Row address) [2 bits]
: Data memory address Low (Column address) [4 bits]
: Immediate data [4 bits]
: Data memory address
: Bit position [4 bits]
: Resister number [4 bits]
: Port number [4 bits]
: Port control word number [4 bits]
: General register (One of the addresses from 00H to 0FH of BANK0)
: Contents of register or memory
: Data memory specified by DH, DL
Operand
1st
2nd
r
M
Function
Add M to r
Operations function
r ← (r) + (M)
Instruction format
f
e
d
c
b
a
0
1
0
0
0
0
9
8
DH
7
6
5
DL
4
3
2
1
ADS
r
M
Add M to r, then skip if carry
r ← (r) + (M), skip if carry
0
1
0
0
0
1
DH
DL
r
AC
r
M
Add M to r with carry
r ← (r) + (M) + C
0
1
0
0
1
0
DH
DL
r
ACS
r
M
Add M to r with carry,
then skip if carry
r ← (r) + (M) + C
skip if carry
0
1
0
0
1
1
DH
DL
r
AI
M
I
Add I to M
M ← (M) + I
0
1
0
1
0
0
DH
DL
I
AIS
M
I
Add I to M, then skip if carry
M ← (M) + I, skip if carry
0
1
0
1
0
1
DH
DL
I
AIC
M
I
Add I to M with carry
M ← (M) + I + C
0
1
0
1
1
0
DH
DL
I
Add I to M with carry,
then skip if carry
M ← (M) + I + C,
skip if carry
0
1
0
1
1
1
DH
DL
I
AICS
M
I
SU
r
M
Subtract M from r
r ← (r) – (M)
0
1
1
0
0
0
DH
DL
r
Subtract M from r,
then skip if borrow
r ← (r) – (M),
skip if borrow
0
1
1
0
0
1
DH
DL
r
SUS
r
M
SB
r
M
Subtract M from r with borrow
r ← (r) – (M) – b
0
1
1
0
1
0
DH
DL
r
Subtract M from r with borrow,
then skip if borrow
r ← (r) – (M) – b,
skip if borrow
0
1
1
0
1
1
DH
DL
r
SBS
r
M
SI
M
I
Subtract I from M
M ← (M) – I
0
1
1
1
0
0
DH
DL
I
Subtract I from M,
then skip if borrow
M ← (M) – I,
skip if borrow
0
1
1
1
0
1
DH
DL
I
SIS
M
I
SIB
M
I
Subtract I from M with borrow
M ← (M) – I – b
0
1
1
1
1
0
DH
DL
I
I
Subtract I from M with borrow,
then skip if borrow
M ← (M) – I – b,
skip if borrow
0
1
1
1
1
1
DH
DL
I
SIBS
M
0
r
Continued on next page.
No. 7253-12/15
LC723481W/2W/3W
Continued from preceding page.
Logic instructions
Comparison instructions
Instructions
Mnemonic
SEQ
Transfer instructions
2nd
r
M
Function
Skip if r equal to M
Operations function
Instruction format
f
e
d
c
b
a
(r) – (M), skip if zero
0
0
0
1
0
0
9
DH
8
7
6
DL
5
4
3
2
r
1
SEQI
M
I
Skip if M equal to I
(M) – I, skip if zero
0
0
0
1
1
0
DH
DL
I
SNEI
M
I
Skip if M not equal to I
(M) – I, skip if not zero
0
0
0
0
0
1
DH
DL
I
(r) – (M),
skip if not borrow
0
0
0
1
1
0
DH
DL
r
I
SGE
r
M
Skip if r is greater than or
equal to M
SGEI
M
I
Skip if M is greater than
equal to I
(M) – I, skip if not borrow
0
0
0
1
1
1
DH
DL
SLEI
M
I
Skip if M is less than I
(M) – I, skip if borrow
0
0
0
0
1
1
DH
DL
I
AND
r
M
AND M with r
r ← (r) AND (M)
0
0
1
0
0
0
DH
DL
r
ANDI
M
I
AND I with M
M ← (M) AND I
0
0
1
0
0
1
DH
DL
I
OR
r
M
OR M with r
r ← (r) OR (M)
0
0
1
0
1
0
DH
DL
r
ORI
M
I
OR I with M
M ← (M) OR I
0
0
1
0
1
1
DH
DL
I
EXL
r
M
Exclusive OR M with r
r ← (r) XOR (M)
0
0
1
1
0
0
DH
DL
r
EXLI
M
I
Exclusive OR M with M
M ← (M) XOR I
0
0
1
1
1
0
DH
DL
I
0
0
0
0
0
0
SHR
Jump and subroutine
Bit test
call instructions
instructions
Operand
1st
r
carry
(r)
Shift r right with carry
0
0
1
1
1
0
r
LD
r
M
Load M to r
r ← (M)
1
1
0
1
0
0
DH
DL
r
ST
M
r
Store r to M
M ← (r)
1
1
0
1
0
1
DH
DL
r
MVRD
r
M
Move M to destination M
referring to r in the same row
[DH, Rn] ← (M)
1
1
0
1
1
0
DH
DL
r
MVRS
M
r
Move source M referring to r
to M in the same row
M ← [DH, Rn]
1
1
0
1
1
1
DH
DL
r
MVSR
M1
M2
Move M to M in the same row
[DH, DL1] ← [DH, DL2]
1
1
1
0
0
0
DH
DL1
DL2
MVI
M
I
Move I to M
M←I
1
1
1
0
0
1
DH
DL
I
if M (N) = all 1s, then skip 1
1
1
1
0
0
DH
DL
N
if M (N) = all 0s, then skip 1
1
1
1
0
1
DH
DL
N
Jump to the address
PC ← ADDR
1
0
0
ADDR (13 bits)
Call subroutine
PC ← ADDR
Stack ← (PC) + 1
1
0
1
ADDR (13 bits)
Return from subroutine
PC ← Stack
0
0
0
0
0
0
0
0
1
0
0
0
Return from interrupt
PC ← Stack,
BANK ← Stack,
CARRY ← Stack
0
0
0
0
0
0
0
0
1
0
0
1
TMT
M
N
Test M bits, then skip if all bits
specified are true
TMF
M
N
Test M bits, then skip if all bits
specified are false
JMP
CAL
RT
RTI
ADDR
ADDR
0
Continued on next page.
No. 7253-13/15
LC723481W/2W/3W
Continued from preceding page.
Status register
instructions
Instructions
Mnemonic
Operand
2nd
SS
SWR
N
Set status register
Hardware control
instructions
I/O instructions
Bank switching
instructions
Instruction format
f
e
d
c
b
a
9
8
7
6
(Status W-reg) N ← 1
1
1
1
1
1
1
1
1
0
0 SWR
5
4
3
2
N
1
RS
SWR
N
Reset status register
(Status W-reg) N ← 0
1
1
1
1
1
1
1
1
0
1 SWR
N
SRR
N
Test status register true
if (Status R-reg) N = all
1
1
1
1
1
0
0
0
0
SRR
N
TSF
SRR
N
Test status register false
if (Status R-reg) N = all
1
1
1
1
1
0
0
0
1
SRR
N
Test Unlock F/F
if Unlock F/F (N) = all 0s,
then skip
0
0
0
0
0
0
0
0
1
1
Load M to PLL register
PLL reg ← PLL data
1
1
1
1
1
0
Set I to UCCW1
UCCW1 ← I
0
0
0
0
0
0
0
0
0
0
0
1
I
Set I to UCCW2
UCCW2 ← I
0
0
0
0
0
0
0
0
0
0
1
0
I
Beep control
BEEP reg ← I
0
0
0
0
0
0
0
0
0
1
1
0
I
Dead zone control
DZC reg ← I
0
0
0
0
0
0
0
0
1
0
1
1
I
Set timer register
Timer reg ← I
0
0
0
0
0
0
0
0
1
1
0
0
1
1
1
1
1
1
0
TUL
N
M
UCS
I
UCC
I
BEEP
I
DZC
I
TMS
I
DH
0
1
DL
r
I
IOS
PWn
N
Set port control word
IOS reg PWn ← N
IN
M
Pn
Input port data to M
M ← (Pn)
1
1
1
0
1
0
DH
DL
Pn
Output contents of M to port
P1n ← M
1
1
1
0
1
1
DH
DL
Pn
Input port data to M
M ← (Pn)
0
0
1
1
1
0
DH
DL
Pn
Set port1 bits
(Pn)N ← 1
0
0
0
0
0
0
1
0
Pn
N
(Pn)N ← 0
0
0
0
0
0
0
1
1
Pn
N
INR
SPB
M
Pn
M
Pn
P1n
N
PWn
N
RPB
P1n
N
Reset port1 bits
TPT
P1n
N
Test port1 bits, then skip if all bits
if (Pn)N = all 1s, then skip 1
specified are true
1
1
1
1
1
0
0
Pn
N
TPF
P1n
N
Test port1 bits, then skip if all bits
if (Pn)N = all 0s, then skip 1
specified are false
1
1
1
1
1
0
1
Pn
N
0
0
0
0
0
0
0
0
1
1
0
0
0
0
DH
DL
DIGIT
1
1
0
0
0
1
DH
DL
DIGIT
1
1
0
0
1
0
DH
DL
DIGIT
1
1
0
0
1
1
DH
DL
DIGIT
BANK
I
LCDA
M
I
LCDB
M
I
LCPA
M
I
LCPB
M
I
HALT
CKSTP
NOP
I
Select Bank
BANK ← I
Output segment pattern to LCD
digit direct
LCD (DIGIT) ← M
0
1
1
0
N
1
OUT
LCD
instructions
Operations function
TST
PLL
Other
instructions
Function
1st
1
Output segment pattern to LCD
digit through LA
LCD (DIGIT) ← LA ← M
Halt mode control
HALT reg ← I,
then CPU clock stop
0
0
0
0
0
0
0
0
0
1
0
0
Clock stop
Stop x’tal OSC
0
0
0
0
0
0
0
0
0
1
0
1
No operation
No operation
0
0
0
0
0
0
0
0
0
0
0
0
I
I
No. 7253-14/15
LC723481W/2W/3W
Specifications of any and all SANYO products described or contained herein stipulate the performance,
characteristics, and functions of the described products in the independent state, and are not guarantees
of the performance, characteristics, and functions of the described products as mounted in the customer’s
products or equipment. To verify symptoms and states that cannot be evaluated in an independent device,
the customer should always evaluate and test devices mounted in the customer’s products or equipment.
SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all
semiconductor products fail with some probability. It is possible that these probabilistic failures could
give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire,
or that could cause damage to other property. When designing equipment, adopt safety measures so
that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective
circuits and error prevention circuits for safe design, redundant design, and structural design.
In the event that any or all SANYO products (including technical data, services) described or contained
herein are controlled under any of applicable local export control laws and regulations, such products must
not be exported without obtaining the export license from the authorities concerned in accordance with the
above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system,
or otherwise, without the prior written permission of SANYO Electric Co., Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification”
for the SANYO product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not
guaranteed for volume production. SANYO believes information herein is accurate and reliable, but
no guarantees are made or implied regarding its use or any infringements of intellectual property rights
or other rights of third parties.
This catalog provides information as of November, 2002. Specifications and information herein are
subject to change without notice.
PS No. 7253-15/15