SANYO LC723784

Ordering number : ENN8011A
LC723781N
LC723782N
LC723783N
LC723784
LC723785
CMOS IC
Electronic tuning system for car audio
ETR Microcontrollers
Overview
The LC723780 Series are large-capacity ETR microcontrollers that can support up to 128KB of ROM and up to 8KB of
RAM. In addition to the expanded table reference instruction to support large-capacity program ROM, the LC723780
Series provide enhanced interrupt capability to directly control CD mechanism and CD-DSP, and the capability to
support the RDS models. They also have a built-in serial I/O port and an 8-input 8-bit A/D converter for communicating
with the internal and external devices, and for minimizing the connecting wire between the front panel board and the
main board, particularly for car audio systems.
The on-chip high-performance PLL circuit provides a high-speed lock circuit used to search for alternative frequencies of
RDS in a short time, the ability to control the C/N characteristics of a local oscillator, and the high S/N through the direct
PLL configuration.
Functions
• ROM
• RAM
• Stack
: Up to 64K steps (65,535×16-bits)
The subroutine area holds 4K steps (4,096×16-bits)
: Up to 16K×4-bits (In banks 00 through FF)
LC723781N-ROM : 40KB, RAM : 2KB
LC723782N-ROM : 48KB, RAM : 2KB
LC723783N-ROM : 64KB, RAM : 4KB
LC723784-ROM : 96KB, RAM : 6KB
LC723785-ROM : 128KB, RAM : 8KB
: 32levels
Any and all SANYO Semiconductor products described or contained herein do not have specifications
that can handle applications that require extremely high levels of reliability, such as life-support systems,
aircraft's control systems, or other applications whose failure can be reasonably expected to result in
serious physical and/or material damage. Consult with your SANYO Semiconductor representative
nearest you before using any SANYO Semiconductor products described or contained herein in such
applications.
SANYO Semiconductor assumes no responsibility for equipment failures that result from using products
at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor
products described or contained herein.
92706 / 80505HKIM B8-9065,9068,9069,8420,8219 / 91004JOIM No.8011-1/14
LC723781N/723782N/723783N/723784/723785
• Serial I/O
• External interrupts
• Internal interrupts
: Three channels. These circuits can support both 2-wire and 3-wire 8-bit communication
techniques, and can be switched between MSB first and LSB first operation.
One of six internally generated serial transfer clock rates can be selected: 12.5kHz,
37.5kHz, 187.5kHz, 281.25kHz, 375kHz, and 450kHz
: Seven interrupt inputs (pins INT0 through INT5, and the HOLD pin)
These interrupts can be set to switch between rising and falling edges, although the
HOLD pin only supports falling edge detection.
: Seven interrupts ; four internal timer interrupts, and three serial I/O interrupts.
Functions (Continued)
• Interrupt nesting levels
: 16 levels
Interrupts are prioritized in hardware as follows :
HOLD pin>INT0 pin>INT1 pin>INT2 pin>INT3 pin>INT4 pin>INT5 pin>
S-I/O0>S-I/O1>S-I/O2>Internal TMR0>Internal TMR1>Internal TMR2>
Internal TMR3
• A/D Converter
: 8-bit resolution and 8 inputs
• General-purpose ports
: Input ports : 13
Output ports : 4
I/O ports : 62 (These pins can be switched between input and output in 1-bit units.)
• PLL block
: Includes a sub-charge pump for high-speed locking.
Supports dead zone control.
Built-in unlock detection circuit
Twelve reference frequencies : 1kHz, 3kHz, 3.125kHz, 5kHz, 6.25kHz, 9kHz,
10kHz, 12.5kHz, 25kHz, 30kHz, 50kHz, and 100kHz
• Universal counter
: This 20-bit counter can be used for either frequency or period measurement and
supports four measurement (calculation) periods : 1ms, 4ms, 8ms, and 32ms
• Timers
: Two fixed timers and two programmable timers (8-bit counters)
TMR0
: Supports four periods : 10µs, 100µs, 1ms, and 5ms
TMR1
: Supports four periods : 10µs, 100µs, 1ms, and 10ms
TMR2 and TMR3 : Programmable 8-bit counters.
Input clocks with 10µs, 100µs, and 1ms
One 125-ms timer flip-flop provided
• Beep circuit
: Provides 12 fixed beep tones :
500Hz, 1kHz, 2kHz, 2.08kHz, 2.2kHz, 2.5kHz, 3kHz, 3.125kHz, 3.33kHz,
3.75kHz, 4.17kHz, and 7.03kHz
Programmable 8-bit beep tone generator.
Reference clocks with frequencies of 50kHz, 15kHz, and 5kHz.
• Reset
: Built-in voltage detection reset circuit
External reset pin
• Cycle time
: 1.33µs/833ns (All instructions are one word), X’tal : 4.5MHz/7.2MHz
Supports software switching (Initial cycle time is 1.33µs)
• Halt mode
: The microcontroller operating clock is stopped in Halt mode.
There are four conditions that can clear Halt mode : Interrupt requests,
timer flip-flop overflows, port PA inputs, and HOLD pin inputs.
• Operating supply voltage : 4.5 to 5.5V (Microcontroller block only : 3.5 to 5.5V)
• Package
: QIP100E
• OTP version
: LC72F3781
• Development tools
: Emulator
: RE128V
Evaluation chip
: LC72EV3780
Evaluation board
: EB-72EV3780
No.8011-2/14
LC723781N/723782N/723783N/723784/723785
Specifications
Absolute Maximum Ratings at Ta = 25°C VSS = 0V
Parameter
Symbol
Conditions
Maximum supply voltage
VDD max
Input voltage
VIN1
PC-PORT
VIN2
All input pins other than VIN1
Output voltage
Output current
Ratings
Unit
-0.3 to +6.5
VOUT1
PJ-PORT
VOUT2
PC-PORT
VOUT3
All input pins other than VOUT1 and VOUT2
IOUT1
PC, PJ-PORT
IOUT2
PB, PD, PE, PF, PG, PK, PL, PM, PN, PO, PP PQ,
V
-0.3 to +8
V
-0.3 to VDD+0.3
V
-0.3 to +14
V
-0.3 to +8
V
-0.3 to VDD+0.3
V
PR, PS, PT-PORT, EO1, EO2, SUBPD
Ta = -40 to +85 °C
0 to +5
mA
0 to +3
mA
400
mW
Allowable power dissipation
Pd max
Operating temperature
Topr
-40 to +85
°C
Storage temperature
Tstg
-40 to +125
°C
Allowable Operating Range at Ta = -40 to +85°C, VDD = 3.5 to 5.5V
Parameter
Symbol
Ratings
Pins
min
Supply voltage
Input high-level
typ
uit
mx
VDD1
CPU and PLL operation
4.5
VDD2
CPU operation
3.5
5.5
VDD3
Memory retention
1.1
5.5
VIH1
PB, PC, PH, PI, PL, PM, PN, PP, PO, PQ, PR, PS,
0.7VDD
VDD
V
0.8VDD
VDD
V
2.5
VDD
V
0.6VDD
VDD
V
0
0.3VDD
V
0
0.2VDD
V
voltage
PT-PORT, HCTR, LCTR, INEO, SUBPD
5.0
5.5
V
(with the I/O ports set to input mode)
VIH2
PD, PE, PF, PG, PK-PORT, LCTR
(in period measurement mode), HOLD, RESET
Input low-level voltage
VIH3
SNS
VIH4
PA-PORT
VIL1
PB, PC, PH, PI, PL, PM, PN, PP, PO, PQ, PR, PS,
PT-PORT, HCTR, LCTR, INEO, SUBPD
(with the I/O ports set to input mode)
VIL2
PA, PD, PE, PF, PG, PK-PORT, LCTR
(in period measurement mode), RESET
Input frequency
Input amplitude
Input voltage range
VIL3
SNS
0
1.1
V
VIL4
HOLD
0
0.4VDD
V
FIN1
XIN
4.0
8.0
MHz
FIN2
FMIN : VIN2, VDD1
10
150
MHz
FIN3
FMIN : VIN3, VDD1
10
130
MHz
FIN4
AMIN(H) : VIN3, VDD1
2.0
40
MHz
FIN5
AMIN(L) : VIN3, VDD1
0.5
10
MHz
FIN6
HCTR : VIN3, VDD1
0.4
12
MHz
FIN7
LCTR : VIN3, VDD1
100
500
kHz
1
3
FIN8
LCTR (in period measurement) : VIH2, VIL2, VDD1
VIN1
XIN
VIN2
VIN3
VIN6
ADI0 to ADI7
4.5
20×10
Hz
0.5
1.5
Vrms
FMIN
0.07
1.5
Vrms
FMIN, AMIN, HCTR, LCTR
0.04
1.5
Vrms
0
VDD
V
No.8011-3/14
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Electrical Characteristics in the allowable operating ranges
Parameter
Symbol
Ratings
Pins
min
Input high-level current
unit
typ
max
IIH1
XIN : VI = VDD = 5.0V
2.0
5.0
15
µA
IIH2
FMIN, AMIN, HCTR, LCTR : VI = VDD = 5.0V
4.0
10
30
µA
IIH3
PA, PB, PC, PD, PE, PF, PG, PH, PI, PK, PL, PM, PN, PO,
PP, PQ, PR, PS, PT-PORT, SNS, HOLD, RESET, HCTR,
3
µA
LCTR, INEO, SUBPD : VI = VDD = 5.0V
(with the ports PB, PC, PD, PE, PF, PG, PK, PL, PM, PN,
PP, PO, PQ, PR, PS, and PT-PORT set to input mode)
Input low-level current
IIL1
XIN : VI = VDD = VSS
2.0
5.0
15
µA
IIL2
FMIN, AMIN, HCTR, LCTR : VI = VDD = VSS
4.0
10
30
µA
IIL3
PA, PB, PC, PD, PE, PF, PG, PH, PI, PK, PL, PM, PN, PO,
PP, PQ, PR, PS, PT-PORT, SNS, HOLD, RESET, HCTR,
3
µA
LCTR, INEO, SUBPD : VI = VSS
(with the ports PB, PC, PD, PE, PF, PG, PK, PL, PM, PN,
PP, PO, PQ, PR, PS, and PT-PORT set to input mode)
Hysteresis
VH
PD, PE, PF, PG, PK-PORT, RESET, LCTR
0.1VDD
(in period measurement)
Output high-level voltage
VOH1
PB, PD, PE, PF, PG, PK, PL, PM, PN, PO, PP, PQ, PR,
PS, PT-PORT : IO = -1mA
Output low-level voltage
0.2VDD
VDD-1.0
V
VOH2
EO1, EO2, SUBPD : IO = -500µA
VDD-1.0
V
VOH3
XOUT : IO = -200µA
VDD-1.0
V
VOL1
PB, PD, PE, PF, PG, PK, PL, PM, PN, PO, PP PQ, PR,
PS, PT-PORT : IO = -1mA
Output off leakage
1.0
V
VOL2
EO1, EO2, SUBPD : IO = -500µA
1.0
V
VOL3
XOUT : IO = -200µA
1.5
V
VOL4
PC, PJ-PORT : IO = -5mA
2.0
V
IOFF1
PB, PD, PE, PF, PG, PK, PL, PM, PN, PO, PP, PQ, PR,
-3
3
µA
-100
100
nA
-5
5
µA
-1.5
+1.5
current
PS, PT-PORT
IOFF2
EO1, EO2, SUBPD
IOFF3
PC, PJ-PORT
A/D conversion error
ADI0 to ADI7
Rejected pulse width
PREJ1
Power down detection
VDET
SNS
2.7
voltage
Power supply current
V
3.0
LSB
50
µs
3.3
V
IDD1
VDD1 : FIN2 = 130MHz Ta = 25°C, X’tal : 4.5MHz
5
10
mA
IDD2
VDD1 : FIN2 = 130MHz Ta = 25°C, X’tal : 7.2MHz
5.5
11
mA
IDD3
VDD2 : Halt mode Ta = 25°C, X’tal : 4.5 MHz
IDD4
VDD2 : Halt mode Ta = 25°C, X’tal : 7.2MHz
IDD5
Backup mode (OSC stopped)
VDD = 5.5V, Ta = 25°C
IDD6
*1 (Fig. 1)
*2 (Fig. 2)
Backup mode (OSC stopped)
VDD = 2.5V, Ta = 25°C
*2 (Fig. 2)
0.45
mA
0.55
mA
5
µA
1
µA
*1 : Twenty instruction steps are executed every millisecond. The PLL, universal counter, and other functions are stopped.
No.8011-4/14
LC723781N/723782N/723783N/723784/723785
Test Circuits
Figure 1. IDD2 in Halt Mode
Figure 2. IDD3 and IDD4 in Backup Mode
Package Dimensions
unit : mm
3151A
No.8011-5/14
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Pin Assignment
No.8011-6/14
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Block Diagram
No.8011-7/14
LC723781N/723782N/723783N/723784/723785
Pin Description
Pin name
Pin No.
I/O
PA0
32
I
PA1
31
These ports are designed with a low threshold voltage.
PA2
30
Input is disabled in Backup mode.
PA3
29
PB0
28
PB1
27
The mode (input or output) is set using the IOS2 instruction.
PB2
26
Input is disabled and the pins go to the high-impedance state in
PB3
25
Backup mode.
I/O
Pin explanation
Equivalent circuit
Dedicated input ports.
General-purpose I/O ports.
These ports are set up as general-purpose input ports after a power
on reset.
PC0
24
PC1
23
I/O
General-purpose I/O ports (middle-voltage input and output).
The mode (input or output) is set using the IOS2 instruction.
PC2
22
External pull-up resistors are required since the output circuits are
PC3
21
open drain.
Input is disabled and the pins go to the high-impedance state in
Backup mode.
These ports are set up as general-purpose input ports after a power
on reset.
PD0/INT4
20
I/O
General-purpose I/O and external interrupt shared function ports.
PD1/INT5
19
The input formats are Schmitt inputs.
PD2
18
The external interrupt function is enabled when the external interrupt
PD3
17
enable flag is set.
• When used as general-purpose I/O ports :
The mode (input or output) is set in 1-bit units using the IOS2
instruction.
• When used as external interrupt pins :
The external interrupt functions are enabled by setting the
corresponding external interrupt enable flag (INT4EN or INT5EN).
In this case, the pins must be set to input mode in advance.
Input is disabled and the pins go to the high-impedance state in
Backup mode.
These ports are set up as general-purpose input ports after a power
on reset.
Continued on next page.
No.8011-8/14
LC723781N/723782N/723783N/723784/723785
Continued from preceding page.
Pin name
Pin No.
I/O
PE0
16
I/O
Pin explanation
PE1/SCK2
15
The input formats are Schmitt inputs. The PE1/SCK2 and PE2/SO2
PE2/SO2
14
pins can be switched to function as open drain outputs.
PE3/SI2
13
The IOS1 instruction is used to switch between the general-purpose
PF0
12
I/O port and serial I/O port functions.
PF1/SCK1
11
• When used as general-purpose I/O ports :
PF2/SO1
10
The pins are set to the general-purpose I/O port function using the
PF3/SI1
9
IOS1 instruction.
PG0
8
The mode (input or output) is set in 1-bit units using the IOS1
PG1/SCK0
7
PG2/SO0
6
PG3/SI0
5
Equivalent circuit
General-purpose I/O ports with shared functions as serial I/O ports.
instruction
• When used serial I/O ports :
The pins are set to the serial I/O port function using the IOS1
instruction.
[Pin states when set to the serial I/O port function]
PE0, PF0, PG0 … General-purpose I/O
PE1, PF1, PG1 … SCK input or output
PE2, PF2, PG2 … SO output
PE3, PF3, PG3 … SI input
The PE1/SCK2 and PE2/SO2 pins can be switched to function as
open drain outputs with the IOS2 instruction. When using this circuit
type, the external pull-up resistors must be connected to the same
power supply as that used by the IC.
Input is disabled and the pins go to the high-impedance state in
Backup mode.
These ports are set up as general-purpose input ports after a power
on reset.
XIN
1
I
XOUT
100
O
EO1
98
O
EO2
97
Connections for 4.5MHz/7.2MHz crystal oscillator element
Main charge pump outputs.
These pins output a high level when the frequency of the local
oscillator divided by n is higher than that of the reference frequency,
and they output a low level when that frequency is lower.
They go to the high-impedance state when the frequencies match.
These pins go to the high-impedance state in Backup mode, after a
power on reset, and in the PLL stopped state.
VDDPORT
VDDPLL
39
-
Power supply connections.
93
The VDDPORT and VSSPORT pins are mainly supply power for the
VSSCPU
VSSPORT
VSSADC
4
peripheral I/O blocks.
40
The VDDPLL and VSSPLL pins are mainly for the PLL circuits and
81
the regulator.
VSSPLL
96
The VSSCPU pin is mainly used by the CPU block.
The VSSADC pin is mainly used by the ADC block.
Since all the VDD and VSS pins are independent, all must be
connected to the same power supply.
VREG
3
O
Internal low voltage output.
Connect a bypass capacitor to this pin.
Continued on next page.
No.8011-9/14
LC723781N/723782N/723783N/723784/723785
Continued from preceding page.
Pin name
Pin No.
I/O
FMIN
95
I
Pin explanation
Equivalent circuit
FM VCO (local oscillator) input.
This pin is selected with CW1 in the PLL instruction.
The signal input to this pin must be capacitor coupled.
Input is disabled in Backup mode, after a power on reset, and in the
PLL stopped state.
AMIN
94
I
AM VCO (local oscillator) input.
This pin is selected and the band set with CW1 (b1, b0) in the PLL
instruction.
b1
b0
Band
1
0
2 to 40MHz (SW, AM upconversion)
1
1
0.5 to 10MHz (MW, LW)
The signal input to this pin must be capacitor coupled.
Input is disabled in Backup mode, after a power on reset, and in the
PLL stopped state.
SUBPD
92
I/O
Sub-charge pump output and general-purpose input shared function
port.
The IOS2 instruction is used for switching between the sub-charge
pump output and general-purpose input functions.
• When used as the sub-charge pump output :
The sub-charge pump output function is set up with the IOS2
instruction.
A high-speed locking circuit can be formed by using this pin in
conjunction with the main charge pump.
The sub-charge pump is controlled using the DZC instruction.
b3
b2
0
0
0
1
1
0
1
1
Operation
High impedance
Only operates when the PLL is unlocked
(450kHz)
Only operates when the PLL is unlocked
(900kHz)
Normal operation
• When used as a general-purpose input :
The general-purpose input function is set up with the IOS2
instruction.
Data is read from the port using the INR instruction.
This pin goes to the high-impedance state in Backup mode, after a
power on reset, and in the PLL stopped state.
INEO
91
I
Dedicated input port.
Data is read from the port using the INR instruction
Input is disabled in Backup mode.
Continued on next page.
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Continued from preceding page.
Pin name
Pin No.
I/O
Pin explanation
HCTR
90
I
Universal counter and general-purpose input shared function input port.
Equivalent circuit
The IOS1 instruction is used for switching between the universal
counter and general- purpose input functions.
• When used for frequency measurement :
The universal counter function is set up with the IOS1 instruction.
The counter is controlled using UCS and UCC instructions.
Since this pin functions as an AC amplifier in this mode, the input
signal must be input with capacitor coupling.
• When used as a general-purpose input pin :
The general-purpose input function is set up with the IOS1
instruction.
Data is read from the port using the INR (b0) instruction.
Input is disabled in Backup mode. (The input pin will be pulled down.)
The universal counter function is selected after a power on reset.
LCTR
89
I
Universal counter (frequency or period measurement) and generalpurpose input shared function input port.
The IOS1 instruction is used for switching between the universal
counter and general-purpose input functions.
• When used for frequency measurement :
The universal counter function is set up with the IOS1 instruction.
Set up LCTR frequency measurement mode with the UCS
instruction, and control operation with the UCC instruction.
Since this pin functions as an AC amplifier in this mode, the input
signal must be input with capacitor coupling.
• When used for period measurement :
The universal counter function is set up with the IOS1 instruction.
Set up LCTR frequency measurement mode with the UCS
instruction, and control operation with the UCC instruction.
Since the bias feedback resistor is disconnected in this mode, the
input signal must be input with DC coupling.
• When used as a general-purpose input pin :
The general-purpose input port function is set up with the IOS1
instruction.
Data is read from the port using the INR (b1) instruction.
Input is disabled in Backup mode. (The input pin will be pulled down.)
The universal counter function (HCTR frequency measurement mode)
is selected after a power on reset.
SNS
88
I
Voltage sense and general-purpose input shared function port.
This input circuit is designed with a low input threshold voltage.
• When used as a voltage sense input :
The pin is used to test for power failures on the return from Backup
mode.
Application can test this condition using the internal SNS flip-flop.
The SNS flip-flop can be tested with the TST instruction.
(This usage requires external components, capacitors and resistors.
For the sample application circuit, see the user’s manual.)
• When used as a general-purpose input port :
When used as a general-purpose input port the pin state can be
tested with the TST instruction.
Unlike the other input ports, input to this pin is not disabled in Backup
mode and after a power on reset. As a result, through currents must
be taken into account when designing applications that use this pin as
a general-purpose input.
HOLD
87
I
Power supply monitor (with interrupt function)
This is designed with a high input threshold voltage.
This pin is normally connected to the ACC line and used for power off
detection.
When a power off state is detected, the HOLDON flag and the hold
interrupt request flag will be set.
To enter Backup mode, execute a CKSTP instruction when the HOLD
pin is low. Set this pin high to clear Backup mode.
Continued on next page.
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Continued from preceding page.
Pin name
Pin No.
I/O
RESET
86
I
Pin explanation
Equivalent circuit
System reset pin.
When the CPU is operating or in Halt mode, the system is reset when
this pin is held low for at least one machine cycle. Execution starts
with the PC pointing to location 0. At this time the SNS flip-flop is set.
A low level must be applied for at least 50ms when power is first
applied.
PH0/ADI0
85
PH1/ADI1
84
The IOS1 instruction is used to switch between the general-purpose
PH2/ADI2
83
input and the A/D converter input functions.
PH3/ADI3
82
• When used as general-purpose input ports :
PI0/ADI4
81
The general-purpose input port function is set up with the IOS1
PI1/ADI5
80
instruction. (In bit units)
PI2/ADI6
79
PI3/ADI7
78
I
General-purpose input and A/D converter input shared function ports.
• When used as A/D converter input pins :
The A/D converter input port function is set up with the IOS1
instruction. (In bit units)
The pin whose voltage is to be converted is specified with the IOS1
instruction, and the conversion is started with UCC instruction.
Note : Since input is disabled for ports specified for the ADI function,
executing an input instruction for such a port will always return
a low level.
Input is disabled in Backup mode.
These ports are set up as general-purpose input ports after a power
on reset.
O
General-purpose output ports (high-voltage output)
PJ0
76
PJ1
75
Since these are open-drain output circuits, external pull-up resistors
PJ2
74
are required.
PJ3
73
The internal transistors are turned off (resulting in a high-level output)
in Backup mode and after a power on reset.
PK0/INT0
72
PK1/INT1
71
I/O
General-purpose I/O and external interrupt shared function ports.
The input formats are Schmitt inputs.
PK2/INT2
70
The external interrupt function is enabled when the external interrupt
PK3/INT3
69
enable flag is set.
• When used as general-purpose I/O ports :
The mode (input or output) is set in 1-bit units using the IOS1
instruction.
• When used as external interrupt pins :
The external interrupt functions are enabled by setting the
corresponding external interrupt enable flag (INT0EN through
INT3EN). Here, the pins must be set to input mode in advance.
Input is disabled and the pins go to the high-impedance state in
Backup mode.
These ports are set up as general-purpose input ports after a power
on reset.
Continued on next page.
No.8011-12/14
LC723781N/723782N/723783N/723784/723785
Continued from preceding page.
Pin name
Pin No.
I/O
PL0 to 3
68 to 61
I/O
PM0 to 3
Pin explanation
Equivalent circuit
General-purpose I/O ports
The mode is switched between input and output with the IOS
instruction.
Input is disabled and the pins go to the high-impedance state in
Backup mode.
These ports are set up as general-purpose input ports after a power
on reset.
PN0/BEEP
60
I/O
General-purpose I/O port and beep tone output shared function ports.
PN1
59
The IOS2 instruction is used to switch between the general-purpose
PN2
58
I/O port and the beep tone output functions.
PN3
57
• When used as general-purpose I/O ports :
The general-purpose I/O port function is set up with the IOS2
instruction.
(Pins PN1 through PN3 are dedicated general-purpose output pins.)
• When used as the beep tone output pin :
The beep tone output function is set up with the IOS2 instruction.
The frequency is set up with the BEEP instruction.
When this pin is used as the beep tone output pin, executing an
output instruction for this pin only sets the internal latch and has no
influence on the output.
Input is disabled and the pins go to the high-impedance state in
Backup mode.
These ports are set up as general-purpose input ports after a power
on reset.
PO0 to 3
56 to 49
I/O
PP0 to 3
General-purpose I/O ports
The mode is switched between input and output with the IOS
instruction.
Input is disabled and the pins go to the high-impedance state in
Backup mode.
These ports are set up as general-purpose input ports after a power
on reset.
PQ0 to 3
48 to 41
PR0 to 3
38 to 33
I/O
General-purpose I/O ports.
The mode is switched between input and output with the IOS
PS0 to 3
instruction, and data is input with the INR instruction and output with
PT0 to 3
the OUTR instruction.
The SPB, RPB, TPT, and TPF instruction cannot be used with these
ports.
Input is disabled and the pins go to the high-impedance state in
Backup mode.
These ports are set up as general-purpose input ports after a power
on reset.
TEST1
99
LSI test pins.
TEST2
2
These pins must be connected to GND.
No.8011-13/14
LC723781N/723782N/723783N/723784/723785
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PS No.8011-14/14