Ordering number : ENN*7023 CMOS IC LC74982W LCD TV Scan Converter IC Preliminary Applications • LCD TVs, monitors, and projectors • PDP displays • Car television and car video monitors Package Dimensions unit: mm 3210-SQFP208 [LC74982W] 30.6 0.5 28.0 156 105 208 53 1 (0.5) (1.25) 30.6 104 157 28.0 • NTSC and PAL input support: 24-bit or 16-bit digital YCbCr signal input • PC input support: Personal computer 24-bit digital RGB signal input at resolutions up to XGA • DTV (480i / 480p) input: 24-bit or 16-bit digital YCbCr input • Two-phase progressive scan RGB 18-bit (24 bit) and 36bit (48 bit) signal output • Simulated increased color-depth processing at 6-bit mode. Values in parentheses apply in 8-bit mode. • YCbCr to RGB conversion • Interlaced to progressive scan conversion • Resolution conversion (enlargement) • Variable display size and display position (independently settable in the horizontal and vertical directions) • Image quality adjustments: brightness, contrast, color, sharpness, color phase, black balance, and white balance • Supply voltage: 3.3 V (input pins are 5 V tolerant) • Maximum operating frequency: 65.0 MHz • Package: SQFP208 0.2 0.15 52 3.8max Features Specifications (3.2) The LC74982W is an LCD display scan converter IC that converts NTSC and PAL TV signals to XGA resolution. The video signal-processing circuits required to implement an LCD TV set can be easily formed by combining this IC with a digital decoder, a microcontroller, and an LCD panel. Since this IC does not require an external frame memory for resolution conversion, it can contribute to minimizing total costs. As additional functionality, it also provides inputs for personal computer video (up to XGA) and digital TV (480p/480i). Since LC74982W operation is based on expansion (resolution increasing) processing, depending on the input resolution, it can also support use of, for example, 800 × 600 and 800 × 480 dot resolution LCD panels. Thus the LC74982W can be used in a wide range of applications. • Built-in γ correction (LUT technique. Each 8-bit R, G, and B signal is independently programmable.) • Built-in OSD function (8 colors, 253 characters) • I2C bus interface • Constant frame-rate processing (identical frame periods in the input and output signals) adopted so that no external memory is required. 0.35 Overview SANYO: SQFP208 Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft’s control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein. SANYO Electric Co.,Ltd. Semiconductor Company TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN 91801TN (OT) No. 7023-1/14 LC74982W I/O Specifications Input Signal Overview Signal type Video signals Sync signals Pin No. Pin 6 to 13 YIN7 to 0 54 to 61 RIN7 to 0 16 to 23 UIN7 to 0 64 to 71 GIN7 to 0 26 to 33 VIN7 to 0 74 to 81 BIN7 to 0 Description Y/Y/R • NTSC, PAL, and DTV (480i and 480p) inputs YCbCr signals conform to the CCIR 601 standard. The YC C signal is a multiplexed CbCr signal (4:2:2). C/Cb/G • PC input (up to XGA) –/Cr/B 90 HITV 91 VITV NTSC/PAL horizontal sync signal 92 HIDTV DTV horizontal sync signal 93 VIDTV DTV vertical sync signal 94 HIPC PC horizontal sync signal 95 VIPC PC vertical sync signal 96 BLKIH Horizontal enable • Input with the same logic. The polarity can be inverted internally. 97 BLKIV Vertical enable • A composite video signal can be input to BLKIH. (BLKIV must be tied high in this case.) NTSC/PAL vertical sync signal Data enable signals Pixel clocks Notes 36 CLKITV 39 CLKIDTV 42 CLKIPC 167 XTAL • Three independent systems for both horizontal and vertical sync signals • Any input polarity may be used. Internal automatic-discrimination. NTSC/PAL clock • Three independent input systems DTV clock PC clock Display clock • Fixed frequency crystal oscillator (65 MHz maximum) Output Signal Overview Signal type Pin No. Pin 106 to 111 ROEVEN5 to 0 Even pixels, red 114 to 119 GOEVEN5 to 0 Even pixels, green Video signals 122 to 127 BOEVEN5 to 0 Even pixels, blue in 6-bit output mode 130 to 135 ROODD5 to 0 Odd pixels, red 138 to 143 GOODD5 to 0 Odd pixels, green 146 to 151 BOODD5 to 0 Odd pixels, blue ROEVEN7 to 0 Even pixels, red GOEVEN7 to 0 Even pixels, green • Each of the RGB channels is an 8-bit 2-phase signal. BOEVEN7 to 0 Even pixels, blue • The output mode can be switched to single-phase output mode. ROODD7 to 0 Odd pixels, red 182 to 189 GOODD7 to 0 Odd pixels, green 192 to 199 BOODD7 to 0 Odd pixels, blue 162 HOUT Horizontal sync signal 163 VOUT Vertical sync signal 102 BLKHOUT Horizontal enable 103 BLKVOUT Vertical enable 106 to 111, 114, 115 116 to 119, 122 to 125 Video signals 126, 127, in 8-bit output mode 130 to 135 138 to 143, 146, 147 Sync signals Data enable signals Pixel clocks 154 DCLK1 155 DCLK1B 158 DCLK2 159 DCLK2B Description Single-phase clock Single-phase clock (inverted) Two-phase clock Two-phase clock (inverted) Notes • Each of the RGB channels is an 6-bit 2-phase signal. • The output mode can be switched to single-phase output mode. (Output from the ODD pin) (Output from the ODD pin) • The sync period, position, and polarity can be set. • A composite sync signal can be output from VOUT. • The enable period and the polarity can be set. • A composite signal can be output from BLKVOUT. • Outputs the same frequency as that of the crystal oscillator. • Outputs a frequency 1/2 that of the crystal oscillator. No. 7023-2/14 LC74982W Control Signal Overview Signal type Three-wire bus I2C-bus Pin No. Pin 172 AICS Chip select Description Notes 173 AIDA Data bus 174 AICK Bus clock 175 SDA Data bus • Used to set the internal control registers and to output internal status information. 176 SCL Bus clock • The slave address is “0111000+ (R/W)”. • Used for OSD control and γ correction characteristics settings. Specifications Absolute Maximum Ratings at VSS = 0 V Parameter Symbol Maximum supply voltage Input voltage Output voltage Conditions Ratings –0.3 to +4.6 V VI –0.5 to + 5.5 V VO Allowable power dissipation Unit VDD max Pd max –0.3 to VDD + 0.3 V 0.9 W Ta = 70°C Storage temperature Tstg –55 to +125 °C Operating temperature Topr –30 to +70 °C Note: While the standard operating temperature is –30 to +70°C, for applications such as automotive applications, it can also be used over the range –40 to +85°C. Note, however, that the value of the allowable power dissipation differs somewhat between these two cases. Contact your SANYO representative for details if you need to use this device with the latter (wider) operating temperature range. Allowable Operating Ranges at Ta = –30 to +70°C Parameter Symbol Conditions Ratings min typ Unit max Supply voltage VDD 3.0 3.3 3.6 V Input voltage range VIN 0 — 5.5 V I/O Pin Capacitances at Ta = 25°C, VDD = VI = 0 V Parameter Input pins Output pins Bidirectional pins Symbol Conditions Ratings min typ Unit max CIN f = 1 MHz — — 10 pF COUT f = 1 MHz — — 10 pF CI/O f = 1 MHz — — 10 pF DC Characteristics at Ta = –30 to +70°C, VDD = 3.0 to 3.6 V Parameter Input high-level voltage Input low-level voltage Symbol VIH VIL Input high-level current IIH Input low-level current IIL Output high-level voltage Output low-level voltage VOH VOL Output leakage current IOZ Pull-down resistance RDN Quiescent current* IDD Conditions CMOS level Ratings min typ Unit max 0.7 VDD — — V 0.75 VDD — — V CMOS level — — 0.2 VDD V CMOS level Schmitt — — 0.15 VDD V –10 — +10 µA CMOS level Schmitt VI = VDD VI = VDD, with pull-down resistors attached. 10 — 100 µA –10 — +10 µA Type B4, IOH = –2 mA VDD – 0.8 — — V Type B8, IOH = –4 mA VDD – 0.8 — — V Type B12, IOH = –6 mA VDD – 0.8 — — V Type B4, IOL = 2 mA — — 0.4 V Type B8, IOL = 4 mA — — 0.4 V Type B12, IOL = 6 mA — — 0.4 V –10 — +10 µA 35 70 140 kΩ — — 100 µA VI = VSS In the high-impedance output state Outputs open, VI = VSS or VDD Note: * Certain of the input pins include built-in pull-down resistors. The quiescent current drain cannot be guaranteed in certain situations due to the structure of these circuits. No. 7023-3/14 LC74982W DVDD DCLK1B DCLK1 DVSS DVDD BOODD5 (TEST3) BOODD4 (TEST2) BOODD3 (TEST1) BOODD2 (TEST0) BOODD1 (ROODD7) BOODD0 (ROODD6) DVSS DVDD GOODD5 (ROODD5) GOODD4 (ROODD4) GOODD3 (ROODD3) GOODD2 (ROODD2) GOODD1 (ROODD1) GOODD0 (ROODD0) DVSS DVDD ROODD5 (BOEVEN7) ROODD4 (BOEVEN6) ROODD3 (BOEVEN5) ROODD2 (BOEVEN4) ROODD1 (BOEVEN3) ROODD0 (BOEVEN2) DVSS DVDD BOEVEN5 (BOEVEN1) BOEVEN4 (BOEVEN0) BOEVEN3 (BOEVEN7) BOEVEN2 (BOEVEN6) BOEVEN1 (BOEVEN5) BOEVEN0 (BOEVEN4) DVSS DVDD GOEVEN5 (GOEVEN3) GOEVEN4 (GOEVEN2) GOEVEN3 (GOEVEN1) GOEVEN2 (GOEVEN0) GOEVEN1 (ROEVEN7) GOEVEN0 (ROEVEN6) DVSS DVDD ROEVEN5 ROEVEN4 ROEVEN3 ROEVEN2 ROEVEN1 ROEVEN0 DVSS Pin Assignment 105 156 157 DVSS DCLK2 DCLK2B DVDD DVSS HOUT VOUT VIRST DVDD DVSS XTAL DVDD DVSS EXCTR MUTE AICS AIDA AICK SDA SCL PDOWN1 PDOWN2 CLKIO DVDD DVSS TSTOA7 (GOODD0) TSTOA6 (GOODD1) TSTOA5 (GOODD2) TSTOA4 (GOODD3) TSTOA3 (GOODD4) TSTOA2 (GOODD5) TSTOA1 (GOODD6) TSTOA0 (GOODD7) DVDD DVSS TSTOB7 (BOODD0) TSTOB6 (BOODD1) TSTOB5 (BOODD2) TSTOB4 (BOODD3) TSTOB3 (BOODD4) TSTOB2 (BOODD5) TSTOB1 (BOODD6) TSTOB0 (BOODD7) TSTMOD3 TSTMOD2 TSTMOD1 TSTMOD0 TSTSUB3 TSTSUB2 TSTSUB1 TSTSUB0 DVDD 208 155 150 145 140 135 130 125 120 115 110 105 160 100 165 95 170 90 175 85 LC74982W (Top view) 180 80 185 75 190 70 195 65 200 60 205 5 10 15 20 25 30 35 40 45 55 50 104 DVDD BLKVOUT BLKHOUT RST DVSS DVDD PLLH BLKIV BLKIH VIPC HIPC VIDTV HIDTV VITV HITV DVSS DVDD CLPCR CLPCB CLPY CLPP DVSS DVDD BIN0 BIN1 BIN2 BIN3 BIN4 BIN5 BIN6 BIN7 DVSS DVDD GIN0 GIN1 GIN2 GIN3 GIN4 GIN5 GIN6 GIN7 DVSS DVDD RIN0 RIN1 RIN2 RIN3 RIN4 RIN5 RIN6 RIN7 DVSS DVSS OSDRIN OSDGIN OSDBIN OSDEN YIN7 YIN6 YIN5 YIN4 YIN3 YIN2 YIN1 YIN0 DVDD DVSS UIN7 UIN6 UIN5 UIN4 UIN3 UIN2 UIN1 UIN0 DVDD DVSS VIN7 VIN6 VIN5 VIN4 VIN3 VIN2 VIN1 VIN0 DVDD DVSS CLKITV DVDD DVSS CLKIDTV DVDD DVSS CLKIPC DVDD SCANMOD SCANEN AVSS PDO AVDD AVSS VCOCNT VOCORNG AVDD 53 1 52 * ( ): Values in parentheses apply in 8-bit mode. No. 7023-4/14 LC74982W Pin Functions Pin No. Pin I/O type I/O Type Connection GND Notes 1 DVSS P 2 OSDRIN I g74980m03 Caption OSD microcontroller OSD red input (NTSC only) 3 OSDGIN I g74980m03 Caption OSD microcontroller OSD green input (NTSC only) 4 OSDBIN I g74980m03 Caption OSD microcontroller OSD blue input (NTSC only) 5 OSDEN I g74980m03 Caption OSD microcontroller OSD data enable (NTSC only) 6 YIN7 I g74980m03 Digital decoder 7 YIN6 I g74980m03 or 8 YIN5 I g74980m03 ADC 9 YIN4 I g74980m03 or 10 YIN3 I g74980m03 Digital Interface 11 YIN2 I g74980m03 12 YIN1 I g74980m03 13 YIN0 I g74980m03 14 DVDD P Power supply 15 DVSS P GND 16 UIN7 I g74980m03 Digital decoder 17 UIN6 I g74980m03 or 18 UIN5 I g74980m03 ADC 19 UIN4 I g74980m03 or UIN3 I g74980m03 Digital Interface 21 UIN2 I g74980m03 UIN1 I g74980m03 g74980m03 MSB Y signal input or R signal input LSB 20 22 Digital system ground Digital system power supply: 3.3 V Digital system ground MSB C (CbCr multiplexed) signal input or Cb signal input or G signal input 23 UIN0 I 24 DVDD P Power supply LSB 25 DVSS P GND 26 VIN7 I g74980m03 Digital decoder 27 VIN6 I g74980m03 or 28 VIN5 I g74980m03 ADC Digital system power supply: 3.3 V Digital system ground MSB Cr signal input or 29 VIN4 I g74980m03 or 30 VIN3 I g74980m03 Digital Interface 31 VIN2 I g74980m03 32 VIN1 I g74980m03 33 VIN0 I g74980m03 34 DVDD P Power supply 35 DVSS P GND 36 CLKITV I 37 DVDD P Power supply 38 DVSS P GND Digital system ground 39 CLKIDTV I PLL DTV clock input 40 DVDD P Power supply 41 DVSS P GND 42 CLKIPC I 43 DVDD P 44 SCANMOD I g74980m03 Open Scan test mode 45 SCANEN I g74980m03 Open Scan test enable 46 AVSS P GND Analog system ground 47 PDO O zwp3vpll3 Loop filter 48 AVDD P Power supply 49 AVSS P GND 50 VCOCNT I g74100m06 51 VCORNG I g74100m06 52 AVDD P g74980m05 g74980m05 g74980m05 B signal input LSB Digital decoder Digital interface Power supply Loop filter Resistor Power supply Digital system power supply: 3.3 V Digital system ground TV clock input (data rate) Digital system power supply: 3.3 V Digital system power supply: 3.3 V Digital system ground PC clock input (data rate) Digital system power supply: 3.3 V Charge pump output (open) Analog system power supply: 3.3 V Analog system ground VCO control input (Connect to AVSS.) VCO bias resistor input (Connect to AVSS.) Analog system power supply: 3.3 V Continued on next page. No. 7023-5/14 LC74982W Continued from preceding page. I/O type Pin No. Pin 53 DVSS P 54 RIN7 I g74980m03 Digital Decoder 55 RIN6 I g74980m03 or 56 RIN5 I g74980m03 ADC 57 RIN4 I g74980m03 or 58 RIN3 I g74980m03 Digital Interface 59 RIN2 I g74980m03 60 RIN1 I g74980m03 61 RIN0 I g74980m03 62 DVDD P Power supply 63 DVSS P GND 64 GIN7 I g74980m03 Digital Decoder 65 GIN6 I g74980m03 or 66 GIN5 I g74980m03 ADC I/O Type Connection GND 67 GIN4 I g74980m03 or GIN3 I g74980m03 Digital Interface 69 GIN2 I g74980m03 GIN1 I g74980m03 g74980m03 Digital system ground MSB Y signal input or R signal input LSB 68 70 Notes Digital system power supply: 3.3 V Digital system ground MSB C (CbCr multiplexed) signal input or Cb signal input or G signal input 71 GIN0 I 72 DVDD P Power supply LSB 73 DVSS P GND 74 BIN7 I g74980m03 Digital Decoder 75 BIN6 I g74980m03 or 76 BIN5 I g74980m03 ADC 77 BIN4 I g74980m03 or 78 BIN3 I g74980m03 Digital Interface 79 BIN2 I g74980m03 80 BIN1 I g74980m03 81 BIN0 I g74980m03 82 DVDD P Power supply 83 DVSS P GND Digital system ground 84 CLPP O POB4 ADC Clamp pulse 85 CLPY O POT4 ADC Y clamp level 86 CLPCB O POT4 ADC Cb clamp level POT4 ADC Cr clamp level Digital system power supply: 3.3 V Digital system ground MSB Cr signal input or B signal input LSB Digital system power supply: 3.3 V 87 CLPCR O 88 DVDD P Power supply 89 DVSS P GND 90 HITV I g74980m04 TV decoder TV horizontal synchronizing signal input 91 VITV I g74980m04 TV decoder TV vertical synchronizing signal input 92 HIDTV I g74980m04 Digital interface 93 VIDTV I g74980m04 Digital interface DTV vertical synchronizing signal input 94 HIPC I g74980m04 Digital interface PC horizontal sync signal input PC vertical sync signal input Digital system power supply: 3.3 V Digital system ground DTV horizontal synchronizing signal input 95 VIPC I g74980m04 Digital interface 96 BLKIH I g74980m02 Digital interface Horizontal blanking signal input (composite blanking signal) 97 BLKIV I g74980m02 Digital interface Vertical blanking signal input (Held high in composite mode) 98 PLLH O POB4 99 DVDD P Power supply 100 DVSS P GND 101 RST I g74980m01 Initialization circuit 102 BLKHOUT O POB8 LCD module Horizontal data enable 103 BLKVOUT O POB8 LCD module Vertical data enable or composite data enable 104 DVDD P Power supply Digital system power supply: 3.3 V PLL PLL internal divider output Digital system power supply: 3.3 V Digital system ground System reset (reset to low) Continued on next page. No. 7023-6/14 LC74982W Continued from preceding page. Pin No. Pin I/O type I/O Type 105 DVSS P 106 ROEVEN0 O POB4 107 ROEVEN1 O POB4 108 ROEVEN2 O POB4 109 ROEVEN3 O POB4 110 ROEVEN4 O POB4 111 ROEVEN5 O POB4 112 DVDD P Connection GND LCD module DVSS P 114 GOEVEN0 (ROEVEN6) O POB4 115 GOEVEN1 (ROEVEN7) O POB4 GOEVEN2 (GOEVEN0) O POB4 117 GOEVEN3 (GOEVEN1) O POB4 118 GOEVEN4 (GOEVEN2) O POB4 119 GOEVEN5 (GOEVEN3) O POB4 120 DVDD P LSB (LSB) (Red signal output (even)) MSB GND 116 Digital system ground Red signal output (even) Power supply 113 Notes LCD module Digital system power supply: 3.3 V Digital system ground LSB (MSB) Green signal output (even) MSB Power supply GND (LSB) (Green signal output (even)) Digital system power supply: 3.3 V 121 DVSS P 122 BOEVEN0 (GOEVEN4) O POB4 123 BOEVEN1 (GOEVEN5) O POB4 124 BOEVEN2 (GOEVEN6) O POB4 (MSB) 125 BOEVEN3 (GOEVEN7) O POB4 (LSB) 126 BOEVEN4 (BOEVEN0) O POB4 127 BOEVEN5 (BOEVEN1) O POB4 128 DVDD P LCD module Digital system ground LSB Blue signal output (even) MSB Power supply GND Digital system power supply: 3.3 V 129 DVSS P 130 ROODD0 (BOEVEN2) O POB4 131 ROODD1 (BOEVEN3) O POB4 Red signal output (odd) 132 ROODD2 (BOEVEN4) O POB4 or 133 ROODD3 (BOEVEN5) O POB4 Red signal single-phase output 134 ROODD4 (BOEVEN6) O POB4 135 ROODD5 (BOEVEN7) O POB4 136 DVDD P LCD module Digital system ground LSB MSB Power supply GND (B signal output (even)) (MSB) Digital system power supply: 3.3 V 137 DVSS P 138 GOODD0 (ROODD0) O POB4 139 GOODD1 (ROODD1) O POB4 Green signal output (odd) 140 GOODD2 (ROODD2) O POB4 or 141 GOODD3 (ROODD3) O POB4 Green signal single-phase output (Red signal output (odd) 142 GOODD4 (ROODD4) O POB4 143 GOODD5 (ROODD5) O POB4 LCD module Digital system ground LSB (LSB) or MSB 144 DVDD P Power supply 145 DVSS P GND 146 BOODD0 (ROODD6) O POB4 147 BOODD1 (ROODD7) O POB4 Blue signal output (odd) 148 BOODD2 (TEST0) O POB4 or 149 BOODD3 (TEST1) O POB4 150 BOODD4 (TEST2) O POB4 151 BOODD5 (TEST3) O POB4 LCD module (OPEN) Red signal single-phase output) Digital system power supply: 3.3 V Digital system ground LSB Blue signal single-phase output (MSB) (Test output (Outputs a fixed low level.)) MSB 152 DVDD P Power supply 153 DVSS P GND 154 DCLK1 O POB12 155 DCLK1B O POB12 156 DVDD P LCD module Digital system power supply: 3.3 V Digital system ground Data clock 1 (for single-phase data output) LCD module Inverted data clock 1 (for single-phase data output) Power supply Digital system power supply: 3.3 V Continued on next page. No. 7023-7/14 LC74982W Continued from preceding page. Pin No. Pin I/O type I/O Type 157 DVSS P 158 DCLK2 O POB12 159 DCLK2B O POB12 160 DVDD P Connection GND — — Power supply Notes Digital system ground Data clock 2 (for two-phase data output) Inverted data clock 2 (for two-phase data output) Digital system power supply: 3.3 V 161 DVSS P GND Digital system ground 162 HOUT O POB8 LCD module Horizontal sync output 163 VOUT O POB8 LCD module Vertical synchronizing signal output or composite synchronizing signal output POB4 164 VIRST O 165 DVDD P 166 DVSS P 167 XTAL I 168 DVDD P — Power supply GND g74980m01 VCO Power supply GND Crystal oscillator reset Digital system power supply: 3.3 V Digital system ground Crystal oscillator circuit output Digital system power supply: 3.3 V 169 DVSS P 170 EXCTR O POB4 — Digital system ground 171 MUTE I g74980m02 Microcontroller Mute control input (mute to low) 172 AICS I g74980m02 Microcontroller 3-wire bus control chip select 173 AIDA I g74980m02 Microcontroller 3-wire bus control bus data 174 AICK I g74980m02 Microcontroller 3-wire bus control bus clock 175 SDA B g74980m06 Microcontroller I2C control data 176 SCL I g74980m02 Microcontroller I2C control clock External control output (output controlled over the I2C bus) 177 PDOWN1 I g74980m01 — Must be tied high during normal operation. 178 PDOWN2 I g74980m01 — Must be tied high during normal operation. 179 CLKI0 O POB12 180 DVDD P — Power supply 181 DVSS P 182 TSTOA7 (GOODD0) O POB4 GND 183 TSTOA6 (GOODD1) O POB4 184 TSTOA5 (GOODD2) O POB4 185 TSTOA4 (GOODD3) O POB4 186 TSTOA3 (GOODD4) O POB4 187 TSTOA2 (GOODD5) O POB4 188 TSTOA1 (GOODD6) O POB4 189 TSTOA0 (GOODD7) O POB4 190 DVDD P OPEN DVSS P 192 TSTOB7 (BOODD0) O POB4 193 TSTOB6 (BOODD1) O POB4 194 TSTOB5 (BOODD2) O POB4 TSTOB4 (BOODD3) O POB4 196 TSTOB3 (BOODD4) O POB4 197 TSTOB2 (BOODD5) O POB4 198 TSTOB1 (BOODD6) O POB4 199 TSTOB0 (BOODD7) O POB4 200 TSTMOD3 I g74980m03 201 TSTMOD2 I g74980m03 202 TSTMOD1 I g74980m03 203 TSTMOD0 I g74980m03 204 TSTSUB3 I g74980m03 205 TSTSUB2 I g74980m03 206 TSTSUB1 I g74980m03 207 TSTSUB0 I g74980m03 208 DVDD P MSB (LSB) Test outputs (G signal output (odd) or G signal single-phase output) LSB GND 195 Digital system ground (LCD module) Power supply 191 Input system clock output Digital system power supply: 3.3 V OPEN (MSB) Digital system power supply: 3.3 V Digital system ground MSB (LSB) Test outputs (B signal output (odd) (LCD module) or B signal single-phase output) LSB (MSB) OPEN Test mode (Must be left open in normal operation.) OPEN Test sub-mode (Must be left open in normal operation.) Power supply Digital system power supply: 3.3 V No. 7023-8/14 LC74982W Pin Type I/O type Applicable pins RST g74980m01 PDOWN1 to 2 Function Equivalent circuit 3 to 5 V voltage handling input XTAL A13541 AICS, AIDA, AICK g74980m02 SCL BLKIH, BLKIV 3 to 5 V voltage handling Schmitt input MUTE A13542 OSDRIN, OSDGIN, OSDBIN, OSDEN YIN0 to 7, UIN0 to 7, VIN0 to 7 g74980m03 SCANMOD, SCANEN RIN0 to 7, GIN0 to 7, BIN0 to 7 3 to 5 V voltage handling pull-down input TSTMOD0 to 3, TSTSUB0 to 3 A13543 Leave open when unused. HITV, VITV g74980m04 HIDTV, VIDTV HIPC, VIPC 3 to 5 V voltage handling pull-down Schmitt input A13544 CLKITV g74980m05 CLKIDTV 3 to 5 V voltage handling OE input CLKIPC A13545 CLPP, PLLH, POB4 POB8 POB12 POT4 ROEVEN0 to 5 (7), GOEVEN0 to 5 (7), BOEVEN0 to 5 (7), ROODD0 to 5 (7), GOODD0 to 5 (7), BOODD0 to 5 (7), VIRST, EXCTR, TST0A0 to 7, TST0B0 to 7, (TEST0 to 3) BLKHOUT, BLKVOUT HOUT, VOUT DCLK1, DBLK1B, DCLK2, DCLK2B CLKI0 CLPY, CLPCB, CLPCR 4 mA drive output 8 mA drive output A13546 12 mA drive output 4 mA 3-state drive output A13547 g74980m06 SDA Open-drain I/O A13548 g74100m06 zwp3vpll3 VCOCNT, VCORNG Analog through PDO Charge pump output A13549 Note: * All of the DVDD, DVSS, AVDD, and AVSS pins must be connected to the corresponding power or ground level. Do not leave any of these pins open. No. 7023-9/14 6 13 90 92 94 91 93 95 96 97 HITV HIDTV HIDPC VITV VIDTV VIDPC BLKIH BLKIV Cr Cb Color 42 172 173 174 AICS / AIDA / AICK B G R 8 176 SDA / SCL 175 I2C bus control interface Horizontal expansion 39 B G R Three-wire bus control interface • Field discrimination • Horizontal sync signal polarity discrimination • Composite blanking signal discrimination and separation • Timing generation for all horizontal and vertical timings RGB ↓ YCbCr 8 Expansion processing Output processing O S D 154 155 158 159 103 BLKVOUT 102 BLKHOUT 163 VOUT 162 HOUT 146 151 BOODD 138 143 GOODD 130 135 ROODD ILC05427 192 199 182 189 138 147 122 127 BOEVEN 126 135 114 119 GOEVEN 116 125 XTAL DCLK1 / DCLK1B / DCLK2 / DCLK2B 167 When in 8-bit output mode 106 111 ROEVEN 106 115 6 or 8 Output clock generation circuit • Input sync signal detection • Timing generation for all horizontal and vertical timings Output timing circuit White balance Contrast Black balance Brightness 36 Color phase Sharpness Input timing circuit YCbCr ↓ RGB Y Input processing γ correction Input clock generation circuit R B G Cr Cb Y 8 Color depth processing CLKITV / CLKIDTV / CLKIPC RIN [7 : 0] 74 81 BIN [7 : 0] 64 71 GIN [7 : 0] 54 61 VIN [7 : 0] 26 33 UIN [7 : 0] 16 23 YIN [7 : 0] 8 LC74982W IC Internal Block Diagram Vertical expansion No. 7023-10/14 LC74982W Sample Application Circuit (LCD TV/Monitor) RO (6bit or 8bit) Y (8bit) Tuner Degital Decoder VCR CbCr (8bit) LC74982W TFT-LCD MODULE (XGA) GO (6bit or 8bit) Hsync BO (6bit or 8bit) Vsync RE (6bit or 8bit) Pixel clocks GE (6bit or 8bit) BE (6bit or 8bit) BLK Hsync PC A/D R (8bit) Vsync G (8bit) Pixel clocks B (8bit) Hsync Vsync PLL Pixel clocks X'Tal 65.0MHz Microcontroller LC86F3248A No. 7023-11/14 LC74982W I/O Data Timing (1) Input data timing tHI tCK Input system clock VDD/2 tLO tSU tHD VDD/2 Input data Pin Parameter min max Unit Clock low-level period Item CLKITV tLO 7.5 — ns Clock high-level period CLKIDTV tHI 7.5 — ns CLKIPC tCK 15.0 — ns tSU 0 — ns tHD 7.0 — ns Clock cycle YIN [7:0], UIN [7:0] Input data setup time VIN [7:0], RIN [7:0] GIN [7:0], BIN [7:0] Input data hold time HITV, VITV, HIDTV, VIDTV HIPC, VIPC, BLKIH, BLKIV Note: * We recommend using a duty of 50% for the input clock signal. (2) Output data timing tHI tCK DCLK2B VDD/2 tLO tOUT Output data VDD/2 Item Pin Clock low-level period Clock high-level period DCLK2, DCLK2B Clock cycle Parameter min max Unit tLO 15.0 — ns tHI 15.0 — ns tCK 30.0 — ns tOUT 0 10 ns ROEVEN [5(7):0], GOEVEN [5(7):0] Output data delay time BOEVEN [5(7):0], ROODD [5(7):0] GOODD [5(7):0], BOODD [5(7):0] BLKHOUT, HOUT, VOUT No. 7023-12/14 LC74982W I/O Clock Timing (1) Input system clock timing tHI tCK CLKITV CLKIDTV CLKIPC VDD/2 tLO tOUT CLKIO VDD/2 Pin Parameter min max Unit Clock low-level period Item CLKITV tLO 7.5 — ns Clock high-level period CLKIDTV tHI 7.5 — ns CLKIPC tCK 15.0 — ns CLKIO tOUT 5 10 ns Clock cycle Cock I/O delay time (2) Output system clock timing tHI tCK XTAL VDD/2 tLO tOUT1 DCLK1 VDD/2 tD1 VDD/2 DCLK1B tOUT2 tHI2 tCK2 VDD/2 DCLK2 tLO2 tD2 DCLK2B Item VDD/2 Pin Clock low-level period Clock high-level period XTAL Clock cycle DCLK1 delay time DCLK1B delay time DCLK2B delay time max Unit 7.5 — ns tHI 7.5 — ns tCK 15.0 — ns DCLK1 tOUT1 0 5 ns tD1 –1 +1 ns tLO2 15.0 — ns tHI2 15.0 — ns tCK2 30.0 — ns DCLK2 tOUT2 0 2 ns DCLK2B tD2 –1 +1 ns DCLK2 Clock cycle DCLK2 delay time min tLO DCLK1B Clock low-level period Clock high-level period Parameter No. 7023-13/14 LC74982W Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer’s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer’s products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification” for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of September, 2001. Specifications and information herein are subject to change without notice. PS No. 7023-14/14