SANYO LC75051E

Ordering number : EN*A0178
LC75051E
CMOS IC
Lip-Sync Enabling Audio DSP
Overview
The LC75051E is a single-chip audio DSP equipped with an Audio interface unit with features such as audio algorithm
and lip-sync functions, which are required by audio/video-related products for which higher and higher sound quality
levels are being demanded. The microcontroller has a CCB (Computer Control Bus) and I2C (Inter-Integrated Circuit)
–support interface.
Features
1. Hardware configuration that allows installation of audio algorithm functions related to audio/video products
• Program ROM: 24 bits×8K words
• Data RAM: 24 bits×4K words×2 planes, 24 bits×1K words×2 planes
• Audio interface: I2S input, MSB first right justified, MSB first left justified (1 port)
• Audio interface: I2S output, MSB first right justified, MSB first left justified (3 ports)
• Analog input: 1 port (2 channel stereo), Analog output: 1 port (2 channel stereo)
2. Audio algorithms for audio/video-related products installed
• Lip sync function (correcting time lags up to 80ms between audio and video at a 48kHz sampling frequency)
• Low frequency enhancement function (S-Live: SANYO Low frequency Intelligence Virtual Excitation)
• Surround function (Digital AViSS: Digital Acoustic Virtual Sound System)
• Equalizer function (3 bands/channel, common to L and R channels)
• Volume control function (0 to –79dB, in 1dB increments, -∞)
• Bass/treble/middle control (±18dB in 1dB increments) and other basic control functions
• Wide variety of audio processing functions
Audio processing functions already installed in LC75051E
Effect
Algorithm (Name)
Remarks
Low frequency enhancement
S-Live
SANYO’s proprietary low frequency enhancement algorithm
Surround
Digital AViSS
SANYO’s proprietary sound field control algorithm
Any and all SANYO Semiconductor products described or contained herein do not have specifications
that can handle applications that require extremely high levels of reliability, such as life-support systems,
aircraft's control systems, or other applications whose failure can be reasonably expected to result in
serious physical and/or material damage. Consult with your SANYO Semiconductor representative
nearest you before usingany SANYO Semiconductor products described or contained herein in such
applications.
SANYO Semiconductor assumes no responsibility for equipment failures that result from using products
at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor
products described or contained herein.
83006 / 61506HKIM No.A0178-1/9
LC75051E
The audio processing functions listed in the table below can be installed by making changes to the program ROM.
(These functions have not been installed in the LC75051E).
Effect
Algorithm (Name)
Remarks
Surround
AViSS
SANYO’s proprietary sound field control algorithm
Virtual surround
VASIL
SANYO’s proprietary sound field control algorithm
Surround
Dolby Prologic II
Registered trademark of Dolby Laboratories, Inc.
Low frequency enhancement
TruBass
Registered trademark of SRS Labs, Inc.
Sound field correction
Focus
Registered trademark of SRS Labs, Inc.
Virtual surround
SRS 3D,TruSurround
Registered trademark of SRS Labs, Inc.
Low- and high-frequency enhancement
Dedekind
Registered trademark of Dedekind R&D
Low- and high-frequency augumentation
BBE
Registered trademark of BBE Sound Inc.
Note 1: Users must be licensees of the algorithms listed. Model names are subject to change.
Note 2: Processing estimates for using the algorithms will be based on the combinations in which the desired functions
are used.
3. Microcontroller interface
• CCB and I2C support
4. Supply voltages
• Analog: 3.3V, 5V
• Digital: 1.8V, 3.3V
Specifications
Absolute Maximum Ratings at VSS = 0V, AVSS = 0V
Ratings
Parameter
Supply voltage
Symbol
Conditions
VDD max1
AVDD1, AVDD2, AVDD3
VDD max1
BVDD1
VDD max2
XVDD
VDD max3
CVDD1, CVDD2, CVDD3, CVDD4
VDD max4
DVDD1, DVDD2, DVDD3, DVDD4
(A/D,D/A,volume,etc)
Supply voltage
(A/D,D/A,volume,etc)
Supply voltage
(crystal oscillator)
Supply voltage
(I/O interface block)
Supply voltage
(DSP core block, PLL block)
Maximum input voltage
PLLDVDD, PLLAVDD, PLLPWRR
VIN1
(A/D,D/A,volume,etc)
Maximum input voltage
INL, INR
EVRINL, EVRINR
VIN2
min
typ
unit
max
-0.3
+6.0
V
-0.3
+3.96
V
-0.3
+3.96
V
-0.3
+3.96
V
-0.3
+2.16
V
-0.3
AVDD+0.3
(max+6.0V)
V
-0.3
CVDD+0.3
(max+3.96V)
V
-0.3
CVDD+0.3
V
TEST0, TEST1, TEST2, TEST3, TEST4,
(DSP core block)
TEST5, TEST6, TEST7
(I/O interface block)
SCKI, LRCKI, BCKI, DATAI, CE, SCL/CL,
I2CBUSY/DI, SDA/DO, MCUIFSEL,
XPDESC, RSTB, PWDB, INTB, XSEL0,
XSEL1, XSEL2
Maximum output voltage
Allowable power dissipation
VOUT
Pd max
CVDD
Conditions: audio disabled operating state,
mounted on a standard board*
Maximum output current
IO
SDA/DO
850
mW
0
4
mA
Operating temperature
Topr
-20
75
°C
Storage temperature
Tstg
-55
125
°C
*: Standard board: 76.1mm×114.3mm×1.6mm; glass epoxy resin
No.A0178-2/9
LC75051E
Allowable Operating Ranges at Ta = -20 to +75°C, VSS = 0V, AVSS = 0V
Ratings
Parameter
Symbol
Conditions
min
typ
unit
max
Supply voltage (analog block)
AVDD
AVDD1, AVDD2, AVDD3
+4.75
+5.25
V
Supply voltage (analog block)
BVDD
BVDD1
+3.0
+3.6
V
Supply voltage (crystal oscillator)
XVDD
XVDD
+3.0
+3.6
V
Supply voltage (digital block)
CVDD
CVDD1, CVDD2, DVDD3, DVDD4
+3.0
+3.6
V
Supply voltage (digital block, PLL)
DVDD
DVDD1, DVDD2, DVDD3, DVDD4
PLLDVDD, PLLAVDD, PLLPWRR
+1.62
+1.98
V
High-level input voltage
VIH_D
CVDD
V
TEST0, TEST1, TEST2, TEST3, TEST4,
TEST5, TEST6, TEST7
SCKI, LRCKI, BCKI, DATAI, CE, SCL/CL,
I2CBUSY/DI, SDA/DO, MCUIFSEL,
0.8
×CVDD
XPDESC, RSTB, PWDB, INTB, XSEL0,
XSEL1, XSEL2
Low-level input voltage
VIL_D
TEST0, TEST1, TEST2, TEST3, TEST4,
TEST5, TEST6, TEST7
SCKI, LRCKI, BCKI, DATAI, CE, SCL/CL,
I2CBUSY/DI, SDA/DO, MCUIFSEL,
0.2
VSS
×CVDD
V
XPDESC, RSTB, PWDB, INTB, XSEL0,
XSEL1, XSEL2
Crystal oscillator frequency
Fop
XIN, XOUT
18.432
MHz
Electrical Characteristics for the Allowable Operating Ranges
Ratings
Parameter
High-level input current
Symbol
IIH
Pin name
TEST0, TEST1, TEST2,
Conditions
min
typ
unit
max
VIN2=VIN3=CVDD
TEST3, TEST4, TEST5,
TEST6, TEST7
SCKI, LRCKI, BCKI,
5
DATAI, CE, SCL/CL,
µA
I2CBUSY/DI, SDA/DO,
MCUIFSEL, XPDESC,
RSTB, PWDB, INTB,
XSEL0, XSEL1, XSEL2
Low-level input current
IIL
TEST0, TEST1, TEST2,
VIN2=VIN3=0V
TEST3, TEST4, TEST5,
TEST6, TEST7
SCKI, LRCKI, BCKI,
-5
DATAI, CE, SCL/CL,
µA
I2CBUSY/DI, SDA/DO,
MCUIFSEL, XPDESC,
RSTB, PWDB, INTB,
XSEL0, XSEL1, XSEL2
High-level output voltage
VOH(1)
TEST6, TEST7, LRCKO,
IOH=-2mA
BCKO, DATAO0, DATAO1,
CVDD-
DATAO2, I2CBUSY/DI,
0.4
EMPF, GPFLAG, MRREQ,
V
XSEL0, XSEL1, XSEL2
VOH(2)
SCKO, SDA/DO
IOH=-4mA
CVDD0.4
Continued on next page.
No.A0178-3/9
LC75051E
Continued from preceding page.
Ratings
Parameter
Symbol
Low-level output voltage
VOL(1)
Pin name
TEST6, TEST7, LRCKO,
Conditions
min
typ
unit
max
IOH=2mA
BCKO, DATAO0, DATAO1,
DATAO2, I2CBUSY/DI,
0.4
SDA/DO
V
EMPF, GPFLAG, MRREQ,
XSEL0, XSEL1, XSEL2
Output off leakage current
VOH(2)
SCKO, SDA/DO
IOH=4mA
IOFF(1)
XSEL0, XSEL1, XSEL2,
VOUT=CVDD
0.4
TEST6, I2CBUSY/DI,
5
SCKO, SDA/DO
IOFF(2)
XSEL0, XSEL1, XSEL2,
µA
VOUT=0V
2
-5
TEST6, I CBUSY/DI,
SCKO, SDA/DO
Full scale input level
VIN
Analog output level
Reference voltage output
Current drain
INL, INR
0.4×AVDD
(max2Vp-p)
Vp-p
VOUT
AOUT1, AOUT2
0.6×AVDD
(max3Vp-p)
Vp-p
Vref
VREF1, VREF2
I_XVDD
XVDD
2.35
2.5
2.65
1.2
1.6
50
65
2
3.5
1.8
2.4
65
85
V
Conditions: audio disabled
operating state, mounted on
a standard board*
XVDD=3.3V
I_AVDD
AVDD1, AVDD2, AVDD3
Conditions: audio disabled
operating state, mounted on
a standard board*
AVDD=5V
I_BVDD
BVDD1
Conditions: audio disabled
operating state, mounted on
a standard board*
mA
BVDD=3.3V
I_CVDD
CVDD1, CVDD2, CVDD3,
Conditions: audio disabled
CVDD4
operating state, mounted on
a standard board*
CVDD=3.3V
I_DVDD
DVDD1, DVDD2, DVDD3,
Conditions: audio disabled
DVDD4
operating state, mounted on
PLLDVDD, PLLAVDD,
a standard board*
PLLPWRR
DVDD=1.8V
*: Standard board: 76.1mm×114.3mm×1.6mm; glass epoxy resin
No.A0178-4/9
LC75051E
Analog Characteristics
Conditions: AVDD = 5V, BVDD = CVDD = 3.3V, DVDD = 1.8V, fs = 48kHz, audio signal frequency = 1kHz
Frequency bandwidth measured from A/D input to volume output: 10Hz to 20kHz, with a SANYO DSP evaluation
board used
Test circuit configured with circuits externally attached to LC75051E; tested with signals passed straight through the
DSP at room temperature using an audio analyzer (System 2) as the test device
Ratings
Parameter
min
typ
max
unit
Conditions
S/N
80
90
dB
A-weighted, input conditions: 2Vp-p
Dynamic range
80
90
dB
A-weighted
dB
Input conditions: 1.5Vp-p, See Note.
THD+N
-75
-70
Note: THD+N denotes the characteristics at which the input (1.5Vp-p) reduced by 3dB from the full-scale input is
optimum.
Conditions: AVDD = 5V, BVDD = CVDD = 3.3V, DVDD = 1.8V, fs = 48kHz, audio signal frequency = 1kHz
Frequency bandwidth measured from digital input to volume output: 10Hz to 20kHz, SANYO DSP evaluation board
used
Test circuit configured with circuits externally attached to LC75051E; tested with signals passed straight through the
DSP at room temperature using an audio analyzer (System2) as the test device
Ratings
Parameter
min
typ
S/N
83
Dynamic range
83
max
93
93
THD+N
-75
-70
unit
Conditions
dB
A-weighted, input conditions: 0dBFS
dB
A-weighted
dB
Input conditions: -3dBFS, See Note.
Note: THD+N denotes the characteristics at which the input reduced by 3dB from the full-scale input is
optimum.
Package Dimensions
unit : mm
3255
17.2
0.8
14.0
60
41
40
80
21
14.0
17.2
61
1
0.65
0.25
20
0.15
(2.7)
0.1
3.0max
(0.83)
SANYO : QFP80(14X14)
No.A0178-5/9
LC75051E
DAOUTL
EVRINL
AOUT1
AVSS3
AVDD3
AVDD4
AVSS4
BVDD1
BVSS1
28
27
26
25
24
23
22
21
DAOUTR
AVSS2
33
29
AVDD2
34
30
VREF2
35
AOUT2
VREF1
37
36
EVRINR
INL
38
31
AVSS1
INR
39
32
AVDD1
40
Pin Assignment
TEST6
41
20
TEST5
XSEL0
42
19
TEST4
XSEL1
43
18
TEST1
XSEL2
44
17
TEST0
CVSS1
45
16
CVSS4
CVDD1
46
15
CVDD4
LRCKI
47
14
XVDD
BCKI
48
13
XIN
DATAI
49
12
XOUT
SCKI
50
11
XVSS
DVSS1
51
10
DVDD4
DVDD1
52
9
DVSS4
SCKO
53
8
TEST3
TEST7
54
7
TEST2
DATAO2
55
6
PLLDVSS
DATAO1
56
5
DATAO0
57
4
PLLDVDD
PLLAVSS
BCKO
58
3
PLLAVDD
LRCKO
59
60
2
PLLGNDR
PLLPWRR
74
75
76
77
78
79
80
DVSS3
DVDD3
MRREQ
GPFLAG
EMPF
CVSS3
CVDD3
69
MCUIFSEL
73
68
INTB
SDA/DO
67
RSTB
72
66
PWDB
I2CBUSY/DI
65
DVDD2
71
64
70
63
PDEN
DVSS2
CE
62
XPDESC
SCL/CL
61
1
CVDD2
CVSS2
LC75051E
Top view
Pin Functions
Pin Name
Input/Output
INL
AI
Function
Lch ADC analog input
Pin No.
37
INR
AI
Rch ADC analog input
38
DAOUTL
AO
Lch DAC analog output
29
DAOUTR
AO
Rch DAC analog output
30
EVRINL
AI
Lch EVR input
28
EVRINR
AI
Rch EVR input
31
AOUT1
AO
Lch EVR output
27
AOUT2
AO
Rch EVR output
32
LRCKI
I
LR clock input
47
BCKI
I
Bit clock input
48
DATAI
I
Data input
49
LRCKO
O
LR clock output
59
BCKO
O
Bit clock output
58
DATAO0
O
Data output 0
57
DATAO1
O
Data output 1
56
DATAO2
O
Data output 2
55
SCKI
I
External clock input
50
SCKO
I/O
DAC master clock output
53
RSTB
I
Reset input (low active)
67
PWDB
I
Power down input (low active)
66
Continued on next page.
No.A0178-6/9
LC75051E
Continued from preceding page.
Pin Name
Input/Output
INTB
I
Function
Pin No.
Interrupt input (low active)
68
2
MCUIFSEL
I
Microcontroller interface select input (CCB: low, I C: high)
69
CE
I
Microcontroller interface chip enable, fixed at high when I2C is selected.
70
SCL/CL
I
Microcontroller interface clock input
71
2
I2CBUSY/DI
I/O
Microcontroller interface data input/I C BUSY output
72
SDA/DO
I/O
Microcontroller interface data input/output
73
EMPF
O
CCB input register status monitor flag
78
GPFLAG
O
DSP-to-MCU general-purpose flag (high active)
77
MRREQ
O
DSP-to-MCU communication error flag
76
XPDESC
I
DSP power down reset signal (low active)
62
PDEN
O
DSP power down signal (high active)
63
XSEL0
I/O
Crystal frequency select signal 0
42
XSEL1
I/O
Crystal frequency select signal 1
43
XSEL2
I/O
Crystal frequency select signal 2
44
TEST7
I
Test pin
54
TEST0, TEST1, TEST2,
I
Test pin
17, 18, 7, 8, 19, 20
I/O
Test pin
41
Crystal oscillator input
13
Crystal oscillator output
12
XVDD
Power supply for crystal oscillator
14
XVSS
GND for crystal oscillator
11
Reference voltage output pin 1 (ADC)
36
Reference voltage output pin 2 (DAC, EVR)
35
TEST3, TEST4, TEST5
TEST6
XIN
XOUT
VREF1
AO
VREF2
AO
AVDD1
ADC analog power supply (+5V)
40
AVSS1
ADC analog GND
39
AVDD2
VREF VDD (+5V)
34
AVSS2
VREF GND
33
AVDD3
EVR analog VDD (+5V)
25
AVSS3
EVR analog GND
26
AVDD4
DAC analog VDD (+5V)
24
AVSS4
DAC analog GND
23
BVDD1
Analog chip logic power supply (+3.3V)
22
BVSS1
Analog chip logic GND
CVDD1, CVDD2,
21
Digital power supply (3.3V)
46, 61, 80, 15
Digital GND
45, 60, 79, 16
Digital power supply (1.8V)
52, 65, 75, 10
Digital GND
51, 64, 74, 9
CVDD3, CVDD4
CVSS1, CVSS2,
CVSS3, CVSS4
DVDD1, DVDD2,
DVDD3, DVDD4
DVSS1, DVSS2,
DVSS3, DVSS4
PLLPWRR
Powering for PLL (ESD) (1.8V)
1
PLLGNDR
GND for PLL (ESD)
2
PLLAVDD
Power supply for PLL (1.8V)
3
PLLAVSS
GND for PLL
4
PLLDVDD
Digital power supply for PLL (1.8V)
5
PLLDVSS
Digital GND for PLL
6
No.A0178-7/9
LC75051E
Block Diagram
DAOUTL
(C ≥ 1µF)
INR
DAC
(20 bits)
ADC
(20 bits)
R
L.P.F.
AOUT1
DSP/CORE
(24 bits)
Vref
DAOUTR
(C ≥ 1µF)
R
INL
EVRINL
DAC
(20 bits)
ADC
(20 bits)
EVRINR
L.P.F.
AOUT2
Vref
Audio
I/F
LRCKO
BCKO
DATAO0
Audio
I/F
DATAO1
Audio
I/F
DATAO2
Program ROM
LRCKI
BCKI
Audio
I/F
DATAI
PLLAVDD
1.8V
PLLAVSS
Data RAM
PLLDVDD
1.8V
PLLDVSS
AVDD1-4
5V
AVSS1-4
Delay RAM
BVDD1
BVSS1
3.3V
CVDD1-4
3.3V
CVSS1-4
DVDD1-4
1.8V
DVSS1-4
PLLPWPR
PLL
VCO
PLLGNDR
XVDD
XVSS
2
CCB or I C
3.3V
XSEL0,1, 2
SCKI
SCKO
TEST7,5-0
TEST6
INTB
PDEN
XPDESC
PWDB
RSTB
SDA/DO
MCUIFSEL
CE
SCL/CL
2
I CBUSY/DI
MRREQ
GPFLAG
EMPF
XOUT
XIN
VREF1
VREF2
For sample external circuit configurations, see "LC75051E External Circuit
Configuration Examples (Draft).
No.A0178-8/9
LC75051E
Specifications of any and all SANYO Semiconductor products described or contained herein stipulate the
performance, characteristics, and functions of the described products in the independent state, and are
not guarantees of the performance, characteristics, and functions of the described products as mounted
in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an
independent device, the customer should always evaluate and test devices mounted in the customer's
products or equipment.
SANYO Semiconductor Co., Ltd. strives to supply high-quality high-reliability products. However, any
and all semiconductor products fail with some probability. It is possible that these probabilistic failures
could give rise to accidents or events that could endanger human lives, that could give rise to smoke or
fire, or that could cause damage to other property. When designing equipment, adopt safety measures
so that these kinds of accidents or events cannot occur. Such measures include but are not limited to
protective circuits and error prevention circuits for safe design, redundant design, and structural design.
In the event that any or all SANYO Semiconductor products (including technical data,services) described
or contained herein are controlled under any of applicable local export control laws and regulations, such
products must not be exported without obtaining the export license from the authorities concerned in
accordance with the above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system, or
otherwise, without the prior written permission of SANYO Semiconductor Co., Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification"
for the SANYO Semiconductor product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not
guaranteed for volume production. SANYO Semiconductor believes information herein is accurate and
reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual
property rights or other rights of third parties.
This catalog provides information as of June, 2006. Specifications and information herein are subject
to change without notice.
PS No.A0178-9/9