SANYO LC87F06J2A

Ordering number : ENA0432A
LC87F06J2A
CMOS IC
FROM 192K byte, RAM 8192 byte on-chip
8-bit 1-chip Microcontroller
Overview
The SANYO LC87F06J2A is an 8-bit microcomputer that, centered around a CPU running at a minimum bus cycle time
of 66.6ns, integrate on a single chip a number of hardware features such as 192K-byte flash ROM (onboard rewritable),
8K-byte RAM, Onchip debugging function, two sophisticated 16-bit timers/counters (may be divided into 8-bit timers), a
16-bit timer with a prescaler (may be divided into 8-bit timers), four 8-bit timers with a prescaler, a base timer serving as
a time-of-day clock, two synchronous SIO ports (with automatic block transmission/reception capabilities), an
asynchronous/synchronous SIO port, two synchronous SIO ports, two UART ports (full duplex), four 12-bit PWM
channels, VPS/PDC/PAL-WSS • XDS • EPG-J • VBID(Video-ID) Data-slicer, an universal remote control transmitter, an
8-bit 16-channel AD converter, a high-speed clock counter, a system clock frequency divider, and a 36-source 10-vector
interrupt, ROM correction function feature.
Features
„Flash ROM
• Single 5V power supply, on-board writeable
• Block erase in 128 byte units
• 196608 × 8 bits (LC87F06J2A)
„RAM
• 8192 × 9 bits
„Bus Cycle Time
• 66.6ns (15MHz, 1/1 frequency division ratio )
Note: Bus cycle time indicates the speed to read ROM.
* This product is licensed from Silicon Storage Technology, Inc. (USA), and manufactured and sold by
SANYO Semiconductor Co., Ltd.
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,
communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be
intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace
instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety
equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case
of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee
thereof. If you should intend to use our products for applications outside the standard applications of our
customer who is considering such use and/or outside the scope of our intended standard applications, please
consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our
customer shall be solely responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer' s products or
equipment.
Ver.1.003
31407HKIM 20070115-S00002 No.A0432-1/32
LC87F06J2A
„Minimum Instruction Cycle Time (tCYC)
• 200ns (15MHz, 1/1 frequency division ratio)
„Ports
• Normal withstand voltage I/O ports
Ports whose I/O direction can be designated in 1 bit units: 75 (P1n, P2n, P3n, P70 to P73, P8n, PAn, PB0 to PB2,
PCn, S2Pn, XT2, PWM0, PWM1, PEn, PFn )
Ports whose I/O direction can be designated in 4 bit units: 8 (P0n)
• Normal withstand voltage input ports:
1 (XT1)
• Dedicated oscillator ports:
2 (CF1, CF2)
• Reset pin:
1 (RES)
• Data slicer pins:
2 (PB4, PB6)
• Power pins:
11 (VSS1 to VSS4, VDD1 to VDD4,
VSSVCO, VDDVCO, VDDODA)
„Timer
• Timer 0: 16-bit timer/counter with capture register
Mode 0: 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers) × 2 channels
Mode 1: 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers)
+ 8-bit counter (with two 8-bit capture registers)
Mode 2: 16-bit timer with an 8-bit programmable prescaler (with two 16-bit capture registers)
Mode 3: 16-bit counter (with two 16-bit capture registers)
• Timer 1: 16-bit timer/counter that support PWM/ toggle output
Mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs)
+ 8-bit timer/counter (with toggle outputs)
Mode 1: 8-bit PWM with an 8-bit prescaler × 2 channels
Mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs)
(toggle outputs also from the lower-order 8 bits)
Mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs)
(The lower-order 8 bits can be used as PWM.)
• Timer 4: 8-bit timer with a 6-bit prescaler
• Timer 5: 8-bit timer with a 6-bit prescaler
• Timer 6: 8-bit timer with a 6-bit prescaler (with toggle outputs)
• Timer 7: 8-bit timer with a 6-bit prescaler (with toggle outputs)
• Timer 8: 16-bit timer with a prescaler (may be divided into 8-bit timers)
• Base timer
1) The clock is selectable from the subclock (32.768kHz crystal oscillator), system clock,
and timer 0 prescaler output.
2) Interrupts programmable in 5 different time schemes.
„Day and Time Counter
1) Using with a base timer, it can be used as 65,000 days + minute + second counter.
„High-speed Clock Counter
1) Can count clocks with a maximum clock rate of 20MHz (at a main clock of 10MHz).
2) Can generate output real time.
„SIO
• SIO 0: 8 bit synchronous serial interface
1) LSB first/MSB first mode selectable
2) Built-in 8-bit baudrate generator (maximum transfer clock cycle = 4/3 tCYC)
3) Automatic continuous data transmission (1 to 256 bits)
• SIO 1: 8 bit asynchronous/synchronous serial interface
Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks)
Mode 1: Asynchronous serial I/O (Half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrates)
Mode 2: Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks)
Mode 3: Bus mode 2 (start detect, 8 data bits, stop detect)
Continued on next page.
No.A0432-2/32
LC87F06J2A
Continued from preceding page.
• SIO2: 8 bit synchronous serial interface
1) LSB first mode
2) Built-in 8-bit baudrate generator (maximum transfer clock cycle = 4/3 tCYC)
3) Automatic continuous data transmission (1 to 32 bytes)
• SIO 7: 8 bit synchronous serial interface
1) LSB first/MSB first mode selectable
2) Built-in 8-bit baudrate generator (maximum transfer clock cycle = 4/3 tCYC)
• SIO 8: 8 bit synchronous serial interface
1) LSB first/MSB first mode selectable
2) Built-in 8-bit baudrate generator (maximum transfer clock cycle = 4/3 tCYC)
„UART: 2 channels
1) Full duplex
2) 7/8/9 bit data bits selectable
3) 1 stop bit (2 bits in continuous transmission mode)
4) Built-in baudrate generator (with baudrates of 16/3 to 8192/3 tCYC)
„AD Converter
• 8 bits × 16 channels
„PWM
• Multifrequency 12-bit PWM × 4 channels
„Remote Control Receiver Circuit (sharing pins with P73, INT3, T0IN and TOHCP)
1) Noise filtering function (noise filter time constant selectable from 1 tCYC, 32 tCYC, and 128 tCYC)
2) The noise filtering function is available for the INT3, T0IN, or T0HCP signal at P73. When P73 is read
with an instruction, the signal level at that pin is read regardless of the availability of the noise filtering function.
„Small Signal Detect Function
1) Small Signal Detect Function is available in the following two terminals.
P20/INT4/T1IN/T0LCP/T0HCP/INT6/T0LCP1/SSGI0
P24/INT5/T1IN/T0LCP/T0HCP/INT7/T0HCP1/SSGI1
2) Capable of detecting a pulse with certain level of amplitude.
3) Input bias circuit available.
„H-Counter
1) H-counter can choose one of the following signals as count-clock.
HCTR signal of P22/INT4/T1IN/T0LCP/T0HCP/HCTR terminal
CSYNC signal of PB6/CVD/CSYNC terminal
Composite sync signal detected from CVD (composite Video) signal by built-in sync-separator inputted form
PB6/CVD/CSYNC terminal
2) Counter 7bit (up) + 1bit (over-flow flag)
„Field (first/second) Detect Function
1) Distinguishes a field with one of the following signals.
CSYNC signal of PB6/CVD/CSYNC terminal
Composite sync signal detected from CVD (composite Video) signal by built-in sync-separator inputted form
PB6/CVD/CSYNC terminal
2) Outputs Field-Detect signal from PB0/DS1FLD terminal
„Watchdog Timer
1) External RC watchdog timer
2) Interrupt and reset signals selectable
No.A0432-3/32
LC87F06J2A
„Data-Slicer
• XDS
1) Supports XDS-1X and XDS-2X (With auto-recognition)
• VPS/PDC/PAL-WSS
Data-slicer can choose one of the following three formats to the TV Line(VBI).
1) PDC/UDT and other Teletext data
2) VPS
3) PAL-WSS
• VPS
• EPG-J
• Antiope
• VBID(VideoID)
„Universal Remote Control Transmitter Circuit
• Outputs remote control signal from PF4/IRP terminal.
„Interrupts
• 36 sources, 10 vector addresses
1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control.
Any interrupt requests of the level equal to or lower than the current interrupt are not accepted.
2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level
takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector
address takes precedence.
No.
Vector
Selectable Level
Interrupt signal
1
00003H
X or L
INT0
2
0000BH
X or L
INT1
3
00013H
H or L
INT2/T0L/INT4
4
0001BH
H or L
INT3/INT5/Base timer0/Base timer1/Remocon transmit
5
00023H
H or L
T0H/INT6/SIO7
6
0002BH
H or L
T1L/T1H/INT7/SIO8
7
00033H
H or L
SIO0/UART1 receive/UART2 receive/T8L/T8H
8
0003BH
H or L
SIO1/SIO2/UART1 transmit/UART2 transmit
9
00043H
H or L
ADC/T6/T7/PWM4, PWM5/ Automatic transmission
10
0004BH
H or L
Port 0/T4/T5/Data slicer /PWM0, PWM1
• Priority Level: X > H > L
• Of interrupts of the same level, the one with the smallest vector address takes precedence.
„Subroutine Stack Levels
• 4096 levels maximum (the stack is allocated in RAM.)
„High-speed Multiplication/Division Instructions
• 16 bits × 8 bits
(5 tCYC execution time)
• 24 bits × 16 bits
(12 tCYC execution time)
• 16 bits ÷ 8 bits
(8 tCYC execution time)
• 24 bits ÷ 16 bits
(12 tCYC execution time)
„Oscillation Circuits
• RC oscillator circuit (internal): For system clock
• CF oscillator circuit: For system clock with internal Rf
• Crystal oscillator circuit: For low-speed system clock
• Multifrequency RC oscillator circuit (internal): For system clock
No.A0432-4/32
LC87F06J2A
„System Clock Divider Function
• Can run on low current.
• The minimum instruction cycle selectable from 300ns, 600ns, 1.2µs, 2.4µs, 4.8µs, 9.6µs, 19.2µs, 38.4µs, and 76.8µs
(at a main clock rate of 10MHz).
„Standby Function
• HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation.
1) Oscillation is not halted automatically.
2) Canceled by system reset or occurrence of interrupt.
• HOLD mode: Suspends instruction execution and the operation of the peripheral circuits.
1) The CF, RC, and crystal oscillators automatically stop operation.
2) There are three ways of resetting the HOLD mode.
(1) Setting the Reset pin to the lower level
(2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level
(3) Having an interrupt source established at port 0
• X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer
and the Day-and-time counter.
1) The CF and RC oscillators automatically stop operation.
2) The state of crystal oscillation established when the HOLD mode is entered is retained.
3) There are four ways of resetting the X'tal HOLD mode.
(1) Setting the Reset pin to the low level.
(2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level.
(3) Having an interrupt source established at port 0.
(4) Having an interrupt source established in the base timer circuit.
„Onchip Debugging
• Permits software debugging with the test device installed on the target board.
„ROM Correction Function
• PC match address registers: 4
• Ram for ROM correction: 128byte
„Package Form
• QIP100E(14×20): “Lead-free type”
„Development Tools
• On-chip debugger: TCB87 TypeA + LC87F06J2A
: TCB87 TypeB + LC87F06J2A
„Flash ROM Programming Boards
Package
Programming boards
QIP100E(14×20)
W87F05256Q
„Flash ROM Programmer
Maker
Flash Support Group, Inc.
Model
AF9708/AF9709/AF9709B
(Single)
(including product of Ando Electric Co.,Ltd)
Flash Support Group, Inc.
AF9723(Main body)
(Gang)
(including product of Ando Electric Co.,Ltd)
AF9833(Unit)
Supported version
Device
Revision: After 02.61
LC87F06J2A FAST
Revision: After 02.04
LC87F06J2A FAST
Revision: After 01.86
(including product of Ando Electric Co.,Ltd)
SANYO
SKK(Sanyo FWS)
Application Version: After 1.03
LC87F06J2
Chip Data Version: After 2.01
No.A0432-5/32
LC87F06J2A
Package Dimensions
unit : mm (typ)
3151A
23.2
0.8
20.0
51
50
100
31
14.0
81
1
17.2
80
30
0.65
0.3
0.15
0.1
3.0max
(2.7)
(0.58)
SANYO : QIP100E(14X20)
No.A0432-6/32
1
2
3
4
5
6
7
PA3/SO8
PA5/SCK8
P70/INT0/T0LCP
P71/INT1/T0HCP
P72/INT2/T0IN/T0LCP
P73/INT3/T0IN/T0HCP
RES
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
P17/T1PWMH/BUZ
P16/T1PWML
P15/SCK1
P14/SI1/SB1
P13/SO1
P12/SCK0
P11/SI0/SB0
P10/SO0
P87/AN7
P86/AN6
P85/AN5
P84/AN4
P83/AN3
P82/AN2
P81/AN1
P80/AN0
VDD1
CF2
CF1
VSS1
9
XT2
8
XT1
PB6/CVD/CSYNC
81
50
SI2P1/SI2/SB2
VSSVCO
82
49
SI2P0/SO2
PB4/FILTSLC
83
48
PF7
VDDVCO
84
47
PF6
PB2
85
46
PF5
PB1
86
45
PF4/IRP
PB0/DS1FLD
87
44
PF3
VSS3
88
43
PF2
VDD3
89
42
PF1
PC7/DBGP2
90
41
PF0
PC6/DBGP1
91
40
VDD4
PC5/DGBP0
92
39
VSS4
PC4/AN11
93
38
PE7
PC3/AN10
94
37
PE6
PC2/AN9
95
36
PE5
PC1/AN8
96
35
PE4
PC0/OCSYNC
97
34
PE3/AN15
PA0/SO7
98
33
PE2/AN14
PA1/SI7/SB7
99
32
PE1/AN13
100
31
PE0/AN12
PA2/SCK7
PA4/SI8/SB8
SI2P2/SCK2
SI2P3/SCK2O
PWM1
PWM0
VDD2
VSS2
P00
P01
P02
P03
P04
P05/CKO
P06/T6O
P07/T7O
P20/INT4/T1IN/T0LCP/T0HCP/INT6/T0LCP1/SSGI0
P21/INT4/T1IN/T0LCP/T0HCP
P22/INT4/T1IN/T0LCP/T0HCP/HCTR
P23/INT4/T1IN/T0LCP/T0HCP
P24/INT5/T1IN/T0LCP/T0HCP/INT7/T0HCP1/SSGI1
P25/INT5/T1IN/T0LCP/T0HCP
P26/INT5/T1IN/T0LCP/T0HCP
P27/INT5/T1IN/T0LCP/T0HCP
P30/PWM4
P31/PWM5
P32/UTX1
P33/URX1
P34/UTX2
P35/URX2
P36
VDDODA
LC87F06J2A
Pin Assignment
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
LC87F06J2A
Top view
SANYO: QIP100E(14×20) “Lead-free Type”
No.A0432-7/32
LC87F06J2A
System Block Diagram
IR
Interrupt Control
PLA
Flash ROM
Standby Control
RC
Xtal
Clock
Generator
CF
PC
MRC
SIO0
Bus Interface
ACC
SIO1
Port 0
B Register
SIO2
Port 1
C Register
SIO7
Port 3
ALU
SIO8
Port 7
Timer 0
ADC
Timer 1
INT0-7
Timer 4
Port 2
(Small signal detect)
Timer 5
Timer 6
Port A
PSW
RAR
RAM
Stack Pointer
Port B
Watchdog Timer
Timer 7
Port C
Onchip Debugger
Timer 8
Port E
UART1
Port F
UART2
PWM4, 5
PWM0,1
Port 8
Data slicer
H-counter
Date slicer RAM
Universal remote
control transmitter
Base timer
Day and time
counter
No.A0432-8/32
LC87F06J2A
Pin Description
Pin Name
VSS1, VSS2
VSS3, VSS4
VSSVCO
VDD1, VDD2
I/O
Function description
Option
-
Power supply pin (-)
No
-
Power supply pin (+)
No
• 8-bit I/O port
Yes
VDD3, VDD4
VDDVCO,
VDDODA
Port 0
I/O
• I/O specifiable in 4-bit units
P00 to P07
• Pull-up resistor can be turned on and off in 4-bit units
• HOLD release input
• Port 0 interrupt input
• Pin functions
P05: System clock output
P06: Timer 6 toggle output
P07: Timer 7 toggle output
Port 1
I/O
Yes
• 8-bit I/O port
• I/O specifiable in 1-bit units
P10 to P17
• Pull-up resistor can be turned on and off in 1-bit units
• Pin functions
P10: SIO0 data output
P11: SIO0 data input, bus I/O
P12: SIO0 clock I/O
P13: SIO1 data output
P14: SIO1 data input, bus I/O
P15: SIO1 clock I/O
P16: Timer 1 PWML output
P17: Timer 1 PWMH output, Beeper output
Port 2
I/O
Yes
• 8-bit I/O port
• I/O specifiable in 1-bit units
P20 to P27
• Pull-up resistor can be turned on and off in 1-bit units
• Pin functions
P20: INT4 input/HOLD reset input/timer 1 event input/timer 0L capture input/
timer 0H capture input/INT6 input/timer 0L capture 1 input/small signal input
P21, P23: INT4 input/HOLD reset input/timer 1 event input/timer 0L capture input/
timer 0H capture input
P22: NT4 input/HOLD reset input/timer 1 event input/timer 0L capture input/
timer 0H capture input/HCTR signal input
P24: INT5 input/HOLD reset input/timer 1 event input/timer 0L capture input/
timer 0H capture input/INT7 input/timer 0H capture 1 input/small signal input
P25 to P27: INT5 input/HOLD reset input/timer 1 event input/timer 0L capture input/
Timer 0H capture input
• Interrupt acknowledge type
Port 3
P30 to P36
I/O
Rising
Falling
INT4
enable
enable
INT5
enable
enable
INT6
enable
INT7
enable
Rising/
H level
L level
enable
disable
disable
enable
disable
disable
enable
enable
disable
disable
enable
enable
disable
disable
Falling
• 7-bit I/O port
Yes
• I/O specifiable in 1-bit units
• Pull-up resistor can be turned on and off in 1-bit units
• Pin functions
P30: PWM4 output
P31: PWM5 output
P32: UART1 transmit
P33: UART1 receive
P34: UART2 transmit
P35: UART2 receive
Continued on next page.
No.A0432-9/32
LC87F06J2A
Continued from preceding page.
Pin Name
Port 7
I/O
I/O
Function description
Option
No
• 4-bit I/O port
• I/O specifiable in 1-bit units
P70 to P73
• Pull-up resistor can be turned on and off in 1-bit units
• Pin functions
P70: INT0 input/HOLD release input/Timer 0L capture input/Output for watchdog timer
P71: INT1 input/HOLD release input/Timer 0H capture input
P72: INT2 input/HOLD release input/Timer 0 event input/Timer 0L capture input
P73: INT3 input with noise filter/Timer 0 event input/Timer 0H capture input
• Interrupt acknowledge type
Port 8
I/O
Rising
Falling
INT0
enable
enable
INT1
enable
enable
INT2
enable
INT3
enable
Rising/
H level
L level
disable
enable
enable
disable
enable
enable
enable
enable
disable
disable
enable
enable
disable
disable
Falling
• 8-bit I/O port
No
• I/O specifiable in 1-bit units
P80 to P87
• Other functions
P80-P87: AD converter input port
Port A
I/O
• 6-bit I/O port
Yes
• I/O specifiable in 1-bit units
PA0 to PA5
• Pull-up resistor can be turned on and off in 1-bit units
• Pin functions
PA0: SIO7 data output
PA1: SIO7 data input, bus I/O
PA2: SIO7 clock I/O
PA3: SIO8 data output
PA4: SIO8 data input, bus I/O
PA5: SIO8 clock I/O
Port B
I/O
• 5-bit I/O port
PB0 to PB2
• I/O specifiable in 1-bit units
PB4, PB6
• Other functions
Yes
PB0: Output for field recognition signal
PB4: LPF connection for Slicer PLL
PB6: Input for CSYNC signal/CVD (Composite Video) signal
Port C
I/O
• 8-bit I/O port
Yes
• I/O specifiable in 1-bit units
PC0 to PC7
• Pull-up resistor can be turned on and off in 1-bit units
• Other functions
PC0: OCSYNC output
PC1 to PC4: AD converter input port
PC5 to PC7: On-chip Debugger
Port E
I/O
• 8-bit I/O port
No
• I/O specifiable in 1-bit units
PE0 to PE7
• Pull-up resistor can be turned on and off in 1-bit units
• Other functions
PE0-PE3: AD converter input port
Port F
PF0 to PF7
I/O
• 8-bit I/O port
No
• I/O specifiable in 1-bit units
• Pull-up resistor can be turned on and off in 1-bit units
• Other functions
PF4: Remote control signal output
Continued on next page.
No.A0432-10/32
LC87F06J2A
Continued from preceding page.
Pin Name
SIO2 Port
I/O
Function description
I/O
Option
• 4-bit I/O port
No
• I/O specifiable in 1-bit units
SI2P0 to SI2P3
• Other functions:
SI2P0: SIO2 data output
SI2P1: SIO2 data input, bus input/output
SI2P2: SIO2 clock input/output
SI2P3: SIO2 clock output
PWM0
O
• PWM0 output port
No
• General-purpose I/O available
PWM1
O
• PWM1 output port
No
• General-purpose I/O available
RES
I
Reset pin
No
XT1
I
• Input terminal for 32.768kHz X'tal oscillation
No
• Other functions:
General-purpose input port
XT2
Must be connected to VDD1 if not to be used.
• Output terminal for 32.768kHz X'tal oscillation
I/O
No
• Other functions:
General-purpose I/O port
Must be set for oscillation and kept open if not to be used.
CF1
I
Ceramic resonator input pin
No
CF2
O
Ceramic resonator output pin
No
Port Output Types
The table below lists the types of port outputs and the presence/absence of a pull-up resistor. Data can be read into any
input port even if it is in the output mode.
Port
Options selected
in units of
Option type
Output type
P00 to P07
1 bit
1
2
N-channel open drain
P10 to P17
1 bit
1
CMOS
Programmable
2
N-channel open drain
Programmable
1
CMOS
2
N-channel open drain
P20 to P27
CMOS
Pull-up resistor
Programmable (Note 1)
No
P30 to P36
PA0 to PA5
PC0 to PC7
PB0 to PB2
1 bit
PB4, PB6
PE0 to PE7
-
No
No
No
CMOS
Programmable
PF0 to PF7
P70
-
No
N-channel open drain
Programmable
P71 to P73
-
No
CMOS
Programmable
P80 to P87
-
No
N-channel open drain
No
SI2P0, SI2P2
-
No
CMOS
No
-
No
CMOS (when selected as ordinary port)
No
SI2P3
PWM0, PWM1
SI2P1
N-channel open drain
(when SIO2 data is selected)
XT1
-
No
Input only
No
XT2
-
No
Output for 32.768kHz crystal oscillator
No
N-channel open drain
(when in general-purpose output mode)
Note 1: Programmable pull-up resistors for port 0 are controlled in 4-bit units (P00 to P03, P04 to P07).
No.A0432-11/32
LC87F06J2A
Absolute Maximum Ratings at Ta = 25°C, VSS1 = VSS2 = VSS3 =VSS4=VSSVCO= 0V
Parameter
Symbol
Pins/Remarks
Specification
Conditions
VDD[V]
Maximum Supply
VDDMAX
voltage
VDD1, VDD2,
VDD3, VDD4,
VDD1=VDD2=VDD3=VDD4
=VDDVCO
=VDDODA
Input voltage
VI(1)
VDDVCO, VDDODA
XT1, CF1, RES
Input/Output
VIO(1)
Ports 0, 1, 2
Voltage
min
typ
max
-0.3
+6.5
-0.3
VDD+0.3
unit
V
Ports 3, 7, 8
Ports A, B, C, E, F
-0.3
SI2P0 to SI2P3
VDD+0.3
PWM0, PWM1,
XT2
Peak output
IOPH(1)
current
Ports 0, 1, 2, 3
CMOS output select per 1
Ports A, B, C, E, F
application pin
-10
SI2P0 to SI2P3
IOPH(2)
PWM0, PWM1
Per 1 application pin.
-20
IOPH(3)
P71 to P73
Per 1 application pin.
-5
IOMH(1)
Ports 0, 1, 2, 3
CMOS output select per 1
output current
Ports A, B, C, E, F
application pin
-10
(Note 1-1)
SI2P0 to SI2P3
-15
High level output current
Average
IOMH(2)
PWM0, PWM1
Per 1 application pin.
IOMH(3)
P71 to P73
Per 1 application pin.
-3
Total
ΣIOAH(1)
P71 to P73
Total of all applicable pins
-5
output
ΣIOAH(2)
PWM0, PWM1
Total of all applicable pins
current
SI2P0 to SI2P3
ΣIOAH(3)
Ports 0, 2, 3
Total of all applicable pins
ΣIOAH(4)
Port 0, 2, 3
Total of all applicable pins
PWM0, PWM1
-20
-30
-50
SI2P0 to SI2P3
ΣIOAH(5)
PB0 to PB2
Total of all applicable pins
-20
ΣIOAH(6)
Ports A, C
Total of all applicable pins
-20
ΣIOAH(7)
Ports A, C,
Total of all applicable pins
PB0 to PB2
ΣIOAH(8)
Peak output
mA
-40
Port F
Total of all applicable pins
-20
ΣIOAH(9)
Ports 1, E
Total of all applicable pins
-20
ΣIOAH(10)
Ports 1, E, F
Total of all applicable pins
-40
ΣIOAH(11)
PB4, PB6
Total of all applicable pins
-20
IOPL(1)
P02 to P07
Per 1 application pin.
current
Ports 1, 2, 3
Ports A, B, C, E, F
20
Low level output current
SI2P0 to SI2P3
PWM0, PWM1
Average
IOPL(2)
P00, P01
Per 1 application pin.
30
IOPL(3)
Ports 7, 8, XT2
Per 1 application pin.
10
IOML(1)
P02 to P07
Per 1 application pin.
output current
Ports 1, 2, 3
(Note 1-1)
Ports A, B, C, E, F
15
SI2P0 to SI2P3
PWM0, PWM1
IOML(2)
P00, P01
Per 1 application pin.
20
IOML(3)
Ports 7, 8, XT2
Per 1 application pin.
7.5
Note 1-1: Average output current is average of current in 100ms interval.
Continued on next page.
No.A0432-12/32
LC87F06J2A
Continued from preceding page.
Specification
Parameter
Symbol
Pins/Remarks
Conditions
VDD[V]
min
typ
max
unit
Total output
ΣIOAL(1)
Port 7, XT2
Total of all applicable pins
15
current
ΣIOAL(2)
Port 8
Total of all applicable pins
15
ΣIOAL(3)
Ports 7, 8, XT2
Total of all applicable pins
30
ΣIOAL(4)
PWM0, PWM1
Total of all applicable pins
40
Low level output current
SI2P0 to SI2P3
ΣIOAL(5)
Ports 0, 2, 3
Total of all applicable pins
ΣIOAL(6)
Ports 0, 2, 3
Total of all applicable pins
80
120
PWM0, PWM1
SI2P0 to SI2P3
ΣIOAL(7)
PB0 to PB2
ΣIOAL(8)
ΣIOAL(9)
mA
Total of all applicable pins
40
Ports A, C
Total of all applicable pins
40
Ports A, C
Total of all applicable pins
80
PB0 to PB2
Maximum power
ΣIOAL(10)
Port F
Total of all applicable pins
40
ΣIOAL(11)
Ports 1, E
Total of all applicable pins
70
ΣIOAL(12)
Ports 1, E, F
Total of all applicable pins
110
ΣIOAL(13)
PB4, PB6
Total of all applicable pins
40
Pd max
QIP100E(14×20)
523
consumption
Operating
Topr
temperature range
Storage
-20
70
-55
125
mW
°C
Tstg
temperature range
Recommended Operating Range at Ta = -20°C to +70°C, VSS1 = VSS2 = VSS3 = VSS4 = VSSVCO = 0V
Parameter
Symbol
Pins/Remarks
Specification
Conditions
VDD[V]
Operating
VDD(1)
supply voltage
(Note 2-1, 2-2)
Data-slicer
VDD(2)
Operating
=VDDVCO=VDDODA
VDD1=VDD2
VDD(3)
VDD1
max
4.5
5.5
1.47µs ≤ tCYC ≤ 200µs
2.7
5.5
4.75
5.25
2.0
5.5
2.0
5.5
unit
0.196µs ≤ tCYC ≤ 0.340µs
• X’tal HOLD mode
Day and time
• Base timer clock is subclock.
counter
• FsX’tal=32.768kHz by crystal
Operating
typ
0.196µs ≤ tCYC ≤ 200µs
=VDD3=VDD4
=VDDVCO=VDDODA
supply voltage
Base timer
VDD1=VDD2
=VDD3=VDD4
min
oscillation mode.
supply voltage
Memory
VHD
VDD1
sustaining
RAM and register contents in
HOLD mode.
supply voltage
High level
VIH(1)
input voltage
V
Ports 1, 2, 3, A
PB6
SI2P0 to SI2P3
P71 to P73
2.7 to 5.5
0.3VDD
+0.7
VDD
P70 port input /interrupt
side
VIH(2)
Ports 0, 8
PB0 to PB2, PB4
Ports C, E, F
2.7 to 5.5
0.3VDD
+0.7
VDD
PWM0, PWM1
VIH(3)
P70 Watchdog timer side
2.7 to 5.5
0.9VDD
VDD
VIH(4)
XT1, XT2, CF1, RES
2.7 to 5.5
0.75VDD
VDD
VIH(5)
P20, P24 Small signal
2.7 to 5.5
0.75VDD
VDD
input side
Note 2-1: VDD must be held greater than or equal to 4.5V in the flash ROM onboard programming mode.
Note 2-2: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at
a division ratio of 1/2.
Continued on next page.
No.A0432-13/32
LC87F06J2A
Continued from preceding page.
Parameter
Symbol
Pins/Remarks
Specification
Conditions
VDD[V]
Low level
VIL(1)
input voltage
min
typ
max
unit
Ports 1, 2, 3,A
PB6
SI2P0 to SI2P3
0.1VDD
2.7 to 5.5
VSS
2.7 to 5.5
VSS
2.7 to 5.5
VSS
2.7 to 5.5
VSS
0.25VDD
2.7 to 5.5
VSS
0.25VDD
5.0
1.4
2.0
2.6
5.0
0.7
1
1.3
+0.4
P71 to P73
P70 port input /interrupt
VIL(2)
Ports 0, 8
PB0 to PB2, PB4
Ports C, E, F
0.15VDD
+0.4
V
PWM0,PWM1
VIL(3)
Port 70 Watchdog
Timer
VIL(4)
XT1, XT2, CF1,
RES
VIL(5)
P20, P24 Small signal
input side
Composite
VCVD(1)
video signal
VCVD(2)
PB6(CVD)
2Vp-p input mode
0.8VDD
-1.0
1Vp-p input mode
input voltage
Vp-p
(Note 2-4)
Instruction
tCYC
Data-slicer Operating mode
cycle time
(Note 2-2)
Oscillation
FmCF(1)
CF1, CF2
frequency
15MHz ceramic oscillation
See Fig. 1.
Range
FmRC
Internal RC oscillation
(Note 2-3)
FmMRC
Frequency variable RC
oscillation source oscillation
FsX’tal
XT1, XT2
32.768kHz crystal oscillation.
See Fig. 2.
4.75 to 5.25
0.196
4.5 to 5.5
0.196
200
2.7 to 5.5
1.470
200
4.5 to 5.5
2.7 to 5.5
0.340
µs
15
0.3
1.0
2.7 to 5.5
16
2.7 to 5.5
32.768
2.0
MHz
kHz
Note 2-2: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at
a division ratio of 1/2.
Note 2-3: See Tables 1 and 2 for the oscillation constants.
Note 2-4: When setting DSLDACT register’s bit7 = 0, bit6 = 0. See diagram 9 for external circuit.
No.A0432-14/32
LC87F06J2A
Electrical Characteristics at Ta = -20°C to +70°C, VSS1 = VSS2 = VSS3 = VSS4 = VSSVCO = 0V
Parameter
Symbol
Pins/Remarks
Specification
Conditions
VDD[V]
High level input
IIH(1)
current
Ports 0, 1, 2
Output disable
Ports 3, 7, 8
Pull-up resistor OFF
Ports A, B, C, E, F
VIN=VDD
(including the off-leak current of
SI2P0 to SI2P3
RES
min
typ
max
unit
2.7 to 5.5
1
2.7 to 5.5
1
2.7 to 5.5
15
the output Tr.)
PWM0, PWM1
IIH(2)
Low level input
XT1, XT2
Using as an input port
IIH(3)
CF1
VIN=VDD
VIN=VDD
IIH(4)
P20, P24 Small
IIL(1)
current
signal input side
VIN=VBIAS+0.5
(VBIAS is bias voltage)
Ports 0, 1, 2
Output disable
Ports 3, 7, 8
Pull-up resistor OFF
Ports A, B, C, E, F
VIN=VSS
(including the off-leak current of
SI2P0 to SI2P3
RES
4.5 to 5.5
4.2
8.5
15
µA
2.7 to 5.5
-1
2.7 to 5.5
-1
the output Tr.)
PWM0, PWM1
IIL(2)
XT1, XT2
Using as an input port
IIL(3)
CF1
VIN=VSS
VIN=VSS
IIL(4)
P20, P24 Small
signal input side
2.7 to 5.5
-15
VIN=VBIAS+0.5
(VBIAS is bias voltage)
4.5 to 5.5
-15
High level output
VOH(1)
Ports 0, 1, 2, 3
IOH=-1.0mA
4.5 to 5.5
VDD-1
voltage
VOH(2)
Ports A, B, C, E, F
IOH=-0.4mA
3.0 to 5.5
VDD-0.4
SI2P0 to SI2P3
voltage
-4.2
VOH(3)
Ports 71, 72, 73
IOH=-0.4mA
3.0 to 5.5
VDD-0.4
VOH(4)
PWM0, PWM1
IOH=-10mA
4.5 to 5.5
VDD-1.5
VOH(5)
P30, P31(PWM4,
IOH=-1.6mA
3.0 to 5.5
VDD-0.4
4.5 to 5.5
1.5
3.0 to 5.5
0.4
5 output mode)
Low level output
-8.5
VOL(1)
Ports 0, 1, 2, 3
IOL=10mA
VOL(2)
Ports A, B, C, E, F
IOL=1.6mA
SI2P0 to SI2P3
V
PWM0, PWM1,
VOL(3)
P00, P01
VOL(4)
Pull-up resistation
IOL=30mA
4.5 to 5.5
1.5
IOL=5.0mA
3.0 to 5.5
0.4
VOL(5)
Ports 7, 8, XT2
IOL=1.6mA
3.0 to 5.5
Rpu(1)
Ports 0, 1, 2, 3
VOH=0.9VDD
4.5 to 5.5
15
40
70
Rpu(2)
Port 7
2.7 to 5.5
15
40
150
kΩ
Ports A, C, E, F
Hysteresis
VHYS(1)
Voltage
0.4
RES
Ports 1, 2, 3, 7, A
4.5 to 5.5
PB6
0.1VDD
V
SI2P0 to SI2P3
VHYS(2)
P20, P24 Small
signal input side
Pin capacitance
CP
All pins
4.5 to 5.5
0.1VDD
2.7 to 5.5
10
• For pins other than that under
test: VIN=VSS
• f=1MHz
pF
• Ta=25°C
Input voltage
Vsen
sensitivity
Bias Voltage
P20, P24 Small
4.5 to 5.5
signal input side
VBIAS
P20, P24 Small
signal input side
Composite video
signal input
VCLMP
PB6(CVD)
0.12VDD
Vp-p
5.0
0.5VDD
V
5.0
1.9
V
Pedestal voltage
clamping voltage
No.A0432-15/32
LC87F06J2A
Serial I/O Characteristics at Ta = -20°C to +70°C, VSS1 = VSS2 = VSS3 = VSS4 = VSSVCO = 0V
1. SIO0 Serial I/O Characteristics (Note 4-1-1)
Parameter
Symbol
Frequency
tSCK(1)
Low level
tSCKL(1)
Pins/
Remarks
SCK0(P12)
Specification
Conditions
VDD[V]
• See Fig. 6.
typ
max
unit
2
1
pulse width
High level
min
tSCKH(1)
1
pulse width
tSCKHA(1a)
• Continuous data
transmission/reception mode
• SIO2 is not in use
Input clock
simultaneous.
4
• Universal remote control
transmitter is not in use
2.7 to 5.5
tCYC
simultaneous.
• See Fig. 6.
• (Note 4-1-2)
tSCKHA(1b)
• Continuous data
transmission/reception mode
• SIO2 is in use simultaneous.
• Universal remote control
9
transmitter is in use
simultaneous.
Serial clock
• See Fig. 6.
• (Note 4-1-2)
Frequency
tSCK(2)
SCK0(P12)
• CMOS output selected.
4/3
• See Fig. 6.
Low level
tSCKL(2)
1/2
pulse idth
High level
tSCK
tSCKH(2)
1/2
pulse idth
tSCKHA(2a)
• Continuous data
transmission/reception mode
• SIO2 is not in use
Output clock
simultaneous.
• Universal remote control
transmitter is not in use
2.7 to 5.5
tSCKH(2)
tSCKH(2)
+2tCYC
+(10/3)tCYC
simultaneous.
• CMOS output selected.
• See Fig. 6.e
tSCKHA(2b)
tCYC
• Continuous data
transmission/reception mode
• SIO2 is in use simultaneous.
• Universal remote control
transmitter is in use
tSCKH(2)
tSCKH(2)
+2tCYC
+(25/3)tCYC
simultaneous.
• CMOS output selected.
• See Fig. 6.
Serial input
Data setup time
tsDI(1)
SI0(P11),
SB0(P11)
• Must be specified with respect
to rising edge of SIOCLK
• See fig. 6.
Data hold Time
thDI(1)
0.03
2.7 to 5.5
µs
0.03
Note 4-1-1: These specifications are theoretical values. Add margin depending on its use.
Note 4-1-2: To use serial-clock-input in continuous trans/rec mode, a time from SI0RUN being set when serial clock is
"H" to the first negative edge of the serial clock must be longer than tSCKHA.
Continued on next page.
No.A0432-16/32
LC87F06J2A
Continued from preceding page.
Parameter
Input clock
tdDO(1)
Pins/
SO0(P10),
Specification
Conditions
Remarks
SB0(P11)
time
VDD[V]
min
typ
• Continuous data
tdDO(2)
unit
+0.05
• Synchronous 8-bit mode.
1tCYC
• (Note 4-1-3)
+0.05
2.7 to 5.5
tdDO(3)
max
(1/3)tCYC
transmission/reception mode
• (Note 4-1-3)
Output clock
Serial output
Output delay
Symbol
µs
• (Note 4-1-3)
(1/3)tCYC
+0.05
Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of
output state change in open drain output mode. See Fig. 6.
2. SIO1 Serial I/O Characteristics (Note 4-2-1)
Input clock
Symbol
Frequency
tSCK(3)
Low level
tSCKL(3)
Pins/
SCK1(P15)
VDD[V]
• See Fig. 6.
Frequency
SCK1(P15)
• CMOS output selected.
tSCKL(4)
2
1/2
tSCK
tSCKH(4)
1/2
pulse width
Serial input
Data setup time
SI1(P14),
SB1(P14)
• Must be specified with respect
Data hold time
0.03
to rising edge of SIOCLK
• See fig. 6.
thDI(2)
2.7 to 5.5
0.03
Output delay time
Serial output
tsDI(2)
uni
1
2.7 to 5.5
pulse width
High level
max
1
• See Fig. 6.
Low level
typ
tCYC
tSCKH(3)
tSCK(4)
min
2
2.7 to 5.5
pulse width
High level
Specification
Conditions
Remarks
pulse width
Output clock
Serial clock
Parameter
tdDO(4)
SO1(P13),
SB1(P14)
µs
• Must be specified with respect
to falling edge of SIOCLK
• Must be specified as the time
to the beginning of output state
2.7 to 5.5
change in open drain output
(1/3)tCYC
+0.05
mode.
• See Fig. 6.
Note 4-2-1: These specifications are theoretical values. Add margin depending on its use.
No.A0432-17/32
LC87F06J2A
3. SIO2 Serial I/O Characteristics (Note 4-3-1)
Parameter
Symbol
Pins/
Frequency
tSCK(5)
SCK2
Low level
tSCKL(5)
(SI2P2)
Specification
Conditions
Remarks
VDD[V]
• See Fig. 6.
typ
max
unit
2
1
pulse width
High level
min
tSCKH(5)
1
Pulse width
tSCKHA(5a)
• Continuous data
transmission/reception mode
of SIO0 is not in use
simultaneous.
4
Input clock
• Universal remote control
transmitter is not in use
2.7to 5.5
tCYC
simultaneous.
• See Fig. 6.
• (Note 4-3-2)
tSCKHA(5b)
• Continuous data
transmission/reception mode
of SIO0 is in use simultaneous.
• Universal remote control
10
transmitter is in use
simultaneous.
Serial clock
• See Fig. 6.
• (Note 4-3-2)
Frequency
tSCK(6)
SCK2
• CMOS output selected.
Low level
tSCKL(6)
(SI2P2),
• See Fig. 6.
4/3
1/2
SCK2O
pulse width
High level
tSCKH(6)
pulse width
tSCKHA(6a)
(SI2P3)
tSCK
1/2
• Continuous data
transmission/reception mode
of SIO0 is not in use
tSCKH(6)
tSCKH(6)
• Universal remote control
+(5/3)
+(10/3)
transmitter is not in use
tCYC
tCYC
Output clock
simultaneous.
simultaneous.
2.7 to 5.5
• CMOS output selected.
• See Fig. 6.
tSCKHA(6b)
tCYC
• Continuous data
transmission/reception
mode of SIO0 is in use
simultaneous.
• Universal remote control
transmitter is in use
tSCKH(6)
tSCKH(6)
+(5/3)
+(28/3)
tCYC
tCYC
simultaneous.
• CMOS output elected.
• See Fig. 6.
Serial input
Data setup time
SI2(SI2P1),
SB2(SI2P1)
• Must be specified with respect
Data hold time
0.03
to rising edge of SIOCLK
• See fig. 6.
thDI(3)
2.7 to 5.5
0.03
Output delay time
Serial output
tsDI(3)
tdDO(5)
SO2(SI2P0)
SB2(SI2P1)
µs
• Must be specified with respect
to falling edge of SIOCLK
• Must be specified as the time
to the beginning of output state
change in open drain output
2.7 to 5.5
(1/3)tCYC
+0.05
mode.
• See Fig. 6.
Note 4-3-1: These specifications are theoretical values. Add margin depending on its use.
Note 4-3-2: To use serial-clock-input , a time from SI2RUN being set when serial clock is "H" to the first negative edge
of the serial clock must be longer than tSCKHA.
No.A0432-18/32
LC87F06J2A
4. SIO7, SIO8 Serial I/O Characteristics (Note 4-4-1)
Parameter
Low level
tSCK(7)
Pins/
VDD[V]
SCK7(PA2),
• See Fig. 6.
SCK8(PA5)
• (Note 4-4-2)
tSCKL(7)
Frequency
Low level
SCK7(PA2),
• CMOS output selected.
SCK8(PA5)
• See Fig. 6.
4/3
tSCKL(8)
1/2
2.7 to 5.5
tSCKH(8)
Serial input
SI7(PA1),
SI8(PA4),
thDI(4)
• Must be specified with respect
to rising edge of SIOCLK
• See fig. 6.
SB8(PA4)
0.03
2.7 to 5.5
0.03
Input clock
Output delay
tdDO(6)
SO7(PA0),
SB7(PA1),
time
SO8(PA3),
SB8(PA4)
• Must be specified with respect
to falling edge of SIOCLK
tdDO(7)
1tCYC
• Must be specified as the time
mode.
• See Fig. 6.
µs
+0.05
to the beginning of output state
change in open drain output
Output clock
Serial output
1.5
SB7(PA1),
Data hold time
tSCK
1/2
tSCKHA(8)
tsDI(4)
uni
1
pulse width
Data setup time
max
1
pulse width
High level
typ
tCYC
tSCKH(7)
tSCK(8)
min
2
2.7 to 5.5
pulse width
High level
Specification
Conditions
Remarks
pulse width
Output clock
Serial clock
Input clock
Frequency
Symbol
2.7 to 5.5
(1/3)tCYC
+0.05
Note 4-4-1: These specifications are theoretical values. Add margin depending on its use.
Note 4-4-2: When starting transmission/reception of SIO7(SIO8) using serial-clock-input, a time from
SI7RUN(SI8RUN) being set when serial clock is "H" to the first negative edge of the serial clock must be
longer than 1tCYC.
No.A0432-19/32
LC87F06J2A
Pulse Input Conditions at Ta = -20°C to +70°C, VSS1 = VSS2 = VSS3 = VSS4 = VSSVCO = 0V
Parameter
Symbol
Pins/Remarks
Specification
Conditions
VDD[V]
High/low level
tPIH(1)
INT0(P70),
• Interrupt source flag can be set.
pulse width
tPIL(1)
INT1(P71),
• Event inputs for timer 0 or 1 are
INT2(P72)
min
typ
max
unit
enabled.
INT4(P20 to P23),
2.7 to 5.5
1
2.7 to 5.5
2
INT5(P24 to P27),
INT6(P20),
INT7(P24)
tPIH(2)
INT3(P73) when
• Interrupt source flag can be set.
tPIL(2)
noise filter time
• Event inputs for timer 0 are
constant is 1/1.
enabled.
tPIH(3)
INT3(P73)
• Interrupt source flag can be set.
tPIL(3)
(The noise rejection
• Event inputs for timer 0 are
clock is selected to
enabled.
tCYC
2.7 to 5.5
64
2.7 to 5.5
256
2.7 to 5.5
1
2.7 to 5.5
200
1/32.)
tPIH(4)
INT3(P73)
• Interrupt source flag can be set.
tPIL(4)
(The noise rejection
• Event inputs for timer 0 are
clock is selected to
enabled.
1/128.)
tPIH(5)
HCTR(P22)
tPIL(5)
CSYNC(PB6)
tPIL(6)
RES
• Count clock inputs for H-counter
are enabled.
Reset acceptable
µs
AD Converter Characteristics at Ta = -20°C to +70°C, VSS1 = VSS2 = VSS3 = VSS4 = VSSVCO = 0V
Parameter
Symbol
Pins/Remarks
Specification
Conditions
VDD[V]
Resolution
N
AN0(P80)
Absolute
ET
to AN7(P87),
(Note 6-1)
AN8(PC1),
Conversion
AN9(PC2),
AD conversion time=32 × tCYC
AN10(PC3),
(when ADCR2=0)
TCAD
max
unit
8
bit
±1.5
12.54
97.92
(tCYC=
(tCYC=
AN11(PC4),
0.396µs)
3.06µs)
AN12(PE0),
47.04
97.92
(tCYC=
(tCYC=
1.47µs)
3.06µs)
(Note 6-2)
AN13(PE1),
4.5 to 5.5
3.0 to 5.5
AN14(PE2),
AN15(PE3)
AD conversion time=64 × tCYC
(when ADCR2=1)
Analog input
typ
3.0 to 5.5
precision
time
min
3.0 to 5.5
VAIN
(Note 6-2)
4.5 to 5.5
3.0 to 5.5
voltage range
Analog port
IAINH
VAIN=VDD
3.0 to 5.5
input current
IAINL
VAIN=VSS
3.0 to 5.5
12.54
97.92
(tCYC=
(tCYC=
0.198µs)
1.53µs)
VSS
VDD
1
LSB
µs
V
µA
-1
Note 6-1: The quantization error (±1/2 LSB) is excluded from the absolute accuracy value.
Note 6-2: The conversion time refers to the interval from the time the instruction for starting the converter is issued till
the complete digital value corresponding to the analog input value is loaded in the required register.
No.A0432-20/32
LC87F06J2A
Consumption Current Characteristics
at Ta = -20°C to +70°C, VSS1 = VSS2 = VSS3 = VSS4 = VSSVCO = 0V
Parameter
Normal mode
Symbol
IDDOP(1)
consumption
current
(Note 7-1)
Pins/
VDD[V]
VDD1
=VDD2
• FsX’tal=32.768kHz by crystal oscillation
=VDD3
=VDD4
• System clock set to 15MHz side
=VDDODA
=VDDVCO
Specification
Conditions
Remarks
min
typ
max
unit
• FmCF=15MHz ceramic oscillation mode
mode
• Internal RC oscillation stopped
• frequency variable RC oscillation stopped
4.75 to 5.25
17
38
4.5 to 5.5
10
24
• 1/1 frequency division ratio.
• Slicer PLL is in running.
• Slicer RC oscillation is in running.
• Data Slicer is in running.
IDDOP(2)
• FmCF=15MHz ceramic oscillation mode
• FsX’tal=32.768kHz by crystal oscillation
mode
• System clock set to 15MHz side
• Internal RC oscillation stopped
mA
• frequency variable RC oscillation stopped
• 1/1 frequency division ratio.
IDDOP(3)
• FmCF=0Hz(oscillation stopped)
• FsX’tal=32.768kHz by crystal oscillation
4.5 to 5.5
0.7
4.5
2.7 to 4.5
0.4
3
4.5 to 5.5
1.3
6
2.7 to 4.5
0.8
4.5
4.5 to 5.5
40
120
mode
IDDOP(4)
• System clock set to internal RC oscillation
• frequency variable RC oscillation stopped
•1/2 frequency division ratio.
IDDOP(5)
• FmCF=0Hz(oscillation stopped)
• FsX'tal=32.768kHz by crystal oscillation
mode.
IDDOP(6)
• System clock set to 1MHz with frequency
variable RC oscillation
• Internal RC oscillation stopped
• 1/2 frequency division ratio.
IDDOP(7)
• FmCF=0Hz(oscillation stopped)
• FsX'tal=32.768kHz by crystal oscillation
mode.
IDDOP(8)
µA
• System clock set to 32.768kHz side.
• Internal RC oscillation stopped
• frequency variable RC oscillation stopped
2.7 to 4.5
18
80
• 1/2 frequency division ratio.
Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up
resistors
Continued on next page.
No.A0432-21/32
LC87F06J2A
Continued from preceding page.
Parameter
HALT mode
Symbol
IDDHALT(1)
consumption
current
(Note 7-1)
Pins/
VDD1
=VDD2
Specification
Conditions
Remarks
VDD[V]
min
typ
max
unit
• HALT mode
• FmCF=15MHz ceramic oscillation mode
=VDD3
=VDD4
• FsX’tal=32.768kHz by crystal
=VDDVCO
=VDDODA
• System clock set to 15MHz side
oscillation mode
4.5 to 5.5
5
10
4.5 to 5.5
0.4
1.5
• Internal RC oscillation stopped
• frequency variable RC oscillation stopped
• 1/1 frequency division ratio.
• HALT mode
IDDHALT(2)
• FmCF=0Hz(oscillation stopped)
• FsX’tal=32.768kHz by crystal
oscillation mode
IDDHALT(3)
mA
• System clock set to internal RC oscillation
• frequency variable RC oscillation stopped
2.7 to 4.5
0.2
1
4.5 to 5.5
1.0
4.5
2.7 to 4.5
0.6
3.5
4.5 to 5.5
25
70
2.7 to 4.5
10
50
•1/2 frequency division ratio.
IDDHALT(4)
• HALT mode
• FmCF=0Hz(oscillation stopped)
• FsX'tal=32.768kHz by crystal
oscillation mode.
• System clock set to 1MHz with
IDDHALT(5)
frequency variable RC oscillation
• Internal RC oscillation stopped
• 1/2 frequency division ratio.
• HALT mode
IDDHALT(6)
• FmCF=0Hz(oscillation stopped)
• FsX'tal=32.768kHz by crystal
oscillation mode.
• System clock set to 32.768kHz side.
IDDHALT(7)
• Internal RC oscillation stopped
• frequency variable RC oscillation stopped
• 1/2 frequency division ratio.
Current drain
IDDHOLD(1)
VDD1
during HOLD
mode
Current drain
VDD1
during timebase clock
µA
4.5 to 5.5
0.085
20
2.7 to 4.5
0.02
15
4.5 to 5.5
21
60
2.7 to 4.5
7
40
• CF1=VDD or open (External clock mode)
IDDHOLD(2)
IDDHOLD(3)
• HOLD mode
• Timer HOLD mode
• CF1=VDD or open (External clock mode)
• FsX'tal=32.768kHz by crystal
IDDHOLD(4)
HOLD mode
oscillation mode
Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up
resistors
F-ROM Write Characteristics at Ta = +10°C to +55°C, VSS1 = VSS2 = VSS3 = VSS4 = VSSVCO = 0V
Parameter
Onboard
Symbol
IDDFW(1)
programming
Pins/
Remarks
VDD1
Specification
Conditions
VDD[V]
min
typ
max
unit
• 128-byte programming
• Erasing current including
4.5 to 5.5
25
40
mA
4.5 to 5.5
25
35
ms
current
Programming
time
tFW(1)
• 128-byte programming
• Erasing current including
• Time for setting up 128 byte data is excluded.
No.A0432-22/32
LC87F06J2A
UART(Full Duplex) Operating Conditions
at Ta = -20°C to +70°C, VSS1 = VSS2 = VSS3 = VSS4 = VSSVCO = 0V
Parameter
Symbol
Pins/Remarks
Specification
Conditions
VDD[V]
Clock rate
UBR,UBR2
min
typ
max
unit
8192/3
tCYC
UTX1(P32),
URX1(P33),
2.7 to 5.5
UTX2(P34),
16/3
URX2(P35)
Data length: 7,8,and 9 bits (LSB first)
Stop bits:
1 bit (2-bit in continuous data transmission)
Parity bits: Non
Example of Continuous 8-bit Data Transmission Mode Processing (First Transmit Data = 55H)
Start bit
Start of
transmission
Stop bit
Transmit data (LSB first)
End of
transmission
UBR,
UBR2
Example of Continuous 8-bit Data Reception Mode Processing (First Receive Data = 55H)
Stop bit
Start bit
Start of
reception
Received data (LSB first)
End of
reception
UBR,
UBR2
No.A0432-23/32
LC87F06J2A
Automatic transmission output characteristics
at Ta = -20°C to +70°C, VSS1 = VSS2 = VSS3 = VSS4 = VSSVCO = 0V
Parameter
Frequency
Symbol
tSCK(9)
Pins/
SCK7(PA2),
Specification
Conditions
Remarks
VDD[V]
See fig. 8.
tSCKL(9)
Input clock
tSCKLA(9)
unit
2
tSCKH(9)
2
pulse width
4.5 to 5.5
tSCKHA(9)
tBLKSEP(9a)
Serial clock
max
2
pulse width
High level
typ
4
• (Note10-1)
Low level
min
2
tCYC
See fig. 8.
4
• Transfer continuous data blocks
• (Note10-1)
tBLKSEP(9b)
See fig. 8.
• Transfer continuous data blocks with
4+
skipping S-number of data blocks
(2/3) •S
• (Note10-1)
Output clock
Frequency
Serial output
SCK7(PA2),
• CMOS output selected
26/3
• See fig. 8.
Low level
tSCKL(10)
pulse width
tSCKLA(10)
High level
tSCKH(10)
pulse width
tSCKHA(10)
Output delay
time
tSCK(10)
tdDO(8)
• (Note10-1)
1/2
4.5 to 5.5
1/2
tSCK
1/2
1.5
SB7(PA1)
• Must be specified with
respect to falling edge of SIOCLK
• Must be specified as the time to the
beginning of output state change in
4.5 to 5.5
1tCYC
+0.05
µs
open drain output mode.
• See fig. 8.
Note10-1: When starting transmission, a time from ECST begin set when serial clock is “H” to the first negative edge
of serial clock must be longer than the following.
(4 + (2/3) • S) • tCYC
S: Skipping number of data block when starting transmission.
No.A0432-24/32
LC87F06J2A
VDD1, VSS1 Terminal condition
It is necessary to place capacitors between VDD1 and VSS1 as describe below.
• Place capacitors as close to VDD1 and VSS1 as possible.
• Place capacitors so that the length of each terminal to the each leg of the capacitor be equal (L1 = L1’, L2 = L2’).
• Place high capacitance capacitor C1 and low capacitance capacitor C2 in parallel.
• Capacitance of C2 must be more than 0.05µF.
• Use thicker pattern for VDD1 and VSS1.
L2
L1
VSS1
C1
C2
VDD1
L1’
L2’
VDDVCO, VSSVCO Terminal condition
It is necessary to place capacitors between VDDVCO and VSSVCO as describe below.
• Place capacitors as close to VDDVCO and VSSVCO as possible.
• Place capacitors so that the length of each terminal to the each leg of the capacitor be equal (L3 = L3’, L4 = L4’).
• Place high capacitance capacitor C3 and low capacitance capacitor C4 in parallel.
• Capacitance of C4 must be more than 0.05µF.
• Use thicker pattern for VDDVCO and VSSVCO.
L3
L4
VSSVCO
C3
C4
VDDVCO
L4’
L3’
No.A0432-25/32
LC87F06J2A
Characteristics of a Sample Main System Clock Oscillation Circuit
Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a
SANYO-designated oscillation characteristics evaluation board and external components with circuit constant values
with which the oscillator vendor confirmed normal and stable oscillation
Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Oscillator
Nominal
Vendor
Frequency
Name
15MHz
MURATA
Circuit Constant
Oscillator Name
CSTCE15M0V53-R0
Operating
Oscillation
Voltage
Stabilization Time
C1
C2
Rd1
Range
typ
max
[pF]
[pF]
[Ω]
[V]
[ms]
[ms]
(15)
(15)
470
3.0 to 5.5
0.1
0.5
Remarks
Internal C1, C2
SMD-type
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized in
follwing cases (see Figure 4).
• The time interval that is required for the oscillation to get stabilized after VDD goes above the operating voltage lower
limit.
• The time interval that is required for the oscillation to get stabilized after the instruction for starting the mainclock
oscillation circuit is executed.
• The time interval that is required for the oscillation to get stabilized after the HOLD mode is reset and ocsillation is
started.
• The time interval that is required for the oscillation to get stabilized after the X'tal Hold mode, under the state which
the CFSTOP (bit 0 of the OCR register) = 0, is reset and ocsillation is started.
Characteristics of a Sample Subsystem Clock Oscillator Circuit
Given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a SANYOdesignated oscillation characteristics evaluation board and external components with circuit constant values with which
the oscillator vendor confirmed normal and stable oscillation.
Table 2 Characteristics of a Sample Subsystem Clock Oscillator Circuit with a Crystal Oscillator
Nominal
Frequency
32.768kHz
Vendor Name
EPSON
TOYOCOM
Circuit Constant
Oscillator
Name
Operating
Oscillation
Voltage
Stabilization Time
C3
C4
Rf1
Rd2
Range
typ
max
[pF]
[pF]
[Ω]
[Ω]
[V]
[s]
[s]
18
18
OPEN
560k
2.2 to 5.5
1.3
3.0
Remarks
Applicable
MC-306
CL value = 12.5pF
SMD-type
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized in
follwing cases (see Figure 4).
• The time interval that is required for the oscillation to get stabilized after VDD goes above the operating voltage lower
limit.
• The time interval that is required for the oscillation to get stabilized after the instruction for starting the subclock
oscillation circuit is executed.
• The time interval that is required for the oscillation to get stabilized after the Hold mode, under the state which the
EXTOSC (bit 6 of the OCR register) = 1, is reset and ocsillation is started.
• The time interval that is required for the oscillation to get stabilized after the Hold mode, under the state which the
DMSRUN (bit 7 of the DMSCNT register) = 1, is reset and ocsillation is started.
No.A0432-26/32
LC87F06J2A
Note: The components that are involved in oscillation should be placed as close to the IC and to one another as possible
because they are vulnerable to the influences of the circuit pattern.
CF1
XT1
CF2
XT2
Rd1
Rf1
C1
CF
C2
Rd2
C4
C3
X’tal
Figure 1 Ceramic Oscillation Circuit
Figure 2 Crystal Oscillation Circuit
0.5VDD
Figure 3 AC Timing Point
No.A0432-27/32
LC87F06J2A
VDD
VDD limit
Power Supply
GND
Reset time
RES
Internal RC
Resonator
tmsCF
CF1, CF2
tmsX’tal
XT1, XT2
Operating mode
Unfixed
Reset
Instruction execution mode
Reset Time and Oscillation Stabilization Time
HOLD release signal
HOLD release signal VALID
Internal RC
Resonator
tmsCF
CF1, CF2
tmsX’tal
XT1, XT2
Operation mode
HOLD
HALT
HOLD Reset Signal and Oscillation Stabilization Time
Figure 4 Oscillation Stabilization Time
No.A0432-28/32
LC87F06J2A
VDD
RRES
Note :
Select CRES and RRES value to assure that at least
200µs reset time is generated after the VDD becomes
higher than the minimum operating voltage.
RES
CRES
Figure 5 Reset Circuit
SIOCLK:
DATAIN:
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DI8
DATAOUT:
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
DO8
Data RAM transmission period
(only SIO0,2)
Continuous trans/rec interval
(only SIO7,8)
tSCK
tSCKL
tSCKH
SIOCLK:
tsDI
thDI
DATAIN:
tdDO
DATAOUT:
Data RAM transmission period
(only SIO0,2)
Continuous trans/rec interval
(only SIO7,8)
tSCKL
tSCKHA
SIOCLK:
tsDI
thDI
DATAIN:
tdDO
DATAOUT:
Figure 6 Serial I/O Waveforms
tPIL
tPIH
Figure 7 Pulse Input Timing Condition
No.A0432-29/32
LC87F06J2A
SIOCLK:
DATAOUT:
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
DO8
DO7
DO8
tSCK
tSCKL
tSCKH
SIOCLK:
tdDO
DATAOUT:
tSCKLA
tSCKHA
SIOCLK:
tdDO
DATAOUT:
SIOCLK:
DATAOUT:
DO0
DO1
DO2
DO3
DO4
DO5
DO6
Transmission
interval over
blocks
tSCKLA
tBLKSEP
SIOCLK:
tdDO
DATAOUT:
Figure 8 Automatic Transmission Output Waveforms
No.A0432-30/32
LC87F06J2A
Table 3 Cfcvd constants
Cfcvd
VPS/PDC/PAL-WSS
Antiope
OPEN
EPG-J
VBID
XDS-1X
820pF
XDS-2X
Composite Video Signal
1µF
220Ω
C-Video
Video Buffer
PB6/CVD/CSYNC
Cfcvd
Figure 9 Recommended CVD Circuit
1kΩ
PB4/FILTSLC
+
2.2µF
-
Cfs
VSSVCO
Cfs=OPEN
Figure 10 Recommended FILTSLC Circuit
No.A0432-31/32
LC87F06J2A
SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using
products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd.
products described or contained herein.
SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all
semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or
malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise
to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt
safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not
limited to protective circuits and error prevention circuits for safe design, redundant design, and structural
design.
In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are
controlled under any of applicable local export control laws and regulations, such products may require the
export license from the authorities concerned in accordance with the above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise,
without the prior written consent of SANYO Semiconductor Co.,Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the
SANYO Semiconductor Co.,Ltd. product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed
for volume production.
Upon using the technical information or products described herein, neither warranty nor license shall be granted
with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third
party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's
intellctual property rights which has resulted from the use of the technical information and products mentioned
above.
This catalog provides information as of January, 2007. Specifications and information herein are subject
to change without notice.
PS No.A0432-32/32