Preliminary Specifications CMOS LSI LE25FV101T 1M (128k words × 8bits) Serial Flash EEPROM Features CMOS Flash EEPROM Technology Single 3.3-Volt Read and Write Operations Sector Erase Capability: 256 Bytes per sector Operating Frequency: 10MHz Low Power Consumption Active Current (Read): 25 mA (Max.) Standby Current: 20 µA (Max.) Serial Peripheral Interface (S.P.I.) mode 0. High Read/Write Reliability Sector-write Endurance Cycles: 104 10 Years Data Retention Self-timed Erase and Programming Byte Programming: 35 µs (Max.) End of Write Detection: Status Register Read Hardware Data Protection Packages Available: MSOP8(225mil) Product Description Device Operation The LE25FV101T is a 128K x 8 CMOS sector erase, byte programmable serial Flash EEPROM. The LE25FV101T is manufactured using SANYO's proprietary, high performance CMOS Flash EEPROM technology. Breakthroughs in EEPROM cell design and process architecture attain better reliability and manufacturability compared with conventional approaches. The LE25FV101T erases and programs with a 3.3-volt only power supply. LE25FV101T conforms to Serial Peripheral Interface (S.P.I.). Commands are used to initiate the memory operation functions of the device. Commands are written to the command register through serial input (SI). The addresses and data of Commands are latched to be used to operate functions such as Read, Sector_Erase, Byte_Program and so on. Featuring high performance programming, the LE25FV101T typically byte programs in 35 µs. The LE25FV101T typically sector (256 bytes) erases in 4ms. Both program and erase times can be optimized using interface feature such as Status Register to indicate the completion of the write cycle. To protect against an inadvertent write, the LE25FV101T has on chip hardware data protection scheme. Designed, manufactured, and tested for a wide spectrum of applications, the LE25FV101T is offered with a guaranteed sector write endurance of 104 cycles. Data retention is rated greater than 10 years. Fig.3 and Fig.4 contain the timing waveforms of serial input and output. By setting CS to LOW, the device is selected. And commands, addresses, and dummy bits can be let in serially through SI port. When the device is in Read or Status Register Read mode, SO pin is in Low-impedance state. And the requested data can be read out from MSB (most significant bit) synchronously with the falling edge of SCK. WP 1 8 RESET Vcc 2 7 Vss CS 3 6 SO SCK 4 5 SI The LE25FV101T is best suited for applications that require re-programmable nonvolatile mass storage of program or data memory. Figure1: Pin Assignment for 8-pin MSOP *This product incorporate technology licensed from Silicon Storage Technology, Inc. This preliminary specification is subject to change without notice. SANYO Electric Co., Ltd. Semiconductor Company 1-1, 1 Chome, Sakata, Oizumi-machi, Ora-gun, GUNMA, 370-0596 JAPAN Revision c-November 1,1999-KI/ki-1/9 LE25FV101T 3.3V-only 1M-Bit Serial Flash EEPROM Preliminary Specifications XDECODER ADDRESS BUFFERS & LATCHES 1,048,576 Bit Flash EEPROM Cell Array Y-DECODER I/O B U F F E R S & DATA LATCHES CONTROL LOGIC SERIAL CS SCK INTERFACE SI SO WP RESET Figure2: Functional Block Diagram of LE25FV101T Table1: Pin Description Symbol Pin Description Functions SCK Serial Clock SI Serial Input To control the timing of serial data input and output. To latch input data and addresses synchronously at the rising edge of SCK, and read out output data synchronously at this falling edge. To input data or addresses serially from MSB to LSB (Least Significant Bit). SO Serial Output To output data serially from MSB to LSB. CS Chip Select WP Write Protect Vcc Power Supply To activate the device when this pin is LOW. To deselect and put the device to standby mode when High. To prevent inadvertent write when this pin is LOW. As WP is connected internally to the Vcc, leave this pin open when this function is not necessary. To provide 3.0V to 3.6V supply. Vss Ground RESET Reset To prevent inadvertent writes by setting this pin to LOW during system power-up. As RESET is connected to Vcc internally, leave this pin open when this function is not necessary. Table2: Commands Summary Command 1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle 5th bus cycle 6th bus cycle OPcode Address Address Address Data / OPcode Dummy FFH A23-A16 A15-A8 A7-A0 X X 20H A23-A16 A15-A8 X D0H X 10H A23-A16 A15-A8 A7-A0 PD X 9FH FFH Read Sector Erase Byte Program Status Register Reset Definition for table 2: 1. X= don't care, H= number in hex. 2. A17-A23=don't care 3. PD= Program data 4. Reset Command is effective when the device is only in Erase or Program sequence (in tBP or tSE period). SANYO Electric Co., Ltd. 2/9 LE25FV101T 3.3V-only 1M-Bit Serial Flash EEPROM Preliminary Specifications Command Definition Table 2 contains a command list and a brief summary of the commands. The following is a detailed description of the options initiated by each command. Read Fig.5 shows the timing waveform of read operation. The read operation is initiated by READ command. After writing OPcode of “FFH” and following 24bit address and 16 dummy bits, SO is transformed into Low-impedance state, and the specified addresses’ data are read out synchronously with SCK clock. While the SCK clock is continuously on, the device counts up the next address automatically and reads the data in order. When the address reaches its maximum, while the read operation still be continuing, the address is reset to the lowest one, and the device continues reading data from the beginning. When CS is set High so as to deselect the device, the read operation terminates with the output in Highimpedance state. Do not execute read operation while the device is in Byte_Program or Sector_Erase Cycle to prevent inadvertent writes. Status_Register Read Fig.6 shows the timing waveform of Status_Register Read. Status_Register can be read while the device is in Program or Erase mode. As is shown in the table below, the LSB (Least Significant Bit) of Status_Register is set to BSY with other bits intact. By setting CS to LOW and writing “9FH” in command register, the contents of the Status_Register come out from MSB. The LSB of the Status_Register stands for if the device is busy or not. Therefore,”0” stands for busy and “1” for not in Program or Erase mode. When CS goes High, Status Register reading terminates with the output pin in High-impedance state. 7(MSB) X 6 X 5 X 4 X 3 X 2 X 1 X 0(LSB) BSY Sector_Erase Fig.7 shows the timing waveform of Sector_Erase. Sector_Erase command consists of 6 bus cycles from 1st bus cycle to 6th bus cycle. This command stages the device for electrical erasing of all bytes within a sector. A sector contains 256 bytes. This sector erasability enhances the flexibility and usefulness of the LE25FV101T, since most applications only need to change a small number of bytes or sectors, not the entire chip. To execute the Sector_Erase operation, erase address, 2nd OPcode (D0H) and Dummy bits must be written to the command register after writing 1st OPcode of (20H). This two-step sequence ensures that only memory contents within the addressed sector are erased and other sectors are not inadvertently erased. The erase operation begins with the rising edge of the CS pulse and terminates automatically by using an internal timer. Termination of this mode is found out by using Status Register Read. Byte_Program Fig.8 shows the timing waveform of Byte_Program. Byte_Program command consists of 6 bus cycles from 1st bus cycle to 6th bus cycle, and stages the device for Byte programmable. To execute the Byte_Program operation, program address, program data and Dummy bits must be written to the command register after writing the OPcode of (10H). The program operation begins with the rising edge of the CS pulse and terminates automatically by using an internal timer. Termination of this mode is found out by using Status Register Read. Reset Fig.9 shows the timing waveform of Reset operation. Reset operation is effective while the device is already in Program or Erase mode. But the data of specified address are not guaranteed. The Reset Command can be provided as a means to safely abort the Erase or Program Command sequences. Following 4th bus cycles (erase or program) with a write of (FFH) in 5th bus cycle will safely abort the operation. Memory contents will not be altered. Hardware Write Protection Setting WP to LOW prevents inadvertent writes by inhibiting write operation. As WP is connected internally to the Vcc, don’t connect externally to any nodes when this function is not necessary. To prevent inadvertent writes during system power-up, LE25FV101T has power-onreset circuit. To perform power up more safely, the usage of RESET is recommended as follows. By holding RESET LOW during system power up and setting to High after Vcc reaches operation voltage, inadvertent writes can be prevented (see Fig.10). Don’t use this function except during power up. As RESET is connected to Vcc internally, don’t connect externally to any nodes when this function is not necessary. Decoupling Capacitors Ceramic capacitors (0.1 µF) must be added between VCC and VSS to each device to assure stable flash memory operation. SANYO Electric Co., Ltd. 3/9 LE25FV101T 3.3V-only 1M-Bit Serial Flash EEPROM Preliminary Specifications Absolute Maximum Stress Ratings Storage Temperature ..............................................................-55 °C ~ 150 °C Supply Voltage .......................................................................-0.5 V ~ 4.6 V D.C. Voltage on Any Pin to Grand Potential ...........................-0.5 V ~ Vcc + 0.5 V Permanent device damage may occur if ABSOLTE MAXIMUM RATINGS are exceeded. Operating Range Ambient Temperature.............................................................0 °C ~ 70 °C Vcc.........................................................................................3.0 V ~ 3.6 V DC Operating Characteristics Symbol Parameter Limit Min. ICCR Power Supply Current unit Test Condition Max. 10 mA SI = VIL / VIH, f = 10MHz, VCC = VCC max. (Read) ICCW SO, WP open CS = VIL Power Supply Current 45 mA 3 mA VCC = VCC max. (Write) ISB1 Standby Vcc Current CS = VIH (TTL input) ISB2 SO, WP , RESET open VCC = VCC max. Standby Vcc Current 20 µA CS = VCC–0.3V (CMOS input) SO, WP , RESET open VCC = VCC max. ILI Input Leakage Current 10 µA VIN = VSS ~ VCC, VCC = VCC max. ILO Output Leakage Current 10 µA VIN = VSS ~ VCC, VCC = VCC max. VIL Input Low Voltage –0.3 0.4 V VCC = VCC max. VIH Input High Voltage 2.4 Vcc+0.3 V VCC = VCC min. VOL Output Low Voltage 0.2 V IOL = 100 µA, VCC = VCC min. VOH Output High Voltage V IOH = –100 µA, VCC = VCC min. Vcc-0.2 Power-up Timing Minimum Units tPU_READ Symbol Power-up to Read Operation(without using RESET ) 10 ms tPU_WRITE Power-up to Write Operation(without using RESET ) 10 ms From RESET goes High to Command Entry 1 µs tPU_RST Parameter Capacitance (Ta = 25 °C, f = 1 MHz) Symbol CDQ Description DQ Pin Capacitance Maximum 12 CIN Input Capacitance Note: These parameters are periodically sampled and are not 100% tested. 6 Unit pF pF Test Condition VDQ = 0V VIN = 0V SANYO Electric Co., Ltd. 4/9 LE25FV101T 3.3V-only 1M-Bit Serial Flash EEPROM Preliminary Specifications AC Characteristics Symbol Parameter Limit Min. unit Max. fCLK Clock Frequency 10 tCSS CS setup time 400 ns tCSH CS hold time 400 ns tCPH CS standby pulse width 250 ns tCHZ CS to Hi-Z output tDS Data Setup time 30 ns tDH Data hold time 30 ns tCLH SCK High pulse width 45 ns tCLL SCK Low pulse width 45 ns tCLZ SCK to Lo-Z output 0 ns tV SCK to output valid tHO Output data hold time tSE Sector Erase Cycle Time 4 ms tBP Byte Program Cycle time 35 µs tRST Write Reset Recovery Time 4 µs 250 40 0 MHz ns ns ns AC Test Conditions Input Pulse Level ..................................................... 0 V ~ 3.0 V Input Rise/Fall Time.................................................. 5 ns Input/Output Timing Level ...................................... 1.5V Input Load Levels...................................................... 30 pF SANYO Electric Co., Ltd. 5/9 LE25FV101T 3.3V-only 1M-Bit Serial Flash EEPROM Preliminary Specifications Figure 3: Serial Input Timing Diagram tCPH CS SCK tcss tCSH tDS SI tDH DATA VALID High Impedance High Impedance SO Figure 4: Serial Output Timing Diagram CS tCLH tCLL tCSH SCK tHO tCLZ SO tCHZ DATA VALID tV SI SANYO Electric Co., Ltd. 6/9 LE25FV101T 3.3V-only 1M-Bit Serial Flash EEPROM Preliminary Specifications Figure 5: Read Cycle Timing Diagram CS 0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 40 47 48 55 56 63 64 71 SCK SI FFH Add. Add. Add. X X N High Impedance SO DATA MSB N+1 N+2 DATA DATA MSB MSB Figure 6: Status Register Read Timing Diagram CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 23 24 31 DATA DATA SCK SI SO 9FH High Impedance DATA MSB MSB MSB SANYO Electric Co., Ltd. 7/9 LE25FV101T 3.3V-only 1M-Bit Serial Flash EEPROM Preliminary Specifications Figure 7: Sector_Erase Timing Diagram Self-timed Sector Erase Cycle t SE CS 0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 40 47 SCK SI 20H Add. Add. X D0H X High Impedance SO Figure 8: Byte_Program Timing Diagram Self-timed Byte Program Cycle t BP CS 0 1 2 3 4 5 6 7 8 15 16 23 24 31 32 39 40 47 SCK SI SO 10H Add. Add. Add. PD X High Impedance SANYO Electric Co., Ltd. 8/9 LE25FV101T 3.3V-only 1M-Bit Serial Flash EEPROM Preliminary Specifications Figure 9: Reset Timing Diagram Reset Command is effective when the device is only in Erase or Program sequence (in tBP or tSE period). t RST CS 0 1 2 3 4 5 6 7 SCK SI SO FFH High Impedance Figure 10: Command Entry Recover Timing from RESET goes High Vcc t PU_RST RESET SANYO Electric Co., Ltd. 9/9