Ordering number : ENA0534 Bi-CMOS IC LV5044V 2ch step-down circuit DC-DC Converter Controller Overview The LV5044V is a high efficiency, 2-channel, step-down, DC-DC converter controller IC adopting a synchronous rectifying system. Incorporating numerous functions on a single chip with easy external setting, it can be used for a wide variety of applications. The device is optimal for use in multi-output power supply systems which are used in LCD-TVs, DVD recorders, game machines, high-end office products, etc. Features • Provides dual step-down DC-DC converter controller circuits integrated on the same chip. • Provides an input UVLO circuit, an overcurrent detection function, an overtemperature detection function, soft start/soft stop functions, and a startup delay circuit. • Output voltage monitoring functions (power good as well as OVP and UVP with timer latch functions) • 180° interleaved operation between phase 1 and phase 2 (supports multiphase drive in 2-phase parallel operation mode). • Supports synchronous operation between different devices (supports master/slave operation when multiple devices are used). Specifications Absolute Maximum Ratings at Ta = 25°C Parameter Supply voltage Peak output current Allowable power dissipation Symbol Conditions VIN Unit 18 IOUT Pd max Ratings V ±1.0 A 1 W *1 Operating temperature Topr -20 to +85 °C Storage temperature Tstg -55 to +150 °C *1 Board size: 114.3×76.1×1.6mm3, glass epoxy board. Continued on next page. Any and all SANYO Semiconductor products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO Semiconductor representative nearest you before usingany SANYO Semiconductor products described or contained herein in such applications. SANYO Semiconductor assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor products described or contained herein. N2806 MS PC 20060927-S00009 No.A0534-1/7 LV5044V Continued from preceding page. Parameter Symbol Conditions Ratings Unit Allowable pin voltage *2 1 HDRV1,2 18 V 6.5 V 18 V 6.5 V VLIN5+0.3 V CBOOT1,2 2 HDRV1,2 ,CBOOT1,2 to SW 3 VIN, ILIM1,2 RSNS1,2, SW1,2 PGOOD1,2 4 VLIN5 VDD, LDRV1,2 5 COMP1,2, FB1,2 SS1,2, UV_DELAY TD1,2, CT CLKO *2 Allowable pin voltages are referenced to the SGND and PGND pins, excluding No.2. No.2 Voltages are referenced to the SW pin. Recommended Operating Conditions at Ta = 25°C Parameter Supply voltage Symbol Conditions Ratings Unit VIN VIN and VLIN open. 7.5 to 16 V VIN VIN and VLIN short. 4.5 to 6.0 V Electrical Characteristics at Ta = 25°C, VIN = 12V Parameter Symbol Conditions Ratings min typ Unit max System Comparator reference voltage VREF Current drain 1 ICC1 TD1, TD2 = 5V (Excluding Ciss charge.) Current drain 2 ICC2 TD1, TD2 = 0V VLIN5 IVLIN5 = 0 to 10mA 5V supply voltage Overcurrent detection comparator VCLOS 0.818 0.826 0.834 2 4 6 mA 0.3 0.6 1.2 mA 4.75 5.00 5.25 -5 V V +5 mV µA offset Overcurrent detection reference ICL VIN = 10 to 14V 7.47 8.30 9.13 -7.0 current Soft start source current ISSSC TD1, TD2 = 5V -1.8 -3.5 Soft start sink current ISSSK TD1, TD2 = 0V 0.2 1.0 µA mA Soft start clamp voltage VSSTO 1.2 1.6 2.0 V UV_DELAY source current ISCUVD UV_DELAY = 2V -4.3 -8.6 -17.2 µA UV_DELAY sink current ISKUVD UV_DELAY = 2V 0.2 1.0 1.5 2.4 3.5 V 87 92 97 % UV_DELAY threshold voltage VUVD UV_DELAY operating voltage VUVD op VUVP detection hysteresis 100% at VFB = VREF ∆VUVP Overvoltage detection VOVP Overvoltage detection delay time VODLY Output discharge transistor VSWON mA 2 100% at VFB = VREF 112 117 % 122 5 10 % µS 1.0 20 Ω 10 µA on-resistance Output Block CBOOT leakage current ICBOOT VCBOOT = VSW + 6.5V HDRVx and LDRVX source current ISCDRV 1.0 HDRVx and LDRVX sink current ISKDRV 1.0 HDRVx low side on-resistance RHDRV IOUT=500mA 1.5 2.5 Ω LDRVx low side on-resistance RLDRV IOUT=500mA 1.5 2.5 Ω Simultaneous on prevention Tdead1 LDRV off → HDRV on 50 nS Tdead2 HDRV off → LDRV on 120 nS A A dead time 1 Simultaneous on prevention dead time 2 Continued on next page. No.A0534-2/7 LV5044V Continued from preceding page. Ratings Parameter Symbol Conditions min typ Unit max Oscillator Oscillator frequency fOSC CT = 130pF 280 330 kHz 1100 kHz Oscillator frequency range fOSC op Maximum on duty DON max CT = 130pF Minimum on time TON min CT = 130pF 100 VsawH fOSC = 300kHz 2.2 2.6 Sawtooth wave low side voltage VsawL fOSC = 300kHz 1 1.2 On time difference between ∆Tdead Sawtooth wave high side voltage 250 380 82 % nS V V 5 % channels 1 and 2 Error Amplifier Error amplifier input current IFB -200 -100 200 nA -100 -18 µA 700 900 µmho 1.5 2.0 2.5 dB 0.5 1.0 COMP pin source current ICOMPSC COMP pin sink current ICOMPSK 18 100 gm 500 GISNS Error amplifier gm Current detection amplifier gain µA Logic Output Sink current in the power good IpwrgdL VPGOOD = 0.4V IpwrgdH VPGOOD = 12V mA low state Leakage current in the power good µA 10 high state TD pin threshold level VONTD When the TD pin is stepped up 1.5 2.4 3.5 V VIN – VLIN5 open. 4.5 5.0 5.5 V ITDSC -1.8 -3.5 -7.0 µA ITDSK 0.8 2 5 mA TD pin open voltage VTDH TD pin source current during charge TD pin sink current during discharge CLKO high-level voltage VCLKOH ICLKO = 1mA CLKO low-level voltage VCLKOL ICLKO = 1mA 0.7VLIN5 V 0.3VLIN5 V 4.3 V Protection Functions VIN UVLO release voltage VUVLO 3.5 4.1 ∆VUVLO UVLO hysteresis 0.2 V Package Dimensions unit : mm 3191B Pd max -- Ta 9.75 0.5 5.6 7.6 16 30 1 15 0.65 0.15 0.22 1.5max (1.3) (0.33) Allowable power dissipation, Pd max -- W 1.2 Specified Substrate (114.3×76.1×1.6mm3) glass epoxy. 1.00 1.0 0.8 0.6 0.52 0.4 0.2 0 -20 0 20 40 60 80 100 OMG0618 0.1 Ambient temperture, Ta -- °C SANYO : SSOP30(275mil) No.A0534-3/7 LV5044V Pin Assignment VDD 1 30 PGND LDRV1 2 29 LDRV2 HDRV1 3 28 HDRV2 SW1 4 27 SW2 CBOOT1 5 26 CBOOT2 VLIN5 6 25 SGND COMP1 7 24 COMP2 FB1 8 23 FB2 9 22 RSNS2 ILIM1 10 21 ILIM2 TD1 11 20 TD2 SS1 12 19 SS2 PGOOD1 13 18 PGOOD2 UV_DELAY 14 17 CT VIN 15 16 CLKO LV5044V RSNS1 Top view No.A0534-4/7 LV5044V Block Diagram and Sample Application Circuit No.A0534-5/7 LV5044V Pin Functions Pin No. Pin 1 VDD 2 LDRV1 Function Gate drive power supply for the external low side MOSFETs. Connect this pin to VLIN5 through a filter. Channel 1 external low side MOSFET gate drive. This pin is also used as the signal input for short through prevention for the high and low side MOSFETs. HDRV cannot be turned on unless this pin's voltage goes below 1V. 3 HDRV1 4 SW1 Channel 1 external high side MOSFET gate drive. This pin is connected to the channel 1 switching node. The external high side MOSFET source and the low side MOSFET drain are connected to this pin.This pin becomes the return current route of pin HDRV. The drain of the discharging MOSFET used for the soft stop function is connected internal in the IC (typ.15Ω). This pin is also used as the signal input for short through prevention for the high and low side MOSFETs. LDRV cannot be turned on unless this pin's voltage goes below 1V referenced to PGND. 5 CBOOT1 Channel 1 bootstrap capacitor connection. The high side MOSFET gate drive power is supplied from this pin. This pin is connected to VDD through a diode and to SW1 through the bootstrap capacitor. 6 VLIN5 Internal 5V regulator output. The current is supplied from VIN. The power supply for the IC internal control circuits is also supplied from this pin. A bypass capacitor (6.8µF) is required between this pin and SGND. This pin is monitored by the UVLO function and the IC starts operating when it first rises above 4.0V. (After starting, the IC will only stop if this voltage falls below 3.8V.) 7 COMP1 Channel 1 phase compensation. The output of the internal transconductance amplifier is connected to this pin. The external phase compensation circuit between this pin and SGND. 8 FB1 Channel 1 feedback input. The transconductance amplifier inverting (−) input is connected to this pin. Provide the feedback potential to this pin by voltage dividing the output voltage. The converter operates so that this pin goes to the internal reference voltage VREF, 0.8V. This pin is also monitored by both the UVP comparator and the OVP comparator. If this pin voltage falls to under 87% of the set voltage, the PGOOD1 pin will go low and the UV_TIMER will operate. If this pin voltage rises to over 117% of the set voltage, the IC will latch in the off state. 9 RSNS1 Input for the channel 1 side overcurrent detection comparator and current detection amplifier. When resistor detection is used, connect the low side of the current detection resistor inserted between VIN and the drain of the external high side MOSFET to this pin. These connections must be wired independently so that the shared impedance with the main current with respect to the detected voltage does not affect this circuit. 10 ILIM1 Connection to the channel 1 overcurrent detection trip point. A 8.3µA (ILIM) sink constant-current supply is connected internal in the IC, and the overcurrent detection voltage ILIM × RLIM is generated by connecting the resistor RLIM between this pin and VIN. The voltage between VIN and ILIM is compared to the voltage across the terminals of either the current detection resistor RSNS or the high side MOSFET to detect the overcurrent state. 11 TD1 Channel 1 startup delay connection. The time until the IC starts up after the power-on reset (POR) is cleared is set by the capacitor connected between this pin and SGND. After the POR state is cleared, the external capacitor is charged by a 3.5µA constant current supplied internally by the IC. The IC starts operation when the voltage on this pin exceeds 2.4V. The IC goes to the standby state when the voltage on this pin is under 2.4V. If no external capacitor is connected to this pin, the IC will start as soon as the power-on reset is cleared. 12 SS1 Channel 1 soft start capacitor connection. After the power-on reset (POR) is cleared and the TD pin voltage exceeds 2.4V, this capacitor is charged by a 3.5µA internal constant current supply from the SS1 pin. This pin is connected to the transconductance amplifier's noninverting (+) input, and the ramp waveform of the SS1 pin is reflected in the ramped-up output waveform. After the UV_DELAY time out and the POR operates, this capacitor is discharged by the SS pin. 13 PGOOD1 Channel 1 power good pin. An IC internal 28V MOSFET open drain is connected to this pin. This pin outputs a low level if the channel 1 output voltage falls more than -13% relative to the set voltage. There is a hysteresis of about VREF × 1.5%. 14 UV_DELAY Channel 1 and channel 2 common UVP delay connection. The time until the IC switches off after the UVP state is detected is set by the capacitor connected between this pin and SGND. If either the channel 1 or channel 2 output voltage falls under -80% of the set voltage, an IC internal 8.6µA constant current source charges the external capacitor connected to this pin. When the voltage on this pin exceeds 2.4V, the IC switches off. If no external capacitor is connected, the IC turns off immediately upon detection of the UVP state. 15 VIN IC power supply. 16 CLKO Clock output. This pin outputs a clock signal synchronized with the CT pin oscillator waveform. When two or more LV5044V chips are operated in synchronization, connect the CT pin of the slave device to the SLKO pin of the master device. If two or more devices are operated in synchronization and the Td pin is used to change the startup timing between the devices, the device that starts the soonest will be the master. Continued on next page. No.A0534-6/7 LV5044V Continued from preceding page. Pin No. Pin Function 17 CT Connection for the oscillator circuit's external capacitor. Connect that capacitor between this pin and ground. When CT is 130pF, fOSC will be 330kHz. If an external clock is applied to this pin, the PWM control functions will operate at that clock frequency. If an external clock is provided, that signal must be a square wave with a low level of 0V and a high level between 3.3 and 5.0V. The square wave generator must have a fanout drive capacity of at least 1mA.and UV_DELAY function doesn't operate when this pin is grounded. 18 PGOOD2 19 SS2 20 TD2 21 ILIM2 22 RSENS1 23 FB2 24 COMP2 25 SGND Channel 2 power good pin. Channel 2 soft start function capacitor connection. Channel 2 startup delay connection. Channel 2 overcurrent detection trip point setting. Channel 2 overcurrent detection comparator input. Channel 2 feedback input. Channel 2 phase compensation. IC system ground. The reference voltage is generated referenced to this pin. The system ground must be connected to this pin. 26 CBOOT2 Channel 2 bootstrap capacitor connection. 27 SW2 28 HDRV2 This pin is connected to the channel 2 switching node. Channel 2 external high side MOSFET gate drive. 29 LDRV2 Channel 2 external low side MOSFET gate drive. 30 PGND Power system ground. This pin is used as the current return path for the LDRV pin. Specifications of any and all SANYO Semiconductor products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Semiconductor Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor products (including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Semiconductor Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO Semiconductor believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of November, 2006. Specifications and information herein are subject to change without notice. PS No.A0534-7/7