Ordering number : ENN7304 Thick-Film Hybrid IC STK672-330 Unipolar Fixed-Current Chopper (External-Excited PWM) Scheme and Built-in Phase Signal Distribution IC Two-Phase Stepping Motor Driver (Square Wave Drive) Output Current: 1.8 A The STK672-330 is a unipolar fixed-current chopper type 2-phase stepping motor driver hybrid IC. It features power MOSFETs in the output stage and a built-in phase signal distribution IC. The incorporation of a phase distribution IC allows the STK672-330 to control the speed of the motor based on the frequency of an external input clock signal. It supports two types of excitation for motor control: 2-phase excitation and 1-2 phase excitation. It also provides a function for switching the motor direction. The STK672-330 features an ENABLE pin, a function not provided in the STK672-110. When the ENABLE pin is set low while the clock signal is being supplied, all MOSFET devices are forced to the off state. When ENABLE is set high again later, the IC resumes operation, continuing with the prior excitation timing. • All inputs are Schmitt inputs. • The motor current can be set by changing the Vref pin voltage. Since a 0.195-Ω current detection resistor is built in, a current of 1 A is set for each 0.195 V of applied voltage. • The input frequency range for the clock signal used for motor speed control is 0 to 50 kHz. • Supply voltage ranges: VCC1 = 10 to 42 V, VCC2 = 5.0 V ±5% • This IC supports motor operating currents of up to 1.8 A at Tc = 105°C, and of up to 2.65 A at Tc = 25°C. • Provides a function that, during clock input, forces all MOSFET devices to the off state when the ENABLE pin is set low, and then, when ENABLE is set high, resumes operation continuing with the prior excitation timing. Applications Package Dimensions • Two-phase stepping motor drive in send/receive facsimile units • Paper feed in copiers, industrial robots, and other applications that require 2-phase stepping motor drive unit: mm 4192 [STK672-330] 3.3 29.5 5.1 • The motor speed can be controlled by the frequency of an external clock signal (the CLOCK pin signal). • The excitation type is switched according to the state (low or high) of the MODE pin. The mode is set to 2-phase or 1-2 phase excitation on the rising edge of the clock signal. • A motor direction switching pin (the CWB pin) is provided. 24.0 Features 1 12 0.4 9.0 Overview 2.9 0.5 1.0 2.0 11×2=22 Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft’s control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein. SANYO Electric Co.,Ltd. Semiconductor Company TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN 33103RM (OT) No. 7304-1/11 STK672-330 Specifications Maximum Rating at Tc = 25°C Parameter Symbol Conditions Ratings Unit Maximum supply voltage 1 VCC max No signal 52 Maximum supply voltage 2 VDD max No signal –0.3 to +7.0 V Input voltage VIN max Logic input pins –0.3 to +7.0 V VDD = 5 V, CLOCK ≥ 200 Hz Output current IOH max Repeated avalanche capacity Ear max Power loss Pd max Operating substrate temperature Tc max Junction temperature Tj max Storage temperature Tstg V 2.65 A 28 With an arbitrarily large heat sink. Per MOSFET mJ 6.5 W 105 °C 150 °C –40 to +125 °C Ratings Unit Allowable Operating Ranges at Ta = 25°C Parameter Symbol Conditions Supply voltage 1 VCC With signals applied 10 to 42 V Supply voltage 2 VDD With signals applied 5.0 ± 5% V Input voltage VIH 0 to VDD V Phase current 1 IOH1 Tc = 105°C, CLOCK ≥ 200 Hz 1.8 A IOH2 Tc = 80°C, CLOCK ≥ 200 Hz See the motor current (IOH) derating curve 2.1 A Phase current 2 Clock frequency fCL Phase driver withstand voltage Recommended operating substrate temperature range VDSS Tc Minimum pulse width: at least 10 µs 0 to 50 kHz ID = 1 mA (Tc = 25°C) 100 min V No condensation 0 to 105 °C Electrical Characteristics at Tc = 25°C, VCC = 24 V, VDD = 5 V Parameter VDD supply current Symbol Conditions ICCO CLOCK = GND Ioave With R/L = 3 Ω/3.8 mH in each phase Vref = 0.137 V FET diode forward voltage Vdf If = 1 A (RL = 23 Ω) Output saturation voltage Vsat RL = 23 Ω Output current Ratings min typ 0.36 Unit max 3.1 7 0.40 0.44 mA A 1.2 1.8 V 0.70 1.00 V High-level input voltage VIH Pins 8 to 12 (5 pins) Low-level input voltage VIL Pins 8 to 12 (5 pins) 0.6 V Input current IIL With pins 8 to 12 at the ground level. 10 µA Vref input voltage VrH Vref input bias current IIB PWM frequency fc Pin 7 2.5 V 0 With pin 7 at 1 V 35 3.5 V 50 500 nA 45 55 kHz Note: A fixed-voltage power supply must be used. No. 7304-2/11 Vref 7 ENABLE 12 RESETB 11 CWB 10 CLOCK 9 MODE 8 VDD 6 (5 V) ENABLE RESETB CWB CLOCK MODE Phase advance counter Excitation mode selection VSS Chopping circuit Phase excitation signal generation VDD AI BI CI FAB FBO FBB FAO F1 A 5 R1 F2 AB 4 F3 B 3 R2 F4 BB 2 ITF02169 1 GND STK672-330 Internal Equivalent Circuit Block Diagram No. 7304-3/11 STK672-330 Sample Application Circuit STK672-330 10 µF VDD = 5 V CO3 CLOCK + 6 9 MODE 8 CWB 10 ENABLE RO4 5V RO3 12 20 kΩ RESETB 10 µF CO4 5 4 3 11 5V 2 A VCC 24 V AB B BB + RO1 D1 + Two-phase stepping motor Vref 7 1 CO2 At least 100 µF GND P.GND 0.1 µF RO2 CO1 ITF02170 • To minimize noise in the 5-V system, locate the ground side of capacitor CO2 in the above circuit as close as possible to pin 1 of the IC. Also, if at all possible, the ground used for Vref must not be common to the P.GND pattern, but must be directly wired from pin 1. • Insert resistor RO3 (47 to 100 Ω) so that the discharge energy from capacitor CO4 is not directly applied to the CMOS IC in this hybrid device. If the diode D1 has Vf characteristics with Vf less than or equal to 0.6 V (when If = 0.1 A), this will be smaller than the CMOS IC input pin diode Vf. If this is the case RO3 may be replaced with a short without problem. • Both TTL and CMOS levels are used for the pin 8, 9, 10, 11 and 12 inputs. • Since the input pins do not have built-in pull-up resistors, when the open-collector type pins 8, 9, 10, 11, and 12 are used as inputs, a 10 to 47 kΩ pull-up resistor (to VDD) must be used. • To prevent incorrect operation due to chopping noise, we recommend inserting 470 to 1000 pF capacitors between pin 1 and each of the pins 8, 9, 10, and 12. (With the open-collector type IC, we also recommend inserting a 470 to 1000 pF capacitor between pin 11 (RESETB) and pin 1 when pin 11 is used as an input.) • The following circuit (for a lowered current of over 0.2 A) is recommended if the application needs to temporarily lower the motor current. Here, a value of close to 100 kΩ must be used for resistor RO1 to make the transistor output saturation voltage as low as possible. 5V 5V RO1 Vref RO1 RO3 Vref RO2 RO3 RO2 ITF02171 ITF02172 No. 7304-4/11 STK672-330 • Motor current peak value IOH setting IOH O IOH = Vref ÷ Rs Vref = (R02 ÷ (R01 + R02)) × 5 V (or 3.3 V) Rs is the hybrid IC internal current detection resistor. In the STK672-330 (and STK672-350) Rs is 0.195 Ω. (In the STK672-340 and STK672-360, Rs is 0.14 Ω.) ITF02173 Input Pin Functions (TTL input levels) Pin Pin No. Function Input conditions when operating CLOCK 9 Reference clock for motor phase current switching Operates on the rising edge of the signal MODE 8 Excitation mode selection Low: 2-phase excitation High: 1-2 phase excitation CWB 10 Motor direction switching Low: CW (forward) High: CCW (reverse) RESETB 11 System reset and A, AB, B, and BB outputs cutoff. Applications must apply a reset signal for at least 10 µs when VDD is first applied. A reset is applied by a low level ENABLE 12 The A, AB, B, and BB outputs are turned off, and after operation is restored by returning the ENABLE pin to the high level, operation continues with the same excitation timing as before the low-level input. The A, AB, B, and BB outputs are turned off by a low-level input. • A simple reset function is formed from D1, CO4, RO3, and RO4 in this application circuit. With the CLOCK input held low, when the 5-V supply voltage is brought up a reset is applied if the motor output phases A and BB are driven. If the 5-V supply voltage rise time is slow (over 50 ms), the motor output phases A and BB may not be driven. Increase the value of the capacitor CO4 and check circuit operation again. • See the timing chart for the concrete details on circuit operation. Usage Notes • STK672-330 input signal functions and timing (Specifications common to the STK672-340, 350, and 360 as well) (All inputs have no internal pull-up resistor and are TTL level Schmitt trigger inputs.) [RESETB and CLOCK (Input signal timing when power is first applied)] As shown in the timing chart, a RESETB signal input is required by the driver to operate with the timing in which the F1 gate is turned on first. The RESETB signal timing must be set up to have a width of at least 10 µs, as shown below. The capacitor CO4, and the resistors RO3 and RO4 in the application circuit form simple reset circuit that uses the RC time constant rising time. However, when designing the RESETB input based on VIH levels, the application must have the timing shown in figure 1. Rise of the 5-V supply voltage RESETB signal input At least 10 µs CLOCK signal At least 5 µs Figure 1 RESETB and CLOCK Signals Input Timing No. 7304-5/11 STK672-330 Note: In the STK672-350 and 360, the RESETB signal must be input at least 10 µs after the rise of the motor power supply VCC level (10 V, minimum), not after the rise of the 5 V power supply (4.5 V, minimum). CLOCK (Phase switching clock) • Input frequency: DC to 50 kHz • Minimum pulse width: 10 µs • Signals are read on the rising edge. CWB (Motor direction setting) The direction of rotation is switched by setting CWB to 1 (high) or 0 (low). See the timing charts for details on the operation of the outputs. Note: The state of the CWB input must not be changed during the 6.25 µs period before and after the rising edge of the CLOCK input. ENABLE (Forcible on/off control of the A, AB, B, and BB outputs, and selection of the operate or hold state for hybrid IC internal operation) ENABLE = 1 (high): Normal operation ENABLE = 0 (low): Outputs A, AB, B, and BB forced to the off state. If, during the state where CLOCK signal input is provided, the ENABLE pin is set to 0 (low) and then is later restored to the 1 (high) state, the IC will resume operation with the excitation timing continued from before the point ENABLE was set to 0 (low). MODE (Excitation mode selection) MODE = 0 (low): 2-phase excitation MODE = 1 (high): 1-2 phase excitation See the timing charts for details on output operation in these modes. Note: The state of the MODE input must not be changed during the 5 µs period before and after the rising edge of the CLOCK input. • Allowable motor current operating range The motor current (IO) must be held within the range corresponding to the area under the curve shown in figure 3. For example, if the operating substrate temperature Tc is 105°C, then IO must be held under IO max = 1.8 A, and in hold mode IO must be held under IO max = 1.5 A. No. 7304-6/11 STK672-330 • Thermal design [Operating range in which a heat sink is not used] The STK672-330 package has a structure that uses no screws, and is recommended for use without a heat sink. This section discusses the safe operating range when no heat sink is used. In the maximum ratings specifications, Tc max is specified to be 105°C, and when mounted in an actual end product system, the Tc max value must never be exceeded during operation. Tc can be expressed by formula (A) below, and thus the range for ∆Tc must be stipulated so that Tc is always under 105°C. Tc = Ta + ∆Tc (A) Ta: Hybrid IC (H-IC) ambient temperature, ∆Tc: Temperature increase across the aluminum substrate As shown in figure 5, the value of ∆Tc increases as the hybrid IC internal average power dissipation PD increases. As shown in figure 4, PD increases with the motor current. Here we describe the actual PD calculation using the example shown in the motor current timing chart in figure 2. Since there are periods when current flows and periods when the current is off during actual motor operation, PD cannot be determined from the data presented in figure 4. Therefore, we calculate PD assuming that actual motor operation consists of repetitions of the operation shown in figure 2. Motor phase current (sink side) ITF02175 Figure 2. Motor Current Timing T1: Motor rotation operation time T2: Motor hold operation time T3: Motor current off time T2 may be reduced, depending on the application. T0: Single repeated motor operating cycle IO1 and IO2: Motor current peak values Due to the structure of motor windings, the phase current is a positive and negative current with a pulse form. Note that figure 2 presents the concepts here, and that the on/off duty of the actual signals will differ. The hybrid IC (H-IC) internal average power dissipation PD can be calculated from the following formula. PD = (T1 × P1 + T2 × P2 + T3) ÷ T0 (I) (Here, P1 is the PD for IO1 and P2 is the PD for IO2) If the value calculated in formula (I) above is under 1.5 W, then from figure 5 we see that operation is allowed up to an ambient temperature Ta of 60°C. While the operating range when a heat sink is not used can be determined from formula (I) above, figure 4 is merely a single example of one operating mode for a single motor. For example, while figure 4 shows a 2-phase excitation motor, if 1-2 phase excitation is used with a 500-Hz clock frequency, the drive will be turned off for 25% of the time and the dissipation PD will be reduced to 75% of that in figure 4. It is extremely difficult for SANYO to calculate the internal average power dissipation PD for all possible end product conditions. After performing the above rough calculations, always install the hybrid IC (H-IC) in an actual end product and verify that the substrate temperature Tc does not rise above 105°C. No. 7304-7/11 STK672-330 Timing Chart 2-phase excitation MODE RESET CWB CLOCK ENABLE FAO FAB FBO FBB 1-2 phase excitation MODE RESET CWB CLOCK ENABLE FAO FAB FBO FBB No. 7304-8/11 STK672-330 1-2 phase excitation (CWB) MODE RESET CWB CLOCK ENABLE FAO FAB FBO FBB Switching from 2-phase to 1-2 phase excitation MODE RESET CWB CLOCK ENABLE FAO FAB FBO FBB No. 7304-9/11 STK672-330 1-2 phase excitation (ENABLE) MODE RESET CWB CLOCK ENABLE FAO FAB FBO FBB No. 7304-10/11 STK672-330 Figure 3 Figure 4 Hybrid IC internal average power dissipation, PD — W IOH — Tc 3.0 200 Hz, 2 phase excitation 2.5 Motor current, IOH — A Hold mode 2.0 1.5 1.0 0.5 0 0 10 Figure 5 Substrate temperature rise, ∆Tc — °C 80 20 30 40 50 60 70 80 90 100 110 Operating Substrate Temperature, Tc — °C ITF02176 ∆Tc — PD PD — IOH 14 VCC = 24 V, VDD = 5.0 V 500 Hz, 2 phase excitation Motor R = 0.63 Ω I = 0.62 mH The data are peak values. 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0.5 1.0 1.5 2.0 Motor current, IOH — °C 2.5 3.0 ITF02177 70 60 50 40 30 20 10 00 0.5 1.0 1.5 2.0 2.5 3.0 Hybrid IC internal average power dissipation, PD — W 3.5 ITF02178 Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer’s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer’s products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification” for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of March, 2003. Specifications and information herein are subject to change without notice. PS No. 7304-11/11