SC1403 Mobile Multi-Output PWM Controller with Lossless Current Sense POWER MANAGEMENT Description Features 3.3V and 5V dual synchronous outputs, resistor The SC1403 is a multiple-output power supply controller designed to power battery operated systems. The SC1403 provides synchronous buck converter control for two (3.3V and 5V) power supplies. An efficiency of 95% can be achieved for the two supplies. The SC1403 uses Semtech’s proprietary Virtual Current Sense™ technology along with external error amplifier compensation to achieve enhanced stability and DC accuracy over a wide range of output filter components while maintaining fixed frequency operation. Lossless current sensing can be used to eliminate current sense resistors and reduce cost. The SC1403 also provides a 5V linear regulator for system housekeeping. The 5V linear regulator is derived from the battery; for improved efficiency, the output is switched to the 5V output when available. Control functions include power-up sequencing, soft start, power-good signaling, and frequency synchronization. Line and load regulation is to +/-1%. The internal oscillator can be set to 200kHz, 300kHz, or synchronized to an external clock. The mosfet drivers provide >1A peak drive current for fast mosfet switching. programmable to 2.5V Fixed frequency or PSAVE operation for maximum efficiency over wide load range 5V / 50mA linear regulator Virtual Current Sense™ for enhanced stability Lossless current limiting Out of phase switching reduces input capacitance External compensation supports wide range of output filter components Programmable power-up sequence Power Good output Output overvoltage and overcurrent protection with output undervoltage shutdown 6µA typical shutdown current 6mW typical quiescent power Applications Notebook and subnotebook computers Tablet PCs Embedded applications The SC1403 includes a PSAVE# input to select pulse skipping mode for high efficiency at light load, or fixed frequency mode for low noise operation. Typical Application Circuit Revision 5, April 2004 1 United States Patent No. 6,377,032 www.semtech.com SC1403 POWER MANAGEMENT Absolute Maximum Ratings PRELIMINARY Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. PAR AMETER D ESC R IPTION MAXIMU M U N ITS Supply and Phase Voltages -0.3 to +30 V PHASE3, PHASE5 to GND Phase Voltages -2.0 (transi ent - 100 nsec) V BST3, BST5, D H3, D H5 to GND Boost voltages -0.3 to +36 V Power Ground to Si gnal Ground ± 0.3 V Logi c Supply -0.3 to +6 V Hi gh-si de Gate D ri ve Supply -0.3 to +6 V Hi gh-si de Gate D ri ve Outputs -0.3 to (+BSTx + 0.3) V Low-si de Gate D ri ve Outputs and C urrent Sense i nputs -0.3 to +(VL + 0.3) V Logi c i nputs/outputs -0.3 to +(VL + 0.3) V ON3, SHD N# to GND -0.3 to +(V+ + 0.3V) V VL, REF Short to GND C onti nuous VD D , V+, PHASE3, PHASE5 to GND PGND to GND VL to GND BST3 to PHASE3; D H3 to PHASE3; BST5 to PHASE5; D H5 to PHASE5 D L3, D L5 to GND C SL5, C SH5, C SL3, C SH3 to GND REF, SYNC , SEQ, PSAVE#, ON5, RESET#, VL, FB3, FB5, C OMP3, C OMP5 to GND REF C urrent +5 mA +50 mA Juncti on Temperature Range +150 °C juncti on to ambi ent 76 °C /Watt TS Storage Temperature Range -65 to +200 °C TL Lead Temperature +300 °C , 10 second max. °C VL C urrent TJ Package Thermal Resi stance Electrical Characteristics Unless otherwise noted: V+ = 15V, both PWMs on, SYNC = 0V, VL load = 0mA, REF load = 0mA, PSAVE# = 0V, TA =-40 to 85°C. Typical values are at TA = +25°C. Circuit = Typical Application Circuit Parameter C onditions Min Typ Max U nits 30.0 V MAIN SMPS C ON TR OLLER S Input Voltage Range FB3, FB5 range - Adjustable Mode 6.0 V+ = 6.0 to 30V, C SLx = FBx, Output Load = 0A to current li mi t 2.45 2.5 2.55 V 3.3V Output - Fi xed Mode V+ = 6.0 to 30V, FB3 = 0V, 3V Load = 0A to current li mi t 3.23 3.3 3.37 V 5V Output - Fi xed Mode V+ = 6.0 to 30V, FB5 = 0V, 5V Load = 0A to current li mi t 4.9 5.0 5.1 V Ei ther SMPS REF 5.5 V Measured at FB3/FB5 0.5 1.1 V Output Voltage Adjust Range Adjustable Mode Threshold 0.8 Load Regulati on Ei ther SMPS, 0A to current li mi t -0.4 Li ne Regulati on Ei ther SMPS, 6.0V < V+ <30; PSAVE# = VL 0.05 2004 Semtech Corp. 2 % United States Patent No. 6,377,032 www.semtech.com SC1403 POWER MANAGEMENT Electrical Characteristics (Cont.) Unless otherwise noted: V+ = 15V, both PWMs on, SYNC = 0V, VL load = 0mA, REF load = 0mA, PSAVE# = 0V, TA =-40 to 85°C. Typical values are at TA = +25°C. Circuit = Typical Application Circuit PAR AMETER Current-Limit Thresholds (2) CONDITIONS MI N T YP MAX UNITS CSHX - CSLX (positive current) 40 55 70 mV CSHX - CSLX (negative current) -50 Zero Crossing Threshold CSHX - CSLX PSAVE# = 0V, not tested 5 mV Soft-Star t Ramp Time From enable to 95% full current limit, with respect to fOSC 512 clks Oscillator Frequency SYN C = VL SYN C = 0V 220 170 300 200 Maximum Duty Factor SYN C = VL SYN C = 0V 92 94 94 96 % SYN C Input High Pulse N ot tested 300 ns SYN C Input Low Pulse Width N ot tested 300 SYN C Rise/Fall Time N ot tested 200 SYN C Input Frequency Range 380 230 240 350 CSH3, CSH5 Input Leakage Current kHz kHz CSH3 = 3.3V, CSH5 = 5.0V 3 10 µA From internal feedback node to COMP3/COMP5 18 V/V 8 MHz 25 Kohms ER R OR AMP DC Loop Gain Gain Bandwidth Product Output Resistance COMP3, COMP5 INTER NAL R EGULATOR AND R EFER ENCE VL Output Voltage VL Undervoltage Lockout Fault Threshold VL Switchover Lockout SHDN # = V+; 6V < V+ <30V, 0mA < ILOAD < 30mA, ON 3 = ON 5 = 0V 4.6 Falling edge, hysteresis = 0.7V 3.5 Switchover at star tup - rising edge 5.25 3.7 4.1 4.5 REF Output Voltage N o external load REF Load Regulation 0µA < ILOAD < 50µA 12.5 0mA < ILOAD < 5mA 50 2004 Semtech Corp. 3 V 2.45 2.5 2.55 mV United States Patent No. 6,377,032 www.semtech.com SC1403 POWER MANAGEMENT Electrical Characteristics (Cont.) PRELIMINARY Unless otherwise noted: V+ = 15V, both PWMs on, SYNC = 0V, VL load = 0mA, REF load = 0mA, PSAVE# = 0V, TA =-40 to 85°C. Typical values are at TA = +25°C. Circuit = Typical Application Circuit Parameter REF Sink Current REF Fault Lockout Voltage V+ Operating Supply Current V+ Standby Supply Current V+ Shutdown Supply Current Quiescent Power Consumption Conditions Min 10mV rise in REF Falling edge Typ 10 1.8 VL switched over to VOUT5, both SMPS on, ILoad3 = 0A, ILoad5 = 0A 10 V+ = 6V to 30V, SMPS off, includes current into SHDN# 300 V+ = 6V to 30V, SHDN# = 0V Max -1 3 SMPS enabled, FB3 = FB5 = 0V, No Load on SMPS Units µA 2.2 V 50 µA 15 6 mW FAULT DETECTION Overvoltage Trip Threshold Overvoltage-Fault Propagation Delay Output Undervoltage Threshold With respect to unloaded output voltage 7 11 Output driven 2% above overvoltage trip VTH 15 1.5 % µs With respect to unloaded output voltage 65 75 85 % Output Undervoltage Lockout Time From each SMPS enabled, with respect to f OSC 5000 6144 7000 clks Thermal Shutdown Threshold Typical hysteresis = +10°C 150 °C R E S E T# RESET# Trip Threshold RESET# Propagation Delay RESET# Delay Time With respect to unloaded output voltage, falling edge; typical hysteresis = 1% -12 Falling edge, output driven 2% below RESET# trip threshold -9 -5 1.5 With respect to fOSC 27,000 FB3, FB5 = 2.6V -1 32,000 % µs 37,000 clks 1 µA 0.6 V INPUTS AND OUTPUTS Feedback Input Leakage Current Logic Input Low Voltage ON3, PSAVE#, ON5, SHDN#, SYNC (SEQ = REF) Logic Input High Voltage ON3, PSAVE#, ON5, SHDN#, SYNC (SEQ = REF) 2004 Semtech Corp. 4 2.4 V United States Patent No. 6,377,032 www.semtech.com SC1403 POWER MANAGEMENT Electrical Characteristics (Cont.) Unless otherwise noted: V+ = 15V, both PWMs on, SYNC = 0V, VL load = 0mA, REF load = 0mA, PSAVE# = 0V, TA =-40 to 85°C. Typical values are at TA = +25°C. Circuit = Typical Application Circuit PAR AMETER CONDITIONS MI N MAX UNITS -1 1 µA 2 Input Leakage Current PSAVE#, ON 5, SYN C SEQ = REF ON 3 Input Leakage Current ON 3 = 15V -2 SHDN # = 15V -1 SHDN # Input Leakage Current T YP 3 10 µA 0.4 V Logic Output Low Voltage RESET#, ISIN K = 4mA Logic Output High Current RESET# = 3.5V 1 mA ON 5 Pull-down Resistance ON 5, RUN /ON 3 = 0V, (SEQ = REF) 100 ohms Gate Driver Sink/Source Current DL3, DH3, DL5, DH5, forced to 2.5V 1 A Gate Driver On-Resistance BST3 to DH3, DH3 to PHASE3, BST5 to DH5, DH5 to PHASE5, VL to DL3, DL3 to PGN D, VL to DL5, DL5 to PGN D 1.5 N on-Overlap Threshold PHASE3, PHASE5, DL3, or DL5 1.0 Shoot-through Delay DHx falling edge to DLx rising edge DLx falling edge to DHz rising edge (1V threshold on DHx and DLx, no external capacitance on DLx/DHx.) 10 35 17 75 7 ohms V 25 115 nsec Note: (1) This device is ESD sensitive. Use of standard ESD handling procedures required. (2) Applicable for TA = 0 to +85°C 2004 Semtech Corp. 5 United States Patent No. 6,377,032 www.semtech.com SC1403 POWER MANAGEMENT Pin Configuration PRELIMINARY Ordering Information TOP VIEW CSH3 1 28 ON3 CSL3 2 27 DH3 FB3 3 26 PHASE3 COMP3 4 25 BST3 COMP5 5 24 DL3 SYNC 6 23 SHDN# ON5 7 22 V+ GND 8 21 VL REF 9 20 PGND PSAVE# 10 19 DL5 RESET# 11 18 BST5 FB5 12 17 PHASE5 CSL5 13 16 DH5 CSH5 14 15 SEQ Device P ackag e Temp. (TA) SC1403ITSTR TSSOP-28 -40 - +85°C SC1403ITSTRT TSSOP-28 Lead-free option -40 - +85°C Note: (1) Only available in tape and reel packaging. A reel contains 2500 devices. (28 Pin TSSOP) Block Diagram 2004 Semtech Corp. 6 United States Patent No. 6,377,032 www.semtech.com SC1403 POWER MANAGEMENT Pin Descriptions Pin # Pin Name Pin Function 1 CSH3 High-side current sense input for 3.3V SMPS. Connect to the high side of the DCR RC network, or to the inductor side of a current sense resistor. 2 C S L3 Low side current sense input for 3.3V SMPS. For adjustable mode operation, connect to the 3.3V output, at either the low side of the DCR RC network, or the output side of a current sense resistor. For fixed-output operation, FB3 is grounded, and CSL3 also operates as the feedback sense input for the 3.3V SMPS. 3 FB 3 4 COMP3 Compensation output of the 3.3V error amplifier. 5 COMP5 Compensation output of the 5.0V error amplifier. 6 SYNC 7 ON5 5V ON/OFF Control Input. Connect a 1K - 10K ohm resistor in series with ON5 to allow 5V shutdown. 8 GND Low noise Analog Ground and Feedback reference point. 9 REF 2.5V Reference Voltage Output. Bypass to GND with 1 µF minimum. 10 PSAVE# Logic Control Input that disables PSAVE Mode when high. Connect to GND for normal use. 11 RESET# Active Low Timed Reset Output. RESET# swings GND to VL. Goes high after a fixed 32,000 clock cycle delay following a successful power up. 12 FB 5 13 C S L5 Low side current sense input for 5V SMPS. For adjustable mode operation, connect to the 5V output, at either the low side of the DCR RC network, or the output side of a current sense resistor. For fixed-output operation, FB5 is grounded, and CSL5 also operates as the feedback sense input for the 5V SMPS. 14 CSH5 High-side current sense input for 5V SMPS. Connect to the high side of the DCR RC network, or to the inductor side of a current sense resistor. 15 SEQ Input that selects SMPS sequence for RESET#. 16 DH5 Gate Drive Output for the 5V, high side N-Channel switch. 17 PHASE5 18 BST5 Feedback Input for the 3.3V SMPS. In adjustable mode (using external feedback resistors), FB3 regulates to REF (2.5V). When FB3 is grounded, internal resistors set a fixed 3.3V output. Oscillator Synchronization and Frequency Select. Tie to VL for 300kHz operation; tie to GND for 200kHz. Drive externally to synchronize between 240kHz and 350kHz. Feedback Input for the 5V SMPS. In adjustable mode (using external feedback resistors), FB3 regulates to REF (2.5V). When FB5 is grounded, internal resistors set a fixed 5V output. 5V SMPS Switching Node (inductor) connection. Boost capacitor connection for 5V high side gate drive. Note: All logic level inputs and outputs are open collector TTL compatible. 2004 Semtech Corp. 7 United States Patent No. 6,377,032 www.semtech.com SC1403 POWER MANAGEMENT Pin Descriptions (Cont.) Pin # Pin N ame PRELIMINARY Pin Function 19 D L5 Gate D ri ve Output for the 5V low si de synchronous recti fi er MOSFET. 20 PGND 21 VL 5V Internal Li near Regulator Output. For i mproved effi ci ency, VL connects to 5V SMPS output when 5V SMPS i s enabled. 22 V+ Battery Voltage Input. 23 SHD N# 24 D L3 25 BST3 26 PHASE3 27 D H3 Gate D ri ve Output for the 3.3V, hi gh si de N-C hannel swi tch. 28 ON3 3.3V ON/OFF C ontrol Input. Power Ground. Shutdown C ontrol Input, acti ve low. Gate D ri ve Output for the 3.3V low si de synchronous recti fi er MOSFET. Boost C apaci tor C onnecti on for 3.3V hi gh si de gate dri ve. 3.3V Swi tchi ng Node (i nductor) C onnecti on. Note: All logic level inputs and outputs are open collector TTL compatible. Block Diagram 2004 Semtech Corp. 8 United States Patent No. 6,377,032 www.semtech.com SC1403 POWER MANAGEMENT Functional Information Under light load conditions when the PSAVE# pin is low, the SC1403 operates as a hysteretic controller in the discontinuous conduction mode to reduce its switching frequency and switching bias current. The switching of the output mosfet does not depend on a given oscillator frequency, but on the hysteretic feedback voltage set around the reference. When entering PSAVE# mode, if the minimum (valley) inductor current measured across the CSH and CSL pins is below the PSAVE# threshold for four switching cycles, the virtual current sensing circuitry is shutdown and PWM switches from forced continuous to hysteretic mode. If the minimum (valley) inductor current is above the threshold for four switching cycles, PWM control changes from hysteretic to forced continuous mode. The SC1403 provides built-in hysteresis to inhibit chattering between the two modes of operation. Detailed Description The SC1403 is a versatile multiple-output power supply controller designed to power battery operated systems. The SC1403 provides synchronous rectified buck control in fixed frequency forcedcontinuous mode and hysteretic PSAVE mode, for two switching power supplies over a wide load range. Out of phase switching improves signal quality and reduces input RMS current, therefore reducing size of input filter inductors and capacitors. Lossless current sensing eliminates the need for discrete current sense resistors. The two switchers have on-chip preset output voltages of 5.0V and 3.3V. An external resistor divider can be used to set the switcher outputs from 2.5V to 5.5V. The control circuitry for each PWM controller includes digital softstart, voltage error amplifier with built-in slope compensation, pulse width modulator, power save, overcurrent, overvoltage and undervoltage fault protection. One linear regulator and a precision reference voltage are also provided. The 5V/30mA linear regulator uses battery power to feed the gate drivers; for improved efficiency the 5V switcher output is used instead when available. Semtech’s proprietary Virtual Current SenseTM provides greater advantages in the aspect of stability and signal-to-noise ratio than the conventional current sense method. Gate Drive / Control The gate drivers on the SC1403 are designed to switch large mosfets up to 350kHz. The high-side gate driver is required to drive the gates of high-side mosfet above the V+ input. The supply for the gate drivers is generated by charging a boostrap capacitor from the VL supply when the low-side driver is on. Monitoring circuitry ensures that the bootstrap capacitor is charged when coming out of shutdown or fault conditions where the bootstrap capacitor may be depleted. In continuous conduction mode, the low-side driver output that controls the synchronous rectifier in the power stage is on when the high-side driver is off. Under light load conditions when PSAVE# pin is low, the inductor ripple current will approach the point where it reverses polarity. This is detected by the low-side driver control and the synchronous rectifier is turned off before the current reverses, preventing energy drain from the output. The low-side driver operation is also affected by various fault conditions as described in the Fault Protection section. PWM Control There are two separate PWM control blocks for each switcher. They are switched out-of-phase with each other. The interleaved topology reduces steady state input filter requirements by reducing current drawn from the filter capacitors. To avoid both switchers switching at the same instance, there is a built-in delay between the turn-on of the 3.3V switcher and 5V switcher, the amount of which depends on the input voltage (see Out-of-Phase Switching). Internal Bias Supply The PWM provides two modes of control over the entire load range. The SC1403 operates in forced continuous conduction mode as a fixed frequency peak current mode controller with falling edge modulation. Current sense is done differently than in conventional peak current mode control. Semtech’s proprietary Virtual Current SenseTM emulates the necessary inductor current information for proper functioning of the IC. In order to accommodate a wide range of output filters, a COMP pin is also available for compensating the error amplifier externally. A nominal gain of 18 is used in the error amplifier to further improve the system loop gain response and the output transient behavior. The VL linear regulator provides a 5V output used to power the gate drivers, 2.5V reference and internal control section of the SC1403. The regulator is capable of supplying up to 30mA (including mosfet gate charge current). The VL pin should be bypassed to GND with 4.7uF to supply the peak current requirements of the gate driver outputs. The regulator receives its input power from the V+ battery input. Efficiency is improved by providing a boot-strapping mode for the VL bias. When the 5V SMPS output voltage reaches 5V, internal circuitry turns on a pmos pass device between CSL5 and VL. The internal VL regulator is then disabled and VL bias is provided by the high efficiency 5V switcher. When the switcher is operating in continuous conduction mode, the high-side mosfet is turned on at the start of each switching cycle. It is turned off when the desired duty cycle is reached. Active shoot-through protection delays the turn-on of the lower mosfet until the phase node drops below 1V. The low-side mosfet remains on until the beginning of the next switching cycle. Again, active shoot-through protection ensures that the gate to the low-side mosfet has dropped low before the high-side mosfet turns on. 2004 Semtech Corp. The REF output is accurate to +/- 2% over temperature. It is capable of delivering 5mA max and should be bypassed with 1uF minimum capacitor. Loading the REF pin will reduce the REF voltage slightly as shown in the following table. 9 United States Patent No. 6,377,032 www.semtech.com SC1403 POWER MANAGEMENT Functional Information (Cont.) Loadi ng Resi stance (ohm) 511 Vref D evi ati on 8.3mV 2.67K 3.1mV 49.9K 0.5mV PRELIMINARY 255K 0.3mV 1Meg SH D N ON3 ON5 MODE DESCRIPTION Low X X Shutdown Minimum bias current High Low Low Standby VREF and VL regulator enable High High High Run Mode Both SMPS Running 0mV Current Sense (CSH, CSL) Output current of each supply is sensed as the voltage between the CSH and CSL pins. Overcurrent is detected when the current sense voltage exceeds +55/-50 mV typical. A positive overcurrent turns off the high-side driver, a negative overcurrent turns off the low-side driver; each on a cycle-by-cycle basis. Output current can be sensed by DCR (lossless) sensing, or optionally with a currentsense resistor; see Applications Information. Output Voltage Selection If FBx is grounded, internal resistors determine 3.3V and/or 5V output voltages. In adjustable mode, the internal resistors are disabled and the output is determined by external resistors, based on 2.5V regulated at the FB pin. The output voltage is determined according the following formula. Rdown should not exceed 10 Kohms. Oscillator When the SYNC pin is high the oscillator runs at 300kHz; when SYNC is low the frequency is 200kHz. The oscillator can be synchronized to the falling edge of a clock on the SYNC pin with a frequency between 240kHz and 350kHz. In general, 200kHz operation provides highest efficiency, while 300kHz is used to obtain smaller output ripple and/or smaller filter components. 3V or 5V Rup Fault Protection Vout In addition to cycle-by-cycle current limit, the SC1403 provides overtemperature, output overvoltage, and undervoltage protection. Overtemperature protection will shut the device down if die temperature exceeds 150°C, with 10°C hysteresis. Rdown Rup = 2 .5 ⋅ 1 + Rdown Power up Controls and Soft Start The user controls the SC1403 RESET# through the SEQ, ON3 and ON5 pins, as shown in the Startup Sequence Chart. At startup, RESET# is held low for 32K switching cycles, and then RESET# is determined by the output voltages and the SEQ pin. If either SMPS output is more than 10% above its nominal value, both SMPS are latched off and the low side mosfets are latched on. To prevent the output from ringing below ground in a fault condition, a 1A Schottky diode should be placed across each output. To prevent surge currents at startup, each SMPS has a counter and DAC to incrementally raise the current limit (CSH-CSL voltage). The current limit follows discrete steps of typically 25%, 40%, 60%, 80%, and 100%, each step lasting 128 clock cycles. To charge up the output capacitors, inductor current at startup must exceed load current. When the output voltage reaches it’s nominal value the SMPS will reduce duty cycle, but the excess LI2 energy of the inductor must flow into the load and output capacitors. If the output capacitor is relatively small, the peak output voltage can approach the overvoltage trip point. To prevent nuisance OVP at startup, the inductance and capacitance must meet the following criteria: Two different levels of undervoltage (UV) are detected. If the output falls 9% below its nominal value, the RESET# output is pulled low. If the output falls 25% below its nominal value, both SMPS are latched off. Both of the latched faults (OVP and UV) persist until SHDN or ON3 is toggled, or the V+ input is brought below 1V. Shutdown and Operating Modes Holding the SHDN pin low disables the SC1403, reducing the V+ input current to less than 10uA. When SHDN is high, the part enters standby mode where the VL regulator and VREF are enabled. Turning on either SMPS will put the SC1403 in run mode. 2004 Semtech Corp. FB3 or FB5 L MAX V O _ NOM 2 ≤ ⋅ 1 . 59 C MIN IL MAX _ OC 2 ILMAX_OC is the maximum inductor current set by the current-limit components, and VO_NOM is the nominal output voltage. 10 United States Patent No. 6,377,032 www.semtech.com SC1403 POWER MANAGEMENT Functional Information (Cont.) Startup Sequence Chart SEQ ON3 ON5 R ESET DESCRIPTION REF LOW LOW Follows 3.3V SMPS. Independant start control mode. Both SMPSs off. REF LOW HIGH Low. 5V SMPS ON, 3.3V SMPS OFF. REF HIGH LOW Follows 3.3V SMPS. 3.3V SMPS ON, 5V SMPS OFF. REF HIGH HIGH Follows 3.3V SMPS. Both SMPSs on. GND LOW X Low. Both SMPSs off. GND HIGH HIGH/LOW High after both outputs are in regulation. 5V starts when ON3 goes high. If ON5 = HIGH, 3V is on. If ON5 = LOW, 3V is off. VL LOW X Low. Both SMPSs off. VL HIGH HIGH/LOW High after both outputs are in regulation. 3V starts when ON3 goes high. If ON5 = HIGH, 5V is on. If ON5 = LOW, 5V is off. Applications Information voltage must be determined. Output ripple is often specified at 1% of the output voltage. For the 3.3V output, we selected a maximum ripple voltage of 33mVp-p. The maximum allowable ESR would then be: Reference Circuit Design The schematic for the reference circuit is shown on page 27. The reference circuit is configured as follows: Switching Regulator 1 Switching Regulator 2 Linear Regulator Input voltage ESR MAX = ∆V O / ∆ IO = 33mV / 1.5 A = 22m Ω Panasonic SP Polymer Aluminum capacitors are a good choice. For this design, use one 180uF, 4V device, with ESR of 15mΩ. Vout1 = 3.3V @ 6A Vout2 = 5.0V @ 6A Vout3 = 5.0V @ 50mA Vin = 7 to 21V The output capacitor must support the inductor RMS ripple current. To check the actual ripple versus the capacitor’s RMS rating: Designing the Output Filter IRMS_ actual = Before calculating the filter inductance and capacitance, an acceptable inductor ripple current is determined. Maximum allowable ripple depends on the transient requirements. Ripple current is usually set at 10% to 20% of the maximum load. However, increasing the ripple current allows for a smaller inductor and will also quicken the output transient response. In this example, we set the ripple current to be 25% of maximum load. ∆ I O = 25 % × 6 A = 1 . 5 A The inductance is found from ripple current, frequency, input voltage, and output voltage. Minimum required inductance is found at maximum Vin, where ripple current is the greatest. L min = Vo × ∆IO 1.5A = = 0.43A 12 12 This is much less than the capacitor’s ripple rating of 3.3A. Choosing Current Sense Components Since the SC1403 implements Virtual Current SenseTM, current sensing is not required for the control loop. But it is required for cycle-by-cycle current limit and for startup. Cycle-by-cycle current limit is reached when the voltage of CSH-CSL exceeds 55mV nominal. Depending on the system requirement, this current limit can vary, but it is typically 10% to 30% higher than the maximum load. This design uses the DC resistance of the inductor as a current sense element, which eliminates the cost and space required for a separate current sense resistor. Below is a typical DCR application circuit. The inductor is shown along with it’s wiring resistance RL. In place of the current sense resistor are C, R2, and R1, which are connected across the inductor terminals. (1 − Vo / Vin ) = 6 . 18 uH F × ∆ Io The next standard value is 6.8uH. For the reference design, the Coiltronics DR127-6R8 is used. To specify the output capacitance, the allowable output ripple 2004 Semtech Corp. 11 United States Patent No. 6,377,032 www.semtech.com SC1403 POWER MANAGEMENT Applications Information (Cont.) CSH PRELIMINARY 1.5Kohm. The bias current from the CSH input flows through these resistors and creates an error term. CSL The value for R1 should not be too small due to power considerations. During a switching cycle, the voltage across R1 is either (Vin - Vo) or (-Vo). This creates a power loss in R1: the power loss can be determined by: (Phase node) C VLX R1 R2 L (Output) RL VO The equation for the current sense signal, CSH - CSL, is given by: V(CSH − CSL) = (VLX − Vo) ⋅ P R1 = R2 (EQ1) R2 + R1+ sC ⋅ R2 ⋅ R1 where (VLX - Vo) is the voltage across the inductor terminals. The values for C, R2, and R1 can be found by comparing the above circuit with resistive sensing, which is shown below. Vo ⋅ (Vin - Vo ) 3 . 3 ⋅ (21 − 3 . 3 ) = = 45 mW R1 1 . 3k Ω Choosing the Main Switching mosfet The IRF7143 is used in the reference design. Before choosing the main (high-side) mosfet, we need to check three parameters: voltage, power, and current rating. The maximum drain to source voltage of the mosfet is mainly determined by the switcher topology. Since this is a buck topology, VDS _ MAX = VIN _ MAX = 21 V The IRF7413 is a 30V device, which allows for 70% derating at 21V operation. (Phase node) CSH VLX sL RL CSL Rsns (Output) Vo The mosfet power dissipation has three components: conduction losses, switching losses, and gate drive losses. The conduction loss is determined using the RMS mosfet current; the equation is shown below. The mosfet current is a trapezoid waveform with values equal to: With resistive sensing, the current sense signal CSH-CSL can be written in the complex s-domain as: V (CSH − CSL ) = ( VLX − Vo) ⋅ Rsns Rsns + RL + sL (EQ 2) where (VLX - Vo) is the voltage across the inductor terminals. Note the similarity between EQ 1 and EQ 2. By choosing proper values for C, R1, and R2, the current-sense voltage (CSH-CSL) will track the inductor current. The following equations determine C, R1, and R2: R1 = L ⋅ ILpk C ⋅ 55mV 55mV R2 = R1 ⋅ (ILpk ⋅ RL − 55mV I MIN = I LOAD − ∆IL = ∆ IL 2 I MAX = I LOAD + Vo ⋅ (1 − D) fs ⋅ L I RMS = D ⋅ (I MIN D = 2 The recommended value for C is 1.0uF. RL inductor resistance is specified at 11.6 mohm typical. 55mV is the current sense threshold. For the reference design, the values are set to C = 1uF and R1 = R2 = 1.3K. This sets the current limit to approximately 10A. Vo Vin + I MIN ⋅ I MAX + I MAX 2 ) As input voltage decreases, the duty cycle increases and the ripple current decrease, and overall the RMS mosfet current will increase. The conduction losses are then given by the formula below, where Rds(on) is 18m-ohm for the IRF7413 at room temperature. Note that Rds(on) increases with temperature. PCONDUCTION = Rds( on) ⋅ IRMS ) ∆ IL 2 2 The mosfet switching loss is estimated according to: 2 PSWITCHING = CRSS ⋅ VIN ⋅ fS ⋅ IOUT IG Crss is the reverse transfer capacitance of the mosfet, which is 240pF for IRF7413. Ig is the gate driver current, which is 1A for SC1403. Two guidelines must be used when selecting C, R1, and R2: The mosfet gate drive loss is estimated from: The values of R2 and R1 should not exceed approximately 2004 Semtech Corp. 12 United States Patent No. 6,377,032 www.semtech.com SC1403 POWER MANAGEMENT Applications Information Information (Cont.) Applications 1 ⋅ CG ⋅ V 2 ⋅ fS 2 Cg is the effective gate capacitance, equal to the Total Gate Charge divided by VGS from the vendor datasheet, and is 7.9nF for the IRF7413. V in the above formula is the final gate-source voltage on the mosfet, 5V for the SC1403. PGATE = The total mosfet losses is the sum of the three loss components. P TOTAL _ DISS = P CONDUCTION + P SWITCHING + P GATE The mosfet dissipation under conditions of 15V input, 6A load, and ambient temperature of 25C, can be determined as: DNOM = 0.22 IMIN = 5.37A ∆IL = 1.26A IMAX = 6.63A IRMS = 4.88A Rds(on) (100C) = 18 mohm PCONDUCTION = 429mW . PSWITCHING = 97mW PGATE = 30mW PTOTAL_DISS = 429 + 97 + 30 = 556 mW The junction temperature rise resulting from the power dissipation is calculated as: ∆ TJ = P T ⋅ θ JA PT is the total device dissipation, and θJA is the package thermal resistance, which is 50°C/W for the IRf7413. The junction temperature rise is then: ∆TJ = 0.556W . 50°C/W = 27.8° This is a modest temperature rise, so no special heat sinking is required when laying out the mosfet. 2004 Semtech Corp. 13 United States Patent No. 6,377,032 www.semtech.com SC1403 POWER MANAGEMENT Applications Information (Cont.) PRELIMINARY 200 Designing the Loop 150 There are two aspects concerning the loop design. One is the power train design and the other is the external compensation design. A good loop design is a combination of the two. In the SC1403, the control-to-output/power train response is dominated by the load impedance, the effective current sense resistor, output capacitance, and the ESR of the output caps. The low frequency gain is dominated by the output load impedance and the effective current sense resistor. Inherent to Virtual Current SenseTM, there is one additional low frequency pole sitting between 100Hz and 1kHz and a zero between 15kHz and 25kHz. To compensate for the SC1403 is easy since the output of error amplifier COMP pin is available for external compensation. A traditional pole-zeropole compensation is not necessary in the design using SC1403. To ensure high phase margin at crossover frequency while minimizing the component count, a simple high frequency pole is usually sufficient. In the reference design below, single-pole compensation method is demonstrated. And the loop measurement results are compared to those obtained from the simulation model. Transient response is also done to validate the model. Also, to help speed up the design process, a list of recommended output caps vs compensation caps value is given in table I. 100 Phase (deg) 50 0 -50 -100 -150 -200 100 1000 10000 100000 f (Hz) Measured Control-to-Output gain & phase response (up to 100kHz) is plotted below. 50 40 30 20 Gain (dB) 10 Single-Pole Compensation Method 0 -10 -20 Given parameters: Vin = 19V, Vout = 3.3V @ 2.2A, Output impedance, Ro = 3.3V/2.2A = 1.5 Ω , Panasonic SP cap, Co = 180uF, Resr = 15 mΩ , Output inductor, Lo = 4.7uH Switching frequency, Fs = 300kHz -30 -40 -50 100 1000 10000 100000 f (Hz) Simulated Control-to-Output gain & phase response (up to 100kHz) is plotted below. 200 150 50 100 40 50 Phase (deg) 30 20 Gain (dB) 10 0 -50 0 -100 -10 -150 -20 -200 100 -30 -40 -50 100 10000 100000 f (Hz) 1000 10000 100000 Single-pole compensation of the error amplifier is achieved by connecting a 100pF capacitor from the COMP pin of the SC1403 to ground. The simulated feedback gain & phase response (up to 100kHz) is plotted below. f (Hz) 2004 Semtech Corp. 1000 14 United States Patent No. 6,377,032 www.semtech.com SC1403 POWER MANAGEMENT Applications Information (Cont.) 25 20 0 20 -20 15 -40 -60 Phase (deg) Gain (dB) 10 5 0 -80 -100 -120 -5 -140 -10 -15 100 -160 -180 1000 10000 100 100000 1000 10000 100000 Frequency (Hz) f (Hz) Simulated overall gain & phase responses (up to 100kHz) is ted below. plot- 0 -10 80 -30 60 -40 40 -50 20 -60 Gain (dB) Phase(deg) -20 -70 0 -80 -20 -90 -40 -100 100 1000 10000 -60 100000 f (Hz) -80 100 1000 10000 100000 f (Hz) Measured feedback gain & phase responses (up to 100kHz) is plotted below. 180 25 160 20 140 15 120 100 Phase(deg) Gain (dB) 10 5 0 80 60 40 -5 20 -10 0 -20 100 -15 100 1000 10000 100000 2004 Semtech Corp. 1000 10000 100000 f (Hz) f (Hz) 15 United States Patent No. 6,377,032 www.semtech.com SC1403 POWER MANAGEMENT Applications Information (Cont.) PRELIMINARY Table I. Recommended compensation cap for different output capacitance. Measured overall gain & phase response of the single-pole compensation using SC1403 is plotted below. 60 Output C ap Recommended C ompensati on C ap Value < = 180µF 100pF > 180µF & <1000µF 200pF >1000µF 330pF 50 40 Gain (dB) 30 20 10 0 -10 -20 100 1000 10000 100000 10000 100000 f (Hz) 180 160 140 120 Phase (deg) 100 80 60 40 20 0 -20 100 1000 f (Hz) 2004 Semtech Corp. 16 United States Patent No. 6,377,032 www.semtech.com SC1403 POWER MANAGEMENT Typical Characteristics Transient response using single-pole (capacitive) compensation is shown on the following pages. The load steps are from 0A to 3A and 3A to 6A. The applied di/dt is 2.5A/usec. Vin = 10V, ILoad= 0A to 3A 3.3V PSAVE disabled Vin = 10V, ILoad= 0A to 3A 3.3V Forced-Continuous Vin = 10V, ILoad= 3A to 6A 3.3V PSAVE enabled 3.3V PSAVE enabled 2004 Semtech Corp. 17 Vin = 19V, ILoad= 0A to 3A United States Patent No. 6,377,032 www.semtech.com SC1403 POWER MANAGEMENT Typical Characteristics (Cont.) 3.3V PSAVE disabled Vin = 19V, ILoad= 0A to 3A 3.3V Forced ContinuousVin = 19V, ILoad= 3A to 6A 2004 Semtech Corp. PRELIMINARY 18 5.0V PSAVE enabled Vin = 10V, ILoad= 0A to 3A 5.0V PSAVE disabled Vin = 10V, ILoad= 0A to 3A United States Patent No. 6,377,032 www.semtech.com SC1403 POWER MANAGEMENT Typical Characteristics (Cont.) 5.0V Forced Continuous Vin = 10V, ILoad= 3A to 6A 5.0V PSAVE disabled Vin = 19V, ILoad= 0A to 3A 5.0V PSAVE enabled 5.0V Forced Continuous Vin = 19V, ILoad= 3A to 6A 2004 Semtech Corp. Vin = 19V, ILoad= 0A to 3A 19 United States Patent No. 6,377,032 www.semtech.com SC1403 POWER MANAGEMENT Applications Information PRELIMINARY Input Capacitor Selection and Out-of-phase Switching As the input voltage is reduced, the duty cycle of both converters increases. For all input voltages less than 8.3V it is impossible to prevent overlap when producing 3.3V and 5V outputs, regardless of the phase relationship between the two converters. Overlap can be seen in the following figure. The SC1403 uses out-of-phase switching between the two converters to reduce input ripple current, allowing smaller, cheaper input capacitors compared to in-phase switching. period The figure below shows in-phase switching. I3in is the input current drawn by the 3.3V converter, I5in is the input current drawn by the 5V converter. The two converters start each switching cycle simultaneously, causing in a significant amount of overlap. This overlap increases the peak current. The total input current to the converter is the third trace, Iin, which shows how the two currents add together. The fourth trace shows the current flowing in and out of the input capacitors. D3 D5 phase lead D3 I5in D5 Iin average I3in 0 0 I5in Icap Iin average 0 From an input filter standpoint it is desirable to minimize the overlap; but it is also desirable to keep the turn-on and turn-off transitions of the two converters separated in time, to prevent the two converters from affecting each other due to switching noise. The SC1403 keeps the turn-on and turn-off transitions separated in time by changing the phase relationship between the converter depending on the input voltage. The following table shows the phase relationship between 3V and 5V turn-on, based on input voltage. 0 Icap The next figure shows out-of-phase switching. The 3.3V and 5V converters are spaced apart, thus there is no overlap. This gives two benefits. The peak current is reduced, and the effective switch frequency is raised; both of which make filtering easier. The third trace shows the total input current, and the fourth trace shows the current flowing in and out of the input capacitors. The RMS value of the capacitor current is significantly lower than the in-phase case, which allows for smaller capacitors. D3 I5in average 0 Icap 2004 Semtech Corp. P h ase l ead f r om 3V t o 5V r i si n g ed g e Vin > 9.6 V 41% of switching period. N o switching overlap between 3V and 5V. 9.6V > Vin > 6.7V 59% of switching period. Small overlap to prevent simultaneous 3V/5V switching. 6.7 > Vin 64% of switching period. Small overlap to prevent simultaneous 3V/5V switching. I3in D5 Iin In p u t v ol t ag e 0 20 United States Patent No. 6,377,032 www.semtech.com SC1403 POWER MANAGEMENT Applications Information (Cont.) and the Schottky diode. The current rating of the Schottky diode can be determined by the following equation: Input ripple current calculations: The following equations provide quick approximations for input ripple current: IF _ AVG = ILOAD ⋅ D3 = 3.3V / VIN = 3V duty cycle 100n = 0.2A TS where 100nsec is the estimated time between the mosfet turning off and the Schottky diode taking over and Ts = 3.33uS. Therefore a Schottky diode with a forward current of 0.5A is sufficient for this design. D5 = 5 V / VIN = 5V duty cycle I3 = 3V DC load current I5 = 5V DC load current External Feedback Design DOVL = overlapping duty cycle of the 3V and 5V pulses (varies according to input voltage) In order to optimize the ripple voltage during Power Save mode, it is strongly recommended to use external voltage dividers (R10 and R9 for 5V power train; R8 and R11 for 3.3V power train) to achieve the required output voltages. In addition a 56pF (C22 for 5V and C21 for 3.3V) cap is recommended connecting from the output to both feedback pins (pin # 3 and #12). The signal-tonoise ratio is therefore increased due to the added zeros. DOVL = 0 for 9.6V ≤ VIN DOVL = (D5 - 0.41) for 6.7V ≤ VIN < 9.6V DOVL = (D5 - 0.36) for VIN < 6.7 IIN = Average DC input current IIN = I3 ⋅ D3 + I5 ⋅ D5 ISW _ RMS = RMS current drawn from VIN ISW _ RMS 2 = D3 ⋅ I32 + D5 ⋅ I52 + 2 ⋅ DOVL ⋅ I3 ⋅ I5 I RMS_CAP = I SW_RMS 2 + I IN_AVE 2 The worst-case ripple current varies by application. For the case of I3 = I5 = 6A, the worst-case ripple occurs at Vin = 7.5V, at which point the rms capacitor ripple current is 4.2A. To handle this the reference design uses 4 paralleled ceramic capacitors, (Murata GRM32NF51E106Z, 10 uF 25V, size 1210). Each capacitor is rated at 2.2A. Choosing Synchronous mosfet and Schottky Diode Since this is a buck topology, the voltage and current ratings of the synchronous mosfet are the same as the main switching mosfet. It makes sense cost- and volume-wise to use the same mosfet for the main switch as for the synchronous mosfet. Therefore, IRF7413 is used again in the design for synchronous mosfet. To improve overall efficiency, an external Schottky diode is used in parallel to the synchronous mosfet. The freewheeling current is going into the Schottky diode instead of the body diode of the synchronous mosfet, which usually has very high forward drop and slow transient behavior. It is really important when laying out the board to place both the synchronous mosfet and Schottky diode close to each other to reduce the current ramp-up and ramp-down time due to parasitic inductance between the channel of the mosfet 2004 Semtech Corp. 21 United States Patent No. 6,377,032 www.semtech.com SC1403 POWER MANAGEMENT Applications Information (Cont.) PRELIMINARY Overvoltage Test Operation Below 6V input Measuring the overvoltage trip point can be problematic. Any buck converter with synchronous mosfets can act as a boost converter, sending energy from output to input. In some cases the energy sent to the input is enough to drive the input voltage beyond normal levels, causing input overvoltage. To prevent this enable the SC1403 PSAVE# feature, which effectively disables the low side mosfet drive so that little energy, if any, is transferred back to the input. The SC1403 will operate below 6V input voltage with careful design, but there are limitations. The first limitation is the maximum available duty cycle from the SC1403, which limits the obtainable output voltage. The design should minimize all circuit losses through the system in order to deliver maximum power to the output. A second limitation with operation below 6V is transient response. When load current increases rapidly, the output voltage drops slightly; the feedback loop normally increases duty cycle briefly to bring the output voltage back up. If duty cycle is already near the maximum limit, the duty cycle cannot increase enough to meet the demand, and the output voltage sags more than normal. This problem can not be solved by changing the feedback compensation, it is a function of the input voltage, duty cycle, and inductor and capacitor values. Semtech recommends the following circuit for measuring the overvoltage trip point. D1 prevents the output voltage from damaging lab supply 1. R1 limits the amount of energy that can be cycled from the output to the input. R2 absorbs the energy that might flow from output to input, and D2 protects lab supply from possible damage. The ON5 signal is monitored to indicate when overvoltage occurs. Initial conditions: Both lab supplies set to zero volts No load connected to 3V or 5V PSAVE# enabled (PSAVE# tied to GND) ON5, ON3 both enabled DVMs monitoring ON5 and the output under test Oscilloscope probe connected to Phase Node of the output under test (not strictly required) If an application requires 5V output from an input voltage below 6V, the following guidelines should be used: 1 - Set the switching frequency to 200 kHz (Tie SYNC to GND). This increases the maximum duty cycle compared to 300 kHz operation. 2 - Minimize the resistance in the power train. Select mosfets, inductor, and current sense resistor to provide the lowest resistance as is practical. Set lab supply 2 to provide 10V at the SC1403 input. The phase node of the output being tested should show some switching activity. The ON5 pin should be above 4V. 3 - Minimize the pcb resistance for all traces carrying high current. This includes traces to the input capacitors, mosfets and diodes, inductor, current sense resistor, and output capacitor. Slowly increase lab supply 1 until the output under test rises slightly above it’s normal DC level. As the input lab supply 1 increases, switching activity at the phase node will cease. The ON5 pin should remain above 4V. 4 - Minimize the resistance between the SC1403 circuit and the power source (battery, battery charger, AC adaptor). Increase lab supply 1 in very small increments, monitoring both ON5 and the output under test. The overvoltage trip point is the highest voltage seen at the output before ON5 pulls low (approximately 0.3V). Do not record the voltage seen at the output after ON5 has pulled low; when ON5 pulls low, the current flowing in D1 changes, corrupting the voltage seen at the output. 5 - Use low ESR capacitors on the input to prevent the input voltage dropping during on-time. 6 - If large load transients are expected, high capacitance and low ESR capacitors should be used on both the input and output. D1 e.g. 1N4004 Lab Supply 2 R2 470 1/2W to DVM Output under test Vin SC1403 SC1403 Evaluation Board D2 D1 e.g. 1N4004 VL R1 75 1/2W 1K ON5 to DVM 2004 Semtech Corp. 22 Lab Supply 1 United States Patent No. 6,377,032 www.semtech.com SC1403 POWER MANAGEMENT Typical Characteristics 5V Line Regulation 5.03 Vout (V) 5.02 5V@0A 5V@3A 5V@6A 5.01 5.00 4.99 10 12 14 16 18 20 22 24 Vin (V) 3.3V Line Regulation 3.34 3.33 Vout (V) 3.3V@0A 3.3V@3A 3.3V@6A 3.32 3.31 10 12 14 16 18 20 22 24 Vin (V) 2004 Semtech Corp. 23 United States Patent No. 6,377,032 www.semtech.com SC1403 POWER MANAGEMENT Typical Characteristics (Cont.) PRELIMINARY 5V Load Regulation @Vin =19V 5.05 5.04 5.03 Vout (V) 5.02 5V @25degC 5.01 5V @125degC 5.00 5V@-45degC 4.99 4.98 4.97 4.96 0 1 2 3 4 5 6 Iout (A) 5V Load Regulation @ Vin =10V 5.03 5.02 5.01 Vout (V) 5.00 5.0V@25degC 4.99 5.0V@125degC 5.0V@-45degC 4.98 4.97 4.96 4.95 0 1 2 3 4 5 6 Iout (A) 2004 Semtech Corp. 24 United States Patent No. 6,377,032 www.semtech.com SC1403 POWER MANAGEMENT Typical Characteristics (Cont.) 3.3V Load Regulation @ Vin = 19V 3.35 3.34 Vout (V) 3.33 3.3V@25degC 3.32 3.3V@125degC 3.3V@-45degC 3.31 3.30 3.29 0 1 2 3 4 5 6 Iout (A) 3.3V Load Regulation @ Vin =10V 3.34 3.33 Vout (V) 3.32 3.3V@25degC 3.31 3.3V@125degC 3.3V@-45degC 3.30 3.29 3.28 0 1 2 3 4 5 6 Iout (A) 2004 Semtech Corp. 25 United States Patent No. 6,377,032 www.semtech.com SC1403 POWER MANAGEMENT Typical Characteristics (Cont.) PRELIMINARY 5V Efficiency 97% 95% Efficiency (%) 93% 5V@19Vin 91% 5V@10Vin 89% 87% 85% 0.01 0.1 1 10 Iout (A) 3.3V Efficiency 95% Efficiency (%) 90% 85% 3.3V@19Vin 3.3V@10Vin 80% 75% 70% 0.01 0.1 1 10 Iout (A) 2004 Semtech Corp. 26 United States Patent No. 6,377,032 www.semtech.com R8 1.58K 1uF C39 3_3V D2 COMP3 C7 100pF 4.99K R11 56pF C21 NO_POP C18 180uF/4V C17 C13 zero_ohm CMP3RC C29 1uF C14 zero_ohm CMP5RC NO_POP C35 0.1uF D D 100pF C8 COMP5 100k R13 NO_POP R19 1.3K D3 140T3 R3 VL 6.8uH L1 R2 R18 1.3K R23 NO_POP 0.005 R6 IRF7413 IRF7413 Q2 5 6 7 8 1 2 3 4 4 10 R1 C37 0.01uF C36 NO_POP Q3 5 6 7 8 1 2 3 C3 COMP3 0.01uF C27 T-ON5 1k R16 SHDN# COMP5 0.22uF C15 4.7uF/35V C9 RUN/ON3 10uF/25V 0.22uF DH3 C2 V+ R4 0 0.1uF C10 ON3 U1 VIN CSH3 1 PHASE3 C1 CSL3 2 27 FB3 3 28 4 26 BST3 COMP3 SC1403 C11 S1 PSV# 0 R5 BAT54A D1 4.7uF/16V 19 10uF/25V SYNC 6 25 5 23 SHDN TIME/ON5 7 24 DL3 COMP5 22 V+ 21 VL GND 8 20 PGND REF 9 4 3 2 1 5 6 7 8 DL5 PSAVE VL 16 0.1uF C12 2M 2M 2M R14 R15 R17 VL 2M R12 REF RESET# FB5 12 18 BST5 RESET 10 27 11 17 PHASE5 DH5 CSL5 13 15 SEQ CSH5 14 1uF/16V C25 4 0.22uF C16 4 8 7 6 5 IRF7413 D Q1 D5 REF RESET# PSV# 0.1uF C26 R20 1.3K C34 NO_POP 140T3 D Q4 Date: Size B Title C20 0.1uF C33 NO_POP C19 150uF/6.3V 0.005 R7 4.9 56pF 4.99K R10 FB5 R9 C22 30BQ015 D4 Monday, March 29, 2004 Document Number Sheet 1 SC1403 Evaluation Bo C28 1uF R21 1.3K R22 NO_POP 6.8uH L2 10uF/25V 10uF/25V 0.22uF C6 C5 C4 IRF7413 3 2 1 8 7 6 5 2004 Semtech Corp. 3 2 1 VIN SC1403 POWER MANAGEMENT Evaluation Board Schematic VIN United States Patent No. 6,377,032 www.semtech.com 30BQ015 SC1403 POWER MANAGEMENT Evaluation Board Bill of Materials Item Quanity 1 4 C1,C2,C5,C6 2 4 C3,C4,C15,C16 0.22uF 0806 3 2 C7,C8 100pF 0603 4 2 C9, C11 4.7uF 5 1 C 25, C 28, C 29 1uF ceramic 6 1 C 17 EEF-UE0G181R 180uF, 4V Panasonic D _ C a se _ 7 3 4 3 7 1 C 19 EEF-UE0J151R 150uF, 6.3V Panasonic D _ C a se _ 7 3 4 3 8 1 D1 BAT54A 30V, 200ma, dual anode Zetex SOT-23 9 2 D 3, D 5 MBRS140T3 40V, 1A Schottky Motorola SMB 10 2 D 2, D 4 30BQ015 15V, 3A Schottky International Rectifier 11 2 L1, L2 DR127-6R8 SMT Inductor 6.8uH Coiltronics 12 4 Q1, Q2, Q3, Q4 IRF7413 30V N-channel MOSFET International Rectifier 13 1 R1 10 ohm 603 14 2 R4, R5 0 ohm 603 15 2 R6, R7 (resistive sensing only) 16 2 R16 18 1 U1 2004 Semtech Corp. Designation PRELIMINARY Part Number Description GRM230Y5V106Z025 WSL2512R005FB43 10uF, 25V 5mohm Manufacturer Murata Vishay Dale 1Kohm SC463ITS Mobile PWM Controller with VCS 28 C ase 1210 SO8 2512 603 Semtech TSSOP28 United States Patent No. 6,377,032 www.semtech.com SC1403 POWER MANAGEMENT Evaluation Board Layout Top Assembly Bottom Assembly 2004 Semtech Corp. 29 United States Patent No. 6,377,032 www.semtech.com SC1403 POWER MANAGEMENT Layout Guidelines PRELIMINARY As with any high frequency switching regulator design, a good PCB layout is very essential in order to achieve optimum noise, efficiency, and stability performance of the converter. Before starting PCB layout, a careful layout strategy is strongly recommended. See the PCB layout in the SC1403 Evaluation Kit manual for example. In most applications, use FR4 with 4 or more layers and at least 2 ounce copper (for output current up to 6A). Use at least one inner layer for ground connection. It is always a good practice to tie signal-ground and power-ground at one single point so that the signal-ground is not easily contaminated. High current paths should have low inductance and resistance by making trace widths as wide as possible and lengths as short as possible. Properly decouple lines that pull large amounts of current in short periods of time. The following layout strategy should be used in order to fully utilize the potential of SC1403. A. Power train arrangement. Place power train components first. The following figure shows the recommended power train arrangement. Q1 is the main switching FET, Q2 is the synchronous Rectifier FET, D1 is the Schottky diode and L1 is the output inductor. The phase node, where the source of the upper switching FET and the drain of the synchronous rectifier meets, switches at very high rate of speed, and is generally the largest source of common-mode noise in the converter circuit. It should be kept to a minimum size consistent with its connectivity and current carrying requirements. Also place the Schottky diode as close to the phase node as possible to minimize the trace inductance, therefore reducing the efficiency loss due to the current ramp-up and down time. This becomes extremely important when the converter needs to handle high di/ dt requirement. Vias between power components should be used only when necessary: if vias are required, use multiple vias to reduce the inter-component impedance, and keep the traces between vias and power components as short and wide as possible. Q1 D1 L1 Q2 B. Current Sense. With DCR sensing: The connections from the RC network to the inductor should be Kelvin connections directly at the inductor solder pads. Place the capacitor close to the CSH/CSL pins on the SC1403, and connect to the capacitor using short direct traces. 2004 Semtech Corp. L C VOUT OUT CSL R1 R2 C S C 1403 CSH With resistive sensing: minimize the length of current sense signal traces. Keep them less than 15mm. Use Kelvin connections as shown below; keep the traces parallel to each other and as close together as possible. L CSH S C 1403 CSL R sn s C. Gate Drive. The SC1403 has built-in gate drivers capable of sinking/sourcing 1A pk-pk. Upper gate drive signals are noisier than the lower ones, so place them away from sensitive analog circuits. Make sure the lower gate traces are as close as possible to the SC1403 pins, and make both upper and lower gate traces as wide as possible. D. PWM placement (pins) and signal ground island. Connect all analog grounds to a separate solid copper island plane, which connects to the SC1403’s GND pin. This includes REF, FB3, FB5, COMP3, COMP5, SYNC, ON3, ON5, PSV# and RESET#. E. Ground plane arrangement. There are several ways to tie the different grounds together (analog ground, input power ground, and output power ground). With a buck topology, the output is quiet compared to the input side. The output is the best place to tie the analog ground to the power ground, often through a 0Ω resistor. The input power ground and the output power ground can be tied together using internal planes. 30 United States Patent No. 6,377,032 www.semtech.com SC1403 POWER MANAGEMENT Outline Drawing - TSSOP-28 Land Pattern - TSSOP-28 Contact Information Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804 2004 Semtech Corp. 31 United States Patent No. 6,377,032 www.semtech.com