SC2447
Dual-Phase, Single or Dual Output
Synchronous Step-Down Controller
POWER MANAGEMENT
Description
Features
2-Phase Step-down Controller optimized for Philips
or Renesas DrMOSTM
Out of Phase Operation for Low Input Current Ripple
Outputs Source and Sink Current
Fixed Frequency Peak Current-Mode Control
Lossless Inductor DCR Current Sensing
Optional Resistor Current-Sensing for Precise Current-Limit
Dual 30A Outputs or 2-Phase 60A Single Output
Operation
Wide Input Voltage Range: 4.65V to 15V
Individual Closed-Loop Soft-Start, Overload Shutdown Timer and Enable
Output Voltage as Low as 0.5V
Starts into Pre-Bias Output
Tri-State PWM Output during Shutdown
Programmable Frequency Up to 1MHz Per Phase
External Synchronization
TSSOP-28 Lead-free Package. Fully WEEE and RoHS
Compliant
The SC2447 is a versatile high-frequency dual phase PWM
step-down controller optimized for Philips and Renesas
DrMOSTM. Both phases are capable of sourcing or sinking load currents, making the SC2447 suitable for networking system power and DDR applications.
The SC2447 employs fixed frequency, continuous-conduction peak current-mode control for easy compensation and fast transient response.
The SC2447 can be used to generate two independent
outputs (up to 30A per output) or a single 60A output
with shared phase current. The PWM signals are 180°
out of phase to minimize input/output ripple.
Either inductor DC resistance or precision sense resistor
can be used for current-mode control. Inductor DC resistance sensing has the advantage of being lossless.
Each phase has individual closed-loop soft-start and overload shutdown timer. The SC2447 powers up neatly with
pre-biased output. It has tri-state shutdown and hiccup
overload protection. In two-phase single-output configuration, the master timer controls the soft-start and overload shutdown functions. The SC2447 is in a lead-free,
WEEE and RoHS compliant, TSSOP-28 package.
Applications
Telecommunication Power Supplies
DDR Memory Power Supplies
Graphic Power Supplies
Servers and Base Stations
Typical Application Circuit
VIN
12V
CB1
100nF
L1
1µH/1.8mΩ
VOUT1
2.5V/20A
VDDO
VDDC
CBP
VDDG
CBN
RFB1A
10KΩ
RS1B
22.1KΩ
RS1A
22.1KΩ
C4
1µF
C3
1µF
AVCC
C6
1µF
VDDC
VDDO
VDDG
CBP
CBN
CVCC
4.7µF
REG5V
VO
CO1
100µF
x3
C5
1µF
R2
10Ω
RVCC
10Ω
R1
10Ω
CIN1
22µF
x4
REG5V
GDH1
GDH2
VI
GDL1
GDL2
DISABLE
VSSC
VSSC
SC2447
PIP212-12M
CCS1
100nF
CS2+
CS1-
CS2-
IN1-
IN2-
VSSO
COMP2
COMP1
CCMP1
10pF
RA1
24.9KΩ
CA1
3.3nF
ROSC
REFOUT
CREF
0.1uF
REF
SS1/EN1
SYNC
SS2/EN2
Revision: December 15, 2006
ROSC , 51.1KΩ
1
RA2
16.9KΩ
CA2
3.3nF
CSS2
0.1µF
Figure 1
VOUT2
1.2V/25A
CO2
100µF
x3
RFB2A
10KΩ
RS2C , 20KΩ
AGND
REFIN
RS2A
22.1KΩ
CCS2
68nF
RS1C , 11KΩ
RFB1B
2.49KΩ
L2
0.4µH/1mΩ
RS2B
200KΩ
PIP212-12M
CS1+
CB2
100nF
VO
VI
DISABLE
VSSO
CIN2
22µF
x4
RFB2B
7.15KΩ
CCMP2
10pF
CSS1
0.1µF
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SC2447
POWER MANAGEMENT
Pin Configurations
Ordering Information
Device
TOP VIEW
CS1+
1
28
SS1/EN1
CS1-
2
27
NC
ROSC
3
26
NC
IN1-
4
25
GDH1
COMP1
5
24
GDL1
SYNC
6
23
NC
AGND
7
22
NC
REF
8
21
GDL2
REFOUT
9
20
GDH2
REFIN
10
19
NC
COMP2
11
18
NC
IN2-
12
17
NC
CS2-
13
16
AVCC
CS2+
14
15
SS2/EN2
SC2447TSTRT(1)(2)
S C 2447E V B
Top Mark
P ackag e
S C 2447
TSSOP-28
Evaluation Board
Notes:
(1) Only available in tape and reel packaging. A reel contains 2500 devices
for TSSOP package.
(2) Lead free product. This product is fully WEEE and RoHS compliant.
(28 Pin TSSOP)
θJA= 84°C/W; θJC= 13°C/W.
Figure 2
Absolute Maximum Rating
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified
in the Electrical Characteristics section is not implied. Exposure to Absolute Maximum rated conditions for extended periods of time may affect device
reliability.
Parameter
Symbol
Maximum Ratings
Units
AVCC
-0.3 to 16
V
VGDH1, VGDH2,VGDL1, VGDL2
-0.3 to 6
V
VIN1-,VIN2-
-0.3 to AVCC+0.3
V
VREF ,VREFOUT
-0.3 to 6
V
VREFIN
-0.3 to AVCC+0.3
V
VCOMP1,VCOMP2
-0.3 to AVCC+0.3
V
VCS1+,VCS1-,VCS2+,VCS2-
-0.3 to AVCC+0.3
V
VSYNC
-0.3 to AVCC+0.3
V
VSS1,VSS2
-0.3 to 6
V
Storage Temperature Range
TSTG
-60 to 150
°C
Lead Temperature (Soldering) 10 sec
TLEAD
260
°C
TJ
150
°C
ESD
2
kV
Supply Voltage
Gate Outputs GDH1, GDH2, GDL1, GDL2 voltages
IN1-, IN2- Voltages
REFOUT Voltages
REF, REFIN Voltage
COMP1, COMP2 Voltages
CS1+, CS1-, CS2+ and CS2- Voltages
SYNC Voltage
SS1/EN1 AND SS2/EN2 Voltages
Junction Temperature
ESD Rating (Human Body Model)
© 2006 Semtech Corp.
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SC2447
POWER MANAGEMENT
Recommended Operating Conditions
The performance is not guarantied if exceeding the specifications below.
Parameter
AVCC Operating Voltage
Symbol
Conditions
Min
Typ
Max
Units
AVCC
4.65
15
V
Ambient temperature Range
TA
-40
85
°C
Junction Temperature Range
TJ
-40
125
°C
Typ
Max
Units
4.50
4.65
V
Electrical Characteristics
Unless specified: AVCC = 12V, SYNC = 0, ROSC = 51.1kΩ, -40°C < TA = TJ < 125°C
Parameter
Symbol
Conditions
AVCC Start Threshold
AVCCTH
AVCC Increasing
AVCC Start Hysteresis
AVCCHYST
Min
Undervoltage Lockout
AVCC Operating Current
ICC
AVCC Quiescent Current in UVLO
0.2
AVCC= 12V
8
AVCC = AVCCTH - 0.2V
2.5
V
15
mA
mA
Channel 1 Error Amplifier
Input Common-Mode Voltage Range(1)
0
3
V
Inverting Input Voltage Range(1)
0
AVCC
V
±1
±3
mV
Input Offset Voltage
0 ~ 70° C
Non-Inverting Input Bias Current
IREF
-100
-250
nA
Inverting Input Bias Current
IIN1-
-100
-250
nA
Amplifier Transconductance
GM1
170
µΩ −1
Amplifier Open-Loop Gain
aOL1
65
dB
5
MHz
V C S 1+ = V C S 1- = 0
VSS1 Increasing
1.7
V
VIN1- = 1V, VCOMP1 = 2.5V
11
µA
VIN1- = 0, VCOMP1 = 2.5V
8.5
µA
Amplifier Unity Gain Bandwidth(1)
Minimum COMP1 Switching Threshold
Amplifier Output Sink Current
Amplifier Output Source Current
Channel 2 Error Amplifier
Input Common-mode Voltage Range(1)
0
3
V
Inverting Input Voltage Range(1)
0
AVCC
V
±3
mV
Input Offset Voltage
© 2006 Semtech Corp.
0 ~ 70° C
3
±1
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SC2447
POWER MANAGEMENT
Electrical Characteristics (Cont.)
Unless specified: AVCC = 12V, SYNC = 0, ROSC = 51.1kΩ, -40°C < TA = TJ < 125°C
Parameter
Non-inverting Input Bias Current
Inverting Input Bias Current
Symbol
Conditions
Typ
Max
Units
IREFIN
-100
-250
nA
IIN2-
-150
-380
nA
Inverting Input Voltage for 2-Phase Single
Output Operation
Min
2.5
V
Amplifier Transconductance
GM2
170
µΩ −1
Amplifier Open-Loop Gain
aOL2
65
dB
5
MHz
V C S 2+ = V C S 2- = 0
VSS2 Increasing
1.7
V
Amplifier Output Sink Current
VCOMP2 = 2.5V
11
µA
Amplifier Output Source Current
VCOMP2 = 2.5V
8.5
µA
Amplifier Unity Gain Bandwidth(1)
Minimum COMP2 Switching Threshold
Oscillator
Channel Frequency
fCH1, fCH2
0 ~ 70° C
Synchronizing Frequency(1)
SYNC Input High Voltage
450
500
kHz
1.5
V
VSYNC = 0.2V
VSYNC = 2V
ISYNC
Channel Maximum Duty Cycle
DMAX1,
DMAX2
Channel Minimum Duty Cycle
DMIN1, DMIN2
kHz
2.1fCH
SYNC Input Low Voltage
SYNC Input Current
550
0.5
V
1
50
µA
88
%
0
%
AVCC - 1.5
V
50
57.5
mV
Current-limit Comparators
Input Common-Mode Range
0
VILIM1+,
VILIM2+
VCS1- = VCS2- = 0.5V,
Sourcing Mode, 0 ~ 70° C
Positive Current-Sense Input Bias Current
ICS1+, ICS2+
V C S 1+ = V C S 1- = 0
V C S 2- = V C S 2- = 0
-0.7
-2
µA
Negative Current-Sense Input Bias
Current
ICS1-, ICS2-
V C S 1+ = V C S 1- = 0
V C S 2+ = V C S 2- = 0
-0.7
-2
µA
Peak Source Current
GDL1, GDL2,
GDH1, GDH2
AVCC = 12V
10
mA
Peak Sink Current
GDL1, GDL2,
GDH1, GDH2
AVCC = 12V
8
mA
Cycle-by-cycle Peak Current Limit
42.5
PWM Outputs
© 2006 Semtech Corp.
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SC2447
POWER MANAGEMENT
Electrical Characteristics (Cont.)
Unless specified: AVCC = 12V, SYNC = 0, ROSC = 51.1kΩ, -40°C < TA = TJ < 125°C
Parameter
Symbol
Conditions
Min
Output High Voltage
Source IO = 1.2mA, 0 ~ 70° C
Output Low Voltage
Sink IO = 1mA
Maximum Tri-State Leakage
Current
Propagation delay time from
current sense inputs to PWM
output(1)
Typ
Max
Units
4.1
5
V
0
0.4
V
2
µA
GDH in High Impedance State
TDLPWM
TA =25° C
85
ns
VSS1 = VSS2 = 1.5V
9.5
µA
VSS1 and VSS2 Increasing
3.2
V
VIN1-= 0.5VREF,VIN2-= 0.5VREFIN ,
VSS1 = VSS2 > 2.85V
37
µA
VIN1-= 0.5VREF,VIN2-= 0.5VREFIN ,
VSS1 = VSS2 < 2.85V
7.5
µA
VSS1 and VSS2 Decreasing
2.85
V
VSS1 and VSS2 Decreasing
0.5
V
Soft-Start, Overload Hiccup and Enable
Soft-Start Charging Current
ISS1, ISS2
Overload Hiccup Enabling
Voltage
Soft-Start Discharging Current
at Over Current Condition
ISS1(DIS),
ISS2(DIS)
Overload Hiccup Threshold
Voltage
Overload Hiccup Recovery
Soft-Start Voltage
VSSRCV1,
VSSRCV2
PWM Output Disable SS/EN
Voltage
PWM Output Enable SS/EN
Voltage
0.6
V
1.2
1.5
V
500
505
mV
Internal 0.5V Reference Buffer
Output Voltage
VREFOUT
IREFOUT = -1mA, 0° C < TA = TJ < 70° C
Load Regulation
0 < IREFOUT < -5mA
Line Regulation
AVCCTH < AVCC < 15V, IREFOUT = -1mA
495
0.05
%/mA
0.02%
%V
Notes:
(1) Guaranteed by design, not tested in production.
© 2006 Semtech Corp.
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SC2447
POWER MANAGEMENT
Typical Performance Characteristics
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SC2447
POWER MANAGEMENT
Typical Application Circuit Performance
Circuit Conditions: 2-Output Configuration as in Figure 16. VIN = 12V, VOUT1 = 2.5V, VOUT2 = 1.2V, ROSC = 51.1kΩ, SYNC = 0, and TA = 25°C.
Pre-biased Start Up (VOUT1)
Soft-Start Up (VOUT1)
VOUT1
1V/div
VOUT1
1V/div
VOUT1
1V/div
Shutdown (VOUT1)
IOUT1
2A/div
VSS1/EN1
2V/div
VSS1/EN1
2V/div
VSS1/EN1
5V/div
IOUT1
10A/div
VGDL1
5V/div
IOUT1=0A
10ms/div
Output Voltage Ripple (VOUT1)
VOUT1
20mV/div
ROUT1=1Ω
10ms/div
Load Transient Response (VOUT1)
200µs/div
Overload Hiccup (VOUT1)
VOUT1
1V/div
VOUT1
0.1V/div
VSS1/EN1
2V/div
IOUT1
10A/div
VSW1
10V/div
IOUT1
5A/div
IOUT1=20A
IOUT1
20A/div
IOUT1=15A to 20A
2µs/DIV
Soft-Start Up (VOUT2)
200µs/div
50ms/div
Pre-biased Start Up (VOUT2)
Shutdown (VOUT2)
VOUT2
0.5V/div
VOUT2
0.5V/div
VOUT2
0.5V/div
VSS2/EN2
2V/div
VSS2/EN2
2V/div
IOUT2
1A/div
VSS2/EN2
5V/div
IOUT2
20A/div
IOUT2
20A/div
VGDL2
5V/div
10ms/div
© 2006 Semtech Corp.
IOUT2=0A
10ms/div
7
ROUT2=1Ω
200µs/div
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SC2447
POWER MANAGEMENT
Typical Application Circuit Performance
Circuit Conditions: 2-Output Configuration as in Figure 16. VIN = 12V, VOUT1 = 2.5V, VOUT2 = 1.2V, ROSC = 51.1kΩ, SYNC = 0, and TA = 25°C.
Output Voltage Ripple (VOUT2)
Load Transient Response (VOUT2)
Overload Hiccup (VOUT2)
VOUT2
0.1V/div
VOUT2
20mV/div
VOUT2
0.5V/div
VSS2/EN2
2V/div
IOUT2
10A/div
IOUT2
5A/div
IOUT2=25A
IOUT2
20A/div
IOUT2=20A to 25A
2µs/DIV
Output Voltage Ripple
VOUT1 & VOUT2
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20mV/div
VSW2
10V/div
50ms/div
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20mV/div
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10V/div
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10V/div
IOUT1=20A
IOUT2=25A
1µs/DIV
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Circuit Conditions: 2-Ouput Configuration, VIN = 12V, LOUT=0.4uH for VOUT= 1.2V, LOUT=1uH for VOUT= 2.5V, 3.3V, and 5.0V, ROSC = 51.1kΩ, and TA = 25°C.
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SC2447
POWER MANAGEMENT
Typical Application Circuit Performance
Circuit Conditions: 2-Phase Configuration as in Figure 17, VIN = 12V, VOUT = 1.2V, ROSC = 51.1kΩ, SYNC = 0, and TA = 25°C.
Pre-biased Start Up (VOUT)
Soft-Start Up
Shutdown (VOUT)
VOUT
0.5V/div
VOUT
0.5V/div
VOUT
0.5V/div
VSS1/EN1
2V/div
VSS1/EN1
2V/div
IOUT
1A/div
VSS1/EN1
5V/div
IOUT
20A/div
IOUT
20A/div
VGDL1
5V/div
IOUT=0A
10ms/div
Output Voltage Ripple (VOUT)
ROUT2=1Ω
10ms/div
Load Transient Response (VOUT)
Overload Hiccup (VOUT)
VOUT
20mV/div
VOUT
0.5V/div
VOUT
0.1V/div
VSS1/EN1
2V/div
IOUT
50A/div
VSW1
10V/div
IOUT
10A/div
VSW2
10V/div
IOUT2=40A to 50A
1µs/DIV
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SC2447
POWER MANAGEMENT
Pin Descriptions
Pin
Pin Name Pin Function
1
C S 1+
The Non-inverting Input of Channel 1 Current-sense Amplifier/Comparator
2
C S 1-
The Inverting Input of Channel 1 Current-sense Amplifier/Comparator. Normally tied to the
output of the converter.
3
ROSC
An external resistor connected from this pin to AGND sets the oscillator frequency.
4
IN1-
5
COMP1
6
SYNC
Edge-triggered Synchronization Input. When not synchronized, tie this pin to a voltage above
1.5V or ground. An external clock (frequency > frequency set with ROSC) at this pin
synchronizes the controllers.
7
AGND
Analog Signal Ground.
8
REF
9
REFOUT
10
REFIN
11
COMP2
12
IN2-
The Inverting Input of Channel 2 Error Amplifier. Tie an external resistive divider between
output 2 and ground for output voltage sensing. Tie to AVCC for two-phase single output
applications.
13
C S 2-
The Inverting Input of Channel 2 Current-sense Amplifier/Comparator. Normally tied to the
output of the converter.
14
C S 2+
The Non-inverting Input of Channel 2 Current-sense Amplifier/Comparator.
15
SS2/EN2
16
AVCC
Power Supply Voltage for the Analog Portion of the Controllers.
20
GDH2
PWM Output 2.
21
GDL2
Logic Enable Signal for Channel 2.
24
GDL1
Logic Enable Signal for Channel 1.
25
GDH1
PWM Output 1.
28
SS1/EN1
17,18,19
22,23,26,27
NC
© 2006 Semtech Corp.
Inverting Input of Channel 1 Error Amplifier. Tie an external resistive divider between output
1 and ground for output voltage sensing.
The Channel 1 Error Amplifier Output. This pin is used for loop compensation.
The Non-inverting Input of Channel 1 Error Amplifier.
Buffered 0.5V internal reference.
An external reference voltage is applied to this pin. This is also the non-inverting input of
Channel 2 Error amplifier.
The Channel 2 Error Amplifier Output. This pin is used for loop compensation.
An external capacitor tied to this pin sets (1) the soft-start time (2) output overload shutdown
time for Channel 2. Pulling this pin below 0.6V tri-states GHD2 and forces GDL2 low. Leave
open for two-phase single output applications.
An external capacitor tied to this pin sets (1) the soft-start time (2) output overload shutdown
time for Channel 1. Pulling this pin below 0.6V tri-states GDH1 and forces GDL1 low.
No Connection.
10
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POWER MANAGEMENT
Block Diagram
SYNC
6
ROSC
3
CLK2
FREQUENCY
DIVIDER
CLK
OSCILLATOR
AVCC
1.25V
CLK1
16
REFERENCE
SLOPE COMP.
COMP1
5
0.5V
IN1
4
25
SLOPE2
-
+
+
REF
8
GDH1
R
-
EA1
S
+
REFSS1
TRI-STATE1
Q
PWM1
TGON1
SLOPE1
GDL1
24
UV
CS1+
1
CS12
+
+ISEN1
-
Σ
+
CLK1
+ILIM1+
OC1
50mV
SSL1
PRE-BIAS
SOFT-START
&
OVERLOAD
HICCUP
CONTROL 1
OL1
DSBL1
SS1/EN1
SS1/EN1
28
1.25V
0.5V
2R
+
REFOUT
9
-
R
UVLO
4.3/4.5V
AGND
7
COMP2
11
B
SEL
2.5V
-
A
Y
CLK2
MUX
+
IN2
12
-
+
+
REFIN
10
EA2
13
-
R
+
S
TRI-STATE2
Q
PWM2
REFSS2
CS2+
14
CS2-
GDH2
20
ANALOG
SWITCH
TGON2
SLOPE2
UV
+
+ Σ
ISEN2
-
+
ILIM2+
50mV
GDL2
21
+
CLK2
OC2
SSL2
PRE-BIAS
SOFT-START
&
OVERLOAD
HICCUP
CONTROL 2
OL2
DSBL2
SS2/EN2
SS2/EN2
15
R
2R
1.25V
REFSS2
Figure 3. SC2447 Block Diagram
© 2006 Semtech Corp.
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SC2447
POWER MANAGEMENT
Block Diagram
2.85V
S
+
0.5V/3.2V
OL
Q
9.5uA
R
SS/EN
COMP
SSL
-
S
+
Q
0.8V
DSBL
(0.6V min.)
R
R
17.0uA
UV
Q
CLK
S
46.5uA
TGON
OC
Figure 4. Soft-Start and Overload Hiccup Control Circuit
© 2006 Semtech Corp.
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SC2447
POWER MANAGEMENT
Timing Chart
AVCC
AVCC
4.5V
4.5V
VSS/EN
3.2V
3.2V
VSS/EN
Enable Hiccup
Enable Hiccup
VCOMP
VCOMP
1.5V
1.5V
1.25V
1.25V
0
0
VREFSS
VIN-
0.5V (VREF)
0
VREFSS
VIN-
0.5V (VREF)
0
GDH
0
GDH in high impedance state
GDL
0
t0
t1
t2 t4
t5
GDH
0
GDH in high impedance state
GDL
0
t0
t6 t7
(a) Normal Start Up
t1
t2
t3t4
t5 t6 t7
(b) Pre-Biased Start Up
Figure 5. SC2447 Start-up Timing Diagram
AVCC
4.3V
VSS/EN
VCOMP
VREFSS
0.5V (VREF)
VIN-
GDH
GDH in high impedance state
GDL
t16
t17
Figure 6. SC2447 UVLO Shutdown Timing Diagram
© 2006 Semtech Corp.
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SC2447
POWER MANAGEMENT
Timing Chart
VSS/EN
3.2V
Enable Hiccup
Enable Hiccup
2.85V
VCOMP
1.50V
1.25V
0.8V
0.5V
0V
VIN-
0.5V
Reference Voltage
Min.(VREF, VREFSS)
0V
GDH i n high impedance state
GDH
0V
GDL
0V
t7
t8
t9
t10 t11 t12
t13
t14
t15
Figure 7. SC2447 Overload Hiccup Operation Timing Diagram
© 2006 Semtech Corp.
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SC2447
POWER MANAGEMENT
Application Information
The SC2447 consists of two current-mode synchronous
buck controllers with many integrated functions. The
SC2447 can be used to generate:
1) two independent outputs from a common input or
two different inputs or,
2) dual-phase output with current sharing,
3) current sourcing/sinking from common or separate
inputs as in DDR (I and II) memory application.
For a given output power, the size of the passive
components are inversely proportional to the switching
frequency, whereas MOSFET/Diode switching losses are
proportional to the operating frequency. Other issues such
as heat dissipation, packaging and the cost issues are
also considered. The frequency bands for signal
transmission should be avoided because of EM
interference.
Minimum Switch On Time Consideration
Step-Down Converter
Starting from the following step-down converter
specifications,
Input voltage range: Vin ∈ [ Vin,min , Vin,max ]
Input voltage ripple (peak-to-peak): ∆Vin
Output voltage: Vo
Output voltage accuracy: ε
Output voltage ripple (peak-to-peak): ∆Vo
Nominal output (load) current: Io
Maximum output current limit: Io,max
Output (load) current transient slew rate: dIo (A/s)
Circuit efficiency: η
Selection criteria and design procedures for the following
are described.
1)
2)
3)
4)
5)
6)
7)
output inductor (L) type and value
output capacitor (Co) type and value
input capacitor (Cin) type and value
power MOSFETs
current sensing and limiting circuit
voltage sensing circuit
loop compensation network
Operating Frequency (fs)
The switching frequency in the SC2447 is userprogrammable. The advantages of using constant
frequency operation are simple passive component
selection and ease of feedback compensation. Before
setting the operating frequency, the following trade-offs
should be considered:
1) Passive component size
2) Efficiency
3) EMI condition
4) Minimum switch on time
5) Maximum duty ratio
© 2006 Semtech Corp.
In the SC2447, the falling edge of the clock turns on the
top MOSFET. The inductor current and the sensed voltage
ramp up. After the sensed voltage crosses a threshold
determined by the error amplifier output, the top MOSFET
is turned off. The propagation delay time from the turnon of the controlling FET to its turn-off is the minimum
switch on time. This propagation delay time consists of
the propagation delay time (TDLPWM) from the current sense
inputs to the PWM output and the propagation delay time
(TDLTG) from the trailing edge of the PWM input to the
trailing edge of the phase voltage.
The SC2447 has a typical propagation delay time from
the current sense inputs to the PWM output of about
85ns at room temperature. The shortest on interval
(TMINON) of the controlling FET is then 85ns+TDLTG. Assuming
that TDLTG is 45ns, the controller either does not turn on
the top MOSFET at all or turns it on for at least 130ns.
TDLTG can be found in the MOSFET driver datasheet.
For a synchronous step-down converter, the operating duty
cycle is VO/VIN. The required on time for the top MOSFET
is VO/(VIN*fs). If the frequency is set such that the required
pulse width is less than 130ns, assuming TDLTG is 45ns,
then the converter will start skipping cycles. Due to
minimum on-time limitation, simultaneously operating at
very high switching frequency and very short duty cycle is
not practical. If the voltage conversion ratio VO/VIN and
hence the required duty cycle is higher, the switching
frequency can be increased to reduce the size of passive
components.
There will not be enough modulating headroom if the on
time is made equal to the minimum on time (TMINON). For
ease of control, set the switching frequency so that the
pulse width is at least 1.5 times the minimum on time.
15
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SC2447
POWER MANAGEMENT
Application Information (Cont.)
Setting the Switching Frequency
Consider the following when choosing inductors:
The switching frequency is set with an external resistor
connected from Pin 3 to the ground. The set frequency is
inversely proportional to the resistor value (Figure 8).
a) Inductor core material: For high efficiency applications
above 350kHz, ferrite, Kool-Mu and polypermalloy
materials should be used. Low-cost powdered iron cores
can be used for cost sensitive-applications below 350kHz
but with attendant higher core losses.
800
b) Select inductance value: Sometimes the calculated
inductance value is not available off-the-shelf. The designer
can choose the next larger standard inductance value.
The inductance varies with temperature and DC current.
It is a good engineering practice to re-evaluate the
resulting current ripple at the rated DC output current.
700
fs (kHz)
600
500
400
300
200
100
0
0
50
100
150
200
250
c) Current rating: The saturation current of the inductor
should be at least 1.5 times of the peak inductor current
under all conditions.
Rosc (k Ohm)
Output Capacitor (Co) and Vout Ripple
Figure 8. Free Running Frequency vs. ROSC
Inductor (L) and Ripple Current
Both step-down controllers in the SC2447 operate in
synchronous continuous-conduction mode (CCM)
regardless of the output load. The output inductor
selection/design is based on the output DC and transient
requirements. Both output current and voltage ripples
are reduced with larger inductors but it takes longer to
change the inductor current during load transients.
Conversely, smaller inductors results in lower DC copper
losses but the AC core losses (flux swing) and the winding
AC resistance losses are higher. A compromise is to
choose the inductance such that peak-to-peak inductor
ripple-current is 20% to 30% of the rated output load
current.
Assuming that the inductor current ripple (peak-to-peak)
value is δ*Io, the inductance value will then be
The output capacitor filters the inductor current in the
steady state and serves as a reservoir during load transient.
The output capacitor can be modeled as an ideal capacitor
in series with its parasitic ESR (Resr) and ESL (Lesl) (Figure
9 ).
Co
Lesl
Resr
Figure 9. An Equivalent Circuit of Co
If the current through the branch is ib(t), the voltage across
the terminals will then be
t
V (1 − D)
.
L= o
δI o f s
vo (t ) = Vo +
The peak current in the inductor becomes (1+δ/2)*Io
and the RMS current is
I L,rms = I o 1 +
© 2006 Semtech Corp.
δ2
12
.
di (t )
1
ib (t )dt + Lesl b + Resr ib (t ).
∫
Co 0
dt
This basic equation illustrates the effect of ESR, ESL
and Co on the output voltage.
The first term is the DC voltage across Co at time t=0.
The second term is the voltage variation caused by the
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SC2447
POWER MANAGEMENT
Application Information (Cont.)
charge balance between the load and the converter
output. The third term is voltage ripple due to ESL and
the fourth term is the voltage ripple due to ESR. The
total output voltage ripple is then the vector sum of the
last three terms.
Since the inductor current waveform is a triangular with
peak-to-peak value δ*Io, the ripple-voltage caused by
inductor current ripple is
∆v C ≈
δIo
,
8C o fs
the ripple-voltage due to ESL is
∆v ESL = L esl fs
The voltage rating of aluminum capacitors should be at
least 1.5Vo. The RMS current ripple rating should also
be greater than
δIo
2 3
.
Usually it is necessary to have several capacitors of the
same type in parallel to satisfy the ESR requirement. The
voltage ripple cause by the capacitor charge/discharge
should be an order of magnitude smaller than the voltage
ripple caused by the ESR. To guarantee this, the
capacitance should satisfy
δIo
,
D
Co >
10
.
2πfsR esr
and the ESR ripple-voltage is
∆v ESR = R esr δIo .
Aluminum capacitors (e.g. electrolytic, solid OS-CON,
POSCAP, tantalum) have high capacitances and low ESLs.
The ESR has the dominant effect on the output ripple
voltage. It is therefore very important to minimize the
ESR.
When determining the ESR value, both the steady state
ripple-voltage and the dynamic load transient need to be
considered. To keep the steady state output ripplevoltage < ∆Vo, the ESR should satisfy
R esr1 <
∆Vo
.
δIo
To limit the dynamic output voltage overshoot/
undershoot to within α (say 3%) of the steady state
output voltage) from no load to full load, the ESR value
should satisfy
R esr 2 <
αVo
.
Io
Then, the required ESR value of the output capacitors
should be
Resr = min{Resr1,Resr2 }.
© 2006 Semtech Corp.
In many applications, several low ESR ceramic capacitors
are added in parallel with the aluminum capacitors in
order to further reduce ESR and improve high frequency
decoupling. Because the values of capacitance and ESR
are usually different in ceramic and aluminum capacitors,
the following remarks are made to clarify some practical
issues.
Remark 1: High frequency ceramic capacitors may not
carry most of the ripple current. It also depends on the
capacitor value. Only when the capacitor value is set
properly, the effect of ceramic capacitor low ESR starts
to be significant.
For example, if a 10µF, 4mΩ ceramic capacitor is
connected in parallel with 2x1500µF, 90mΩ electrolytic
capacitors, the ripple current in the ceramic capacitor is
only about 42% of the current in the electrolytic
capacitors at the ripple frequency. If a 100µF, 2mΩ
ceramic capacitor is used, the ripple current in the
ceramic capacitor will be about 4.2 times of that in the
electrolytic capacitors. When two 100µF, 2mΩ ceramic
capacitors are used, the current ratio increases to 8.3.
In this case most of the ripple current flows in the
ceramic decoupling capacitor. The ESR of the ceramic
capacitors will then determine the output ripple-voltage.
Remark 2: The total equivalent capacitance of the filter
bank is not simply the sum of all the paralleled capacitors.
The total equivalent ESR is not simply the parallel
combination of all the individual ESRs either. Instead
17
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SC2447
POWER MANAGEMENT
Application Information (Cont.)
they should be calculated using the following formulae.
(R1a + R1b )2 ω2C1a C1b + (C1a + C1b )2
2
C eq (ω) :=
2
(R1a C1a + R1b C1b )ω2 C1a C1b + (C1a + C1b )
2
2
R1aR1b (R1a + R1b )ω2C1a C1b + (R1b C1b + R1a C1a )
2
R eq (ω) :=
2
2
2
(R1a + R1b )2 ω2 C1a C1b + (C1a + C1b )2
2
2
where R 1a and C 1a are the ESR and capacitance of
electrolytic capacitors, and R1b and C1b are the ESR and
capacitance of the ceramic capacitors respectively.
(Figure 10)
C1a
R1a
C1b
R1b
Figure 11. A Simple Model for the Converter Input
Ceq
Req
Figure 10. Equivalent RC Branch
Req and Ceq are both functions of frequency. For rigorous
design, the equivalent ESR should be evaluated at the
ripple frequency for voltage ripple calculation when both
ceramic and electrolytic capacitors are used. If R1a = R1b =
R1 and C1a = C1b = C1, then Req and Ceq will be frequencyindependent and
Req = 1/2 R1 and Ceq = 2C1.
Input Capacitor (Cin)
The input supply to the converter usually comes from a
pre-regulator. Since the input supply is not ideal, input
capacitors are needed to filter the current pulses at the
switching frequency. A simple buck converter is shown in
Figure 11.
In Figure 11 the DC input power supply has an internal
impedance Rin and the input capacitor Cin has an ESR of
R esr . The MOSFET and the input capacitor current
waveforms, the ESR voltage ripple and the input voltage
ripple are shown in Figure 12.
© 2006 Semtech Corp.
Figure 12. Typical Waveforms at Converter Input
It can be seen that high di/dt pulse current flows in the
input capacitor. Capacitors with low ESL should be used.
It is also important to place the input capacitor close to
the MOSFETs on the PC board to reduce trace inductance
around the pulse current loop.
The RMS value of the capacitor current is approximately
ICin = Io D[(1+
δ2
12
D
D
)(1− )2 + 2 (1− D) ].
η
η
The power dissipated in the input capacitor is then
PCin = ICin2Resr.
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SC2447
POWER MANAGEMENT
Application Information (Cont.)
For reliable operation, the maximum power dissipation
in the capacitors should not result in more than 10oC of
temperature rise. Many manufacturers specify the
maximum allowable ripple current (ARMS), rating of the
capacitor at a given ripple frequency and ambient
temperature. The input capacitance should be large
enough to handle the ripple current. For higher power
applications, multiple capacitors are placed in parallel to
increase the ripple current handling capability.
Sometimes meeting tight input voltage ripple
specifications may require the use of larger input
capacitance. At full load, the peak-to-peak input voltage
ripple due to the ESR is
δ
∆v ESR = Resr (1 + ) I o .
2
The peak-to-peak input voltage ripple due to the capacitor
is
∆vC ≈
DI o
,
Cin f s
From these two expressions, CIN can be found to meet
the input voltage ripple specification. In a multi-phase
converter, interleaved switching reduces ripple. The two
step-down channels of the SC2447 operate at 180 degrees
from each other. If both step-down channels in the SC2447
are connected in parallel, both the input and the output
RMS currents will be reduced.
If D1<0.5 and D2<0.5, then
I Cin ≈ D1I o1 + D2 I o2 .
2
Choosing Power MOSFETs
Power MOSFETs with integrated gate drivers such as
PIP212, R2J20601NP, PIP202, PIP201 and IP2001,
IP2002 are suitable for SC2447 application.
Current Sensing
Inductor current sensing is required for the current-mode
control. Although the inductor current can be sensed
with a precision resistor in series with the inductor, the
lossless inductive current sense technique can be used
in the SC2447. This technique has the advantages of,
1) lossless current sensing
2) lower cost compared to resistive sensing
3) more accurate compared to RDS(ON) sensing
The basic arrangement of the inductive current sense is
shown in Figure 13.
RL is the equivalent series resistance of the output inductor.
Rs and Cs form a RC network for inductor current sensing.
Ripple cancellation effect of interleaving allows the use
of smaller input capacitors. When converter outputs are
connected in parallel and interleaved, a smaller inductor
and capacitor can be used for each channel. The total
output ripple-voltage remains unchanged. The use of a
smaller inductor helps speed up the output load
transient.
When two channels with a common input are interleaved,
the combined input current waveform depends on the duty
ratios and the output currents of both channels. Assuming
that the output current ripple is small, the following formula
can be used to estimate the RMS ripple current in the
input capacitor.
Let the duty ratio and output current of Channel 1 and
Channel 2 be D1, D2 and Io1, Io2, respectively.
© 2006 Semtech Corp.
2
Vin
Q1
iL(t)
Cin
L
RL
Rs
Cs
Vo
Q2
Cout
Rload
vC(t)
Figure 13. The Basic Structure of Inductive Current
Sense
In steady state, the DC voltage across RL is
VCS = RL IO .
Notice that the DC value of VCs is independent of the
values of L, Rs and Cs. This means that, if only the
average load current information is needed (such as in
19
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SC2447
POWER MANAGEMENT
Application Information (Cont.)
average current mode control), this current sensing
method is sufficient without time constant matching
requirement.
In the current mode control as implemented in SC2447,
voltage ripple on Cs is required for PWM operation. In
fact, the VCs AC peak-to-peak voltage ripple (denoted as
∆VCs) directly affects the signal-to-noise ratio of the PWM
operation. In general, smaller ∆VCs leads to lower signalto-noise ratio and more noise sensitive operation. Larger
∆V Cs leads to more circuit (power stage) parameter
sensitive operation. A good engineering compromise is:
∆VCs~ RL δIo.
of 22nF ~ 330nF.
a) When the required current limit ILM is higher than ILMcp,
Rs3 is not needed and solve the following three equations
for Rs, Rs1, and Rs2:
L
,
RL
( Rs // Rs1 ) Cs =
I LM RL
Rs1
= 50mV ,
Rs + Rs1
R s 2 = R s // R s1 .
and
It is necessary to match the following time constants to
equalize the ripple.
Note that RS2 is made equal to RS//RS1 to reduce effect
of the bias current of the current amplifier in SC2447.
L
≈ Rs C s .
RL
b) When the required current limit ILM is less than ILMcp,
remove Rs1 and solve the following two equations for Rs
and Rs3:
For example, L = 1µH and RL = 1.8mΩ, the time constant
RsCs should be set to 555.6µs. If one selects Cs = 33nF,
then Rs = 16.9 kΩ.
RsCs =
Scaling the Current Limit
I LM RL +
Over-current is handled differently in the SC2447
depending on the direction of the inductor current. If
the differential sense voltage between CS+ and CSexceeds +50mV, the PWM signal (GDH) will go low. The
MOSFET driver will turn off the top MOSFET and turn on
the bottom MOSFET, to limit the inductor current. This
+50mV is the cycle-by-cycle peak current limit when the
load is drawing current from the converter. There is no
cycle-by-cycle current limit when the inductor current flows
in the reverse direction.
L
,
RL
Rs
VO = 50mV ,
Rs 3
Rs2 is then calculated from
Rs 2 =
Rs 3 Rs
.
Rs 3 − Rs
Vin
Q1
Vgs1
iL(t)
L
RL
PN
Cin
In the circuit of Figure 13, the equivalent inductor current
limit is set according to
Rs
Rs1
Vo
Q2
Cs
Cout
Rload
Vgs2
vC(t)
I LMcp
50mV
=
,
RL
when the load is sourcing current from the converter. If
RL = 1.8mΩ, then ILMcp = 27.8A. The circuit in Figure 14
allows the user to scale the equivalent current limit with
the same RL.
ISEN
1
-
2
Rs2
Rs3
CS in the current sensing network is usually in the range
© 2006 Semtech Corp.
+
Figure 14. Scaling the Equivalent Current Limit
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SC2447
POWER MANAGEMENT
Application Information (Cont.)
Overload Protection and Hiccup
During start-up, the capacitor from the SS/EN pin to
ground functions as a soft-start capacitor. After the
converter starts and enters regulation, the same
capacitor operates as an overload shutoff timing
capacitor. There is an internal net 9.5µA current source
charging the soft start capacitor C32(C33), connected to
the SS/EN pin. The soft-start voltage VSS/EN will reach its
final value if no current limit occurs. As the load current
increases, the cycle-by-cycle current-limit comparator will
first limit the inductor current. If VSS/EN is higher than
3.2V, an internal net 37µA current source will discharge
the soft-start capacitor C32(C33) during the off time after
tripping the over-current comparator. If VSS/EN falls to
2.85V, the controller will shut off both the top and the
bottom MOSFETs by pulling down the GDL and tri-stating
the GDH output (PWM). An internal net 7.5µA current
source discharges C32(C33) .
When the capacitor is discharged below 0.5V, the overload
hiccup latch is reset, the 9.5µA current source recharges
the SS/EN capacitor and converter restarts. The overload
hiccup function is enabled when the soft start capacitor
voltage exceeds 3.2V. The converter will repeatedly start
and shut off until it is no longer overloaded when the
soft-start voltage exceeds 3.2V. This hiccup mode of
overload protection is a form of foldback current limiting.
The following calculations estimate the average inductor
current when the converter output is shorted to the
ground:
a) The time taken to discharge the capacitor from 3.2V
to 2.85V is
t ssf 1 = C32
(3.2 − 2.85)V
.
37 µA
If C32 = 0.1µF, tssf1 is calculated as 0.945ms.
b) The time taken to discharge the capacitor from 2.85V
to 0.5V is
t ssf 2 = C32
( 2.85 − 0.5)V
.
7.5µA
When C32 = 0.1µF, tssr is calculated as 28.4ms. Note
that during soft start, the converter only starts switching
when the voltage at SS/EN exceeds 1.25V.
d) The effective start-up time is
The average inductor current is then
I Leff = I LMcp
Setting the Output Voltage
The non-inverting inputs of channel 1 and channel 2 error
amplifiers are brought out as device pins (Pin 10 and Pin
8). These pins can be tied to the precision 0.5V reference
output (Pin 9) of the SC2447. A simple voltage divider
(Ro1 at top and Ro2 at bottom) sets the converter output
voltage. The voltage feedback gain h=0.5/Vo is related
to the divider resistors as follows:
Ro 2 =
h
Ro1 .
1− h
Once either R o1 or R o2 is chosen, the other can be
calculated for the desired output voltage Vo. Since the
number of standard resistance values is limited, the
calculated resistance may not be available as a standard
value resistor. As a result, there will be a set error in the
converter output voltage. This non-random error is
caused by the feedback voltage divider ratio. It cannot
be corrected by the feedback loop.
The following table lists a few standard resistor
combinations for realizing some commonly used output
voltages.
c) The soft start time from 0.5V to 3.2V is
© 2006 Semtech Corp.
t sso
t ssf 1 + t ssf 2 + t ssr .
ILeff ≈ 0.34 ILMcp and is independent of the soft start
capacitor value. The converter will not overheat in
hiccup.
If C32 = 0.1µF, tssf2 is calculated as 31.3ms.
t ssr
(3.2 − 1.25)V
.
9.5µA
t sso = C32
(3.2 − 0.5)V
= C32
.
9.5µA
21
Vo (V)
0.6
0.9
1.2
1.5
1.8
2.5
3.3
(1- h)/h
0.2
0.8
1.4
2
2.6
4
5.6
Ro1 (Ohm)
200
806
1.4K
2.0K
2.61K
4.02K
5.62K
Ro2 (Ohm)
1K
1K
1K
1K
1K
1K
1K
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SC2447
POWER MANAGEMENT
Application Information (Cont.)
Only the voltages in boldface can be precisely set with
standard 1% resistors.
From this table, one may also observe that when the
value
1 − h Vo − 0.5
=
.
0.5
h
and its multiples fall into the standard resistor value
chart (1%, 5% or so), it is possible to use standard value
resistors to set up the exact and required output voltage
value.
The slope of the compensation ramp is then
S e=0.4*fs.
The slope of the internal compensation ramp is well above
the minimal slope requirement for current loop stability
and is sufficient for all the applications.
With the inner current loop stable, the output voltage is
then regulated with the outer voltage feedback loop. A
simplified equivalent circuit model of the synchronous
Buck converter with current mode control is shown in
Figure 15.
The input bias current of the error amplifier also causes
an error in setting the output voltage. The maximum
inverting input bias current of the error amplifiers is 380nA. Assuming the non-inverting input is tied to the
0.5V reference output, the percentage error in the
second output voltage will be –100% · (0.38 µA) ·
R R
/[0.5 · (R +R ) ]. To keep this error below
o1 o2
o1 o2
0.2%, R
< 2.6kΩ.
o2
Loop Compensation
k
SC2447 uses current-mode control for both step-down
channels. Current-mode control is a dual-loop control
system in which the inductor peak current is loosely
controlled by the inner current-loop. The higher gain outer
loop regulates the output voltage. Since the current loop
makes the inductor appear as a current source, the complex
high-Q poles of the output LC network are split into a
dominant pole determined by the output capacitor and
the load resistance and a high frequency pole. This polesplitting property of current-mode control greatly simplifies
loop compensation.
The inner current-loop is unstable (sub-harmonic
oscillation) unless the inductor current up-slope is steeper
than the inductor current down-slope. For stable
operation above 50% duty-cycle, a compensation ramp
is added to the sensed-current. In the SC2447 the
compensation ramp is approximately
Figure 15. A Simple Model of Synchronous Buck
Converter with Current Mode Control
The transconductance error amplifier (in the SC2447)
has a gain gm of 170µA/V. The target of the compensation
design is to select the compensation network consisting
of C2, C3 and R2, along with the feedback resistors Ro1,
Ro2 and the current sensing gain, such that the converter
output voltage is regulated with satisfactory dynamic
performance.
Vramp=D*0.4V.
© 2006 Semtech Corp.
22
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SC2447
POWER MANAGEMENT
Application Information (Cont.)
PC Board Layout Issues
Circuit board layout is very important for the proper
operation of high frequency switching power converters.
A power ground plane is required to reduce ground
bounces. The followings are suggested for proper layout.
Power Stage
1) Separate the power ground from the signal ground. In
the SC2447, the power ground PGND should be tied to
the source terminal of lower MOSFETs. The signal ground
AGND should be tied to the negative terminal of the
output capacitor.
2) Minimize the size of high pulse current loop. Place
the top MOSFET, bottom MOSFET and the input
capacitors close to each other with short and wide traces.
In addition to the aluminum energy storage capacitors,
add multi-layer ceramic (MLC) capacitors from the input
to the power ground to improve high frequency bypass.
Control Section
1) The frequency-setting resistor ROSC should be placed
close to Pin 3. Trace length from this resistor to the
analog ground should be minimized.
2) Solder the bias decoupling capacitor right across the
AVCC and analog ground AGND.
3) Place the current sensing network away from the
power circuit and close to the corresponding CS+ and
CS- pins. Use X7R ceramic capacitor for the sensing
capacitor because of its temperature stability.
4) Use an isolated local ground plane for the controller
and tie it to the negative side of output capacitor bank.
© 2006 Semtech Corp.
23
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© 2006 Semtech Corp.
EN2
24
SS1/EN1
IN1-
Rosc
CS1-
CS1+
CS2+
CS2-
IN2-
COMP2
REFIN
REFOUT
REF
AGND
SYNC
COMP1
SC2447
SS2/EN2
AVCC
NC
NC
NC
GDH2
GDL2
NC
NC
GDL1
GDH1
NC
NC
C35
4.7uF
10
R26
15
16
17
18
19
20
21
22
23
24
25
26
27
28
U1
14
13
12
11
10
9
8
7
6
5
4
3
2
1
C20
0.1uF
51.1K
R5
C37
3.3nF
R21
16.9K
C31
3.3nF
R19
24.9K
C36
10pF
C28
10pF
C18
1uF
10
R24
C53
1uF
D16
3.3V
C52
1uF
D15
3.3V
VSSO
VO
CBN
CBP
VDDO
PIP212-12M
DISABLE
VDDG_EN
VSSC
VI
REG5V
VDDG
VDDC
M1
55
2
56
54
3
4
VSSO
VO
CBN
CBP
VDDO
PIP212-12M
DISABLE
VDDG_EN
VSSC
VI
REG5V
VDDG
VDDC
M2
VIN (12V)
55
2
56
54
3
4
10
5
10
5
C5
R14
2.2
C15
2.2nF
C39
100nF
22uF
C10
R13
2.2
C14
2.2nF
C38
100nF
22uF
C4
C3
C8
C7
68nF
C44
1uF
100pF
20K
RCS-2
200K
RCS+2
C41
C20
C43
1uF
100pF
11K
RCS-1
22.1K
L2
0.4uH/1mOhm
22uF
100nF
RCS+1
C42
C21
L1
1uH/1.8mOhm
C51 22pF
22.1K
R5
22uF 22uF
C9
C2
22uF
C50 22pF
22.1K
R6
22uF 22uF
Figure 16. SC2447/PIP212 Two Outputs Application
VIN= 12V
VOUT= 2.5V/20A, 1.2V/25A
Switching Frequency= 500kHz
M1,M2: Philips PIP212-12M
L1, L2: Delta SPL146 Type Power Inductor
Input Capacitors: Murata GRM31CR61C226K (22uF/16V)
Output Capacitors: TDK C3225X5R0J107K (100uF/6.3V)
Murata GRM31CR60J106K (10uF/6.3V)
C33
0.1uF
1N4148
D18
C32
0.1uF
D17
1N4148
EN1
C19
1uF
10
R23
VIN (12V)
R17
7.15K
R12
10K
R16
2.49K
R11
10K
C22
100uF
C26
100uF
C49
100uF
10uF x 2
C30
1uF
C48
100uF
C27
100uF
C47
10uF x 2
C25
1uF
C24
VO2 (1.2V, 25A)
100uF
C46
VO1 (2.5V, 20A)
SC2447
POWER MANAGEMENT
Typical Application Schematic
www.semtech.com
EN
© 2006 Semtech Corp.
C32
0.1uF
25
IN1-
Rosc
CS1-
CS1+
C35
4.7uF
10K
R17
10K
R27
14
13
12
11
10
9
8
7
6
5
4
3
2
1
10
CS2+
CS2-
IN2-
COMP2
REFIN
REFOUT
REF
AGND
SYNC
COMP1
SC2447
SS2/EN2
AVCC
NC
NC
NC
GDH2
GDL2
NC
NC
GDL1
GDH1
NC
NC
SS1/EN1
R26
15
16
17
18
19
20
21
22
23
24
25
26
27
28
U1
1N4148
D17
C28
10pF
C18
1uF
10
R24
C53
1uF
D16
3.3V
VSSO
VO
CBN
CBP
VDDO
PIP212-12M
DISABLE
VDDG_EN
VSSC
VI
REG5V
VDDG
VDDC
M1
55
2
56
54
3
4
VSSO
VO
CBN
CBP
VDDO
PIP212-12M
DISABLE
VDDG_EN
VSSC
VI
REG5V
VDDG
VDDC
M2
VIN (12V)
55
2
56
54
3
4
10
5
10
5
C5
R14
2.2
C15
2.2nF
C39
100nF
22uF
C10
R13
2.2
C14
2.2nF
C38
100nF
22uF
VIN= 12V
VOUT= 1.2V/50A
Switching Frequency= 500kHz
M1,M2: Philips PIP212-12M
L1, L2: Delta SPL146 Type Power Inductor
Input Capacitors: Murata GRM31CR61C226K (22uF/16V)
Output Capacitors: TDK C3225X5R0J107K (100uF/6.3V)
Murata GRM31CR60J106K (10uF/6.3V)
C31
3.3nF
R19
9.31K
C52
1uF
D15
3.3V
C4
C3
C8
R15
2.2M
68nF
R18
2.2M
C44
1uF
100pF
20K
RCS-2
2.2M
RCS+2
C41
C20
C43
1uF
100pF
20K
RCS-1
2.2M
L2
0.4uH/1mOhm
22uF
C7
68nF
RCS+1
C42
C21
L1
0.4uH/1mOhm
C51 22pF
20K
R5
22uF 22uF
C9
C2
22uF
C50 22pF
20K
R6
22uF 22uF
Figure 17. SC2447/PIP212 Dual-Phase Single Output Application
C20
0.1uF
51.1K
R5
C19
1uF
10
R23
VIN (12V)
R16
7.15K
R11
10K
C67
470pF
C24
100uF
C26
100uF
100uF
C47
100uF
C46
100uF
C48
100uF
C49
C22
10uF x 2 1uF x 2
C27
10uF x 2
C30
VO2 (1.2V, 50A)
SC2447
POWER MANAGEMENT
Typical Application Schematic
www.semtech.com
SC2447
POWER MANAGEMENT
Outline Drawing - TSSOP-28
A
DIM
D
e
N
A
A1
A2
b
c
D
E1
E
e
L
L1
N
01
aaa
bbb
ccc
2X E/2
E1
E
PIN 1
INDICATOR
ccc C
2X N/2 TIPS
1 2 3
e/2
B
aaa C
SEATING
PLANE
D
DIMENSIONS
MILLIMETERS
INCHES
MIN NOM MAX MIN NOM MAX
.047
.002
.006
.031
.042
.007
.012
.003
.007
.378 .382 .386
.169 .173 .177
.252 BSC
.026 BSC
.018 .024 .030
(.039)
28
8
0
.004
.004
.008
1.20
0.05
0.15
0.80
1.05
0.19
0.30
0.09
0.20
9.60 9.70 9.80
4.30 4.40 4.50
6.40 BSC
0.65 BSC
0.45 0.60 0.75
(1.0)
28
0
8
0.10
0.10
0.20
A2 A
C
bxN
bbb
H
A1
C A-B D
c
GAGE
PLANE
0.25
SIDE VIEW
SEE DETAIL
L
(L1)
A
DETAIL
01
A
NOTES:
1.
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2.
DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -H-
3.
DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS
OR GATE BURRS.
4.
REFERENCE JEDEC STD MO-153, VARIATION AE.
Land Pattern - TSSOP-28
X
DIM
(C)
G
Z
Y
C
G
P
X
Y
Z
DIMENSIONS
INCHES
MILLIMETERS
(.222)
.161
.026
.016
.061
.283
(5.65)
4.10
0.65
0.40
1.55
7.20
P
NOTES:
1.
THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
Contact Information
Semtech Corporation
Power Management Products Division
200 Flynn Road, Camarillo, CA 93012
Phone: (805)498-2111 FAX (805)498-3804
© 2006 Semtech Corp.
26
www.semtech.com