SC2621A Voltage Mode PWM Controller With Linear Power Regulator POWER MANAGEMENT Description Features u u u u The SC2621A provides the control and protection features necessary for a synchronous buck converter and a linear regulator in high performance graphic card applications. The SC2621A is designed to directly drive the top and bottom MOSFETs of the buck converter. It uses an internal 8.2V supply as the gate drive voltage for minimum driver power loss and MOSFET switching loss. It allows the converter to operate with 4V to 25V power rail and as low as 0.5V output. The SC2621A is capable to drive a N-type MOSFET in a linear regulator with as low as 0.5V output. u u u u u 4V to 25V power rails Internal LDO for optimum gate drive voltage 1.5A gate drive current Adaptive non-overlapping gate drives provide shoot-through protection for MOSFETs Programmable output voltages Internal soft start for both outputs Power rail under voltage lockout Hiccup mode short circuit protection SOIC-14 package, fully RoHS and WEEE compliant Applications The SC2621A features soft-start, supply power under voltage lockout, and hiccup mode over current protection. The SC2621A monitors the output current by using the Rdson of the bottom MOSFET in the buck converter that eliminates the need for a current sensing resistor. The SC2621A is offered in SOIC-14 package. u Graphics processor power supplies on PCI-Express platform u Embedded, low cost, high efficiency converters u Point of load power supplies Typical Application Circuit 12V IN + 1.5V OUT U2 1 3.3V IN 2 3 4 2.5V OUT 5 6 7 + B ST DH OCS PN COMP FB LDOG LDFB GND GND DL DRV NC V CC 14 1 2 13 12 11 + 10 9 8 S C2 621A February 21, 2007 1 www.semtech.com SC2621A POWER MANAGEMENT Absolute Maximum Ratings Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. Parameter Symbol Maximum Units Input Supply Voltage VCC 18 V BST to GND VBST 40 V BST to PN VBST_PN 10 V PN to GND VPN -1 to 30 V VPN_PULSE -5 V VDL -1 to +10 V VDL_PULSE -3 V VDH_PN -1 to +10 V VDH_PULSE -3 V VDRV 10 V Operating Ambient Temperature Range TA -25 to 85 °C Operating Junction Temperature TJ -25 to 125 °C Thermal Resistance Junction to Ambient θJA 100 °C/W Thermal Resistance Junction to Case θJC 32 °C/W Lead Temperature (Soldering) 10s TLEAD 300 °C Storage Temperature TSTG -65 to 150 °C PN to GND Negative Pulse (tpulse < 20ns) DL to GND DL to GND Negative Pulse (tpulse < 20ns) DH to PN DH to PN Negative Pulse (tpulse < 20ns) DRV to GND Electrical Characteristics Unless specified: VCC = 5V to 16V; VFB = VO; VBST - VPN = 5V to 8.2V; TA = -25°C to 85°C Parameter Symbol Conditions Min Typ Max Units 16 V 7 mA 4 V 10 V 3 mA General VCC Supply Voltage VCC VCC Quiescent Current IQVCC VCC = 12V, VBST -VPN = 8.2V VCC Under Voltage Lockout UVVCC VHYST = 100mV BST to PN Supply Voltage VBST_PN BST Quiescent Current 4 5 4 IQBST VCC = 12V, VBST -VPN = 8.2V LDO Output VDRV 8.6V < VCC < 16V 8.2 V Dropout Voltage VDROP 4V < VCC < 8.6V 0.4 V Internal LDO 2007 Semtech Corp. 2 www.semtech.com SC2621A POWER MANAGEMENT Electrical Characteristics Unless specified: VCC = 5V to 16V; VFB = VO; VBST - VPN = 5V to 8.2V; TA = -25°C to 85°C Parameter Symbol Conditions Min Typ Max Units Reference Voltage VOL LDFB = VOL, TA = 25°C, VCC = 12V 0.495 0.500 0.505 V Gain AOLL LDFB to LDOG Linear Section (2) 70 dB Load Regulation IO = 0 to 1A , VIN = 3.3V, VCC = 12V 0.4 % Line Regulation VIN = 3.2V to 3.4V, VCC = 12V 0.4 % VCC Supply Rejection VIN = 3.3V, VCC = 10V to 14V 0.4 % Gate Sourcing Current VGATE = 6.5V 1 mA Gate Sinking Current VGATE = 6.5V 1 mA LDFB = 0.5V -0.2 VIN = 3.3V, VCC = 12V, TA = 25°C 1.5 LDFB Input Bias Current Soft Start Time -1.0 uA ms Sw itching Section Reference Voltage VREF TA = 25°C, VCC = 12V 0.495 0.500 0.505 V Load Regulation IO = 0.2 to 4A 0.4 % Line Regulation VCC = 10V to 14V 0.4 % Operating Frequency Ramp Amplitude (2) Maximum Duty Cycle Minimum On-Time 400 FS (2) (2) DH Rising/Falling Time DL Rising/Falling Time 525 kHz Vm 0.8 V DMAX 97 % TON_MIN 125 ns tSRC_DH tSINK_DH tSRC_DL tSINK_DL 6V Swing at CL = 3.3nF VBST-VPN = 8.2V 6V Swing at CL = 3.3nF VDRV = 8.2V DH, DL Nonoverlapping Time TA = 25°C, VCC = 12V Soft Start Time 450 41 27 29 42 ns ns 30 ns 1.5 ms Voltage Error Amplifier Input Offset Voltage (2) 2 mV Input Offset Current (2) 40 nA Open Loop Gain (2) 80 dB Unity Gain Bandwidth (2) 10 MHz Output Source Current 0.9 mA Output Sink Current 0.9 mA 1.2 V/us Slew Rate (2) For CL=500pF Load Notes: (1) This device is ESD sensitive. Use of standard ESD handling precautions is required. (2) Guaranteed by design, not tested in production. 2007 Semtech Corp. 3 www.semtech.com SC2621A POWER MANAGEMENT Pin Configuration Ordering Information SOIC-14 TOP VIEW BST 1 14 DH OCS 2 13 PN COMP 3 12 GND FB 4 11 DL LDOG 5 10 DRV LDFB 6 9 NC GND 7 8 VCC Part Numbers P ackag e SC2621ASTRT(1)(2) SO-14 S C 2621A E V B Note: (1) Only available in tape and reel packaging. A reel contains 2500 devices. (2). Lead free products. This product is fully WEEE and RoHS compliant. Pin Descriptions SO-14 Pin N ame 1 BST Boost i nput for top gate dri ve bi as. 2 OC S C urrent li mi t setti ng. C onnect a resi stor from thi s pi n to ground to program the tri p poi nt of load current. 3 C OMP 4 FB 5 LD OG External LD O gate dri ve. C onnect thi s pi n to the external N-MOSFET gate. 6 LD F B External LD O feed back. C onnect thi s pi n to the li near regulator output. 7 GND C hi p ground. 8 VC C C hi p i nput power supply. 9 NC 10 D RV 11 DL 12 GND 13 PN Phase node. C onnect thi s pi n to bottom N-MOSFET drai n. 14 DH Gate dri ve for top MOSFET. 2007 Semtech Corp. Pin Function Error ampli fi er output for compensati on. Voltage feed back of sychronous buck converter. No connecti on. Internal LD O output. C onnect a 1uF cerami c capasi tor from thi s pi n to ground for decoupli ng. Thi s voltage i s used for chi p bi as, i ncludi ng gate dri vers. Gate dri ve for bottom MOSFET. C hi p ground. 4 www.semtech.com SC2621A POWER MANAGEMENT Block Diagram 8.2V 2007 Semtech Corp. 5 www.semtech.com SC2621A POWER MANAGEMENT Applications Information shutdown both outputs. After waiting for around 5 milliseconds, the SC2621A begins to charge SS capacitor again and initiates a fresh startup. The startup and shutdown cycle will repeat until the short circuit is removed. This is called a hiccup mode short circuit protection. THEOR Y OF OPERA TION THEORY OPERATION The SC2621A integrates a high-speed, voltage mode PWM controller with a linear controller into a single package. It is designed to control two independent output voltages for high performance graphic card applications. To program a load trip point for short circuit protection, it is recommended to connect a 3.3k resistor from the OCS pin to the ground, and a resistor Rset from the OCS pin to the DRV pin, as shown in Fig. 1. As shown in the block diagram of the SC2621A, the voltage-mode PWM controller consists of an error amplifier, a 450kHz ramp generator, a PWM comparator, a RS latch circuit, and two MOSFET drivers. The buck converter output voltage is fed back to the error amplifier negative input and is regulated to a reference voltage level. The error amplifier output is compared with the ramp to generate a PWM wave, which is amplified and used to drive the MOSFETs in the buck converter. The PWM wave at the phase node with the amplitude of Vin is filtered out to get a DC output. The linear controller is an error amplifier. It provides the gate drive and output voltage control for a linear regulator. Both PWM controller and linear controller work with soft-start and fault monitoring circuitry to meet application requirement. 12V 8 10 DRV SC2621A Rset 2 OCS 3.3k GND 12 UVLO, Start-up and Shutdown To initiate the SC2621A, a supply voltage is applied to Vcc pin. The top gate (DH) and bottom gate (DL) are held low until Vcc voltage exceed UVLO (Under Voltage Lock Out) threshold, typically 4.0V. Then the internal Soft-Start (SS) capacitor begins to charge, the top gate remains low, and the bottom gate is pulled high to turn on the bottom MOSFET. When the SS voltage at the capacitor reaches 0.4V, the linear controller is enabled and the LDO output is turned on. Meanwhile, the top and bottom gates of PWM controller begin to switch. The switching regulator output is slowly ramping up for a soft turn-on. Fig. 1. Programming load trip point 350 325 Vpn (mV) 300 275 250 225 200 If the supply voltages at Vcc pin falls below UVLO threshold during a normal operation, the SS capacitor begins to discharge. When the SS voltage reaches 0.4V, the PWM controller controls the switching regulator output to ramp down slowly for a soft turn-off. Meanwhile, the linear controller is disabled and LDO output is turned off. 175 150 0 100 200 300 400 500 600 Rset (k -ohm) Fig. 2. Pull up resistor (Rset) vs. trip voltage Vpn The resistor Rset can be found in Fig. 2 for a given phase node voltage Vpn at the load trip point. This voltage is the product of the inductor peak current at the load trip point and the Rdson of the low-side MOSFET: Hiccup Mode Short Circuit Protection The SC2621A uses low-side MOSFET Rdson sensing for over current protection. In every switching cycle, after the bottom MOSFET is on for 150ns, the SC2621A detects the phase node voltage and compares it with an internal setting voltage. If the phase node is lower than the setting voltage, an overcurrent condition occurs. The SC2621A will discharge the internal SS capacitor and 2007 Semtech Corp. V CC V pn = I peak ´ Rds _ on The soft start time of the SC2621A is fixed at around 6 www.semtech.com SC2621A POWER MANAGEMENT Applications Information (Cont.) There is no significant switching loss for the bottom MOSFET because of its zero voltage switching. The conduction losses of the top and bottom MOSFETs are given by: 1.5ms. Therefore, the maximum soft start current is determined by the output inductance and output capacitance. The values of output inductor and output bulk capacitors have to be properly selected so that the soft start peak current does not exceed the load trip point of the short circuit protection. Internal LDO for Gate Drive An internal LDO is designed in the SC2621A to lower the 12V supply voltage for gate drive. An 1uF external ceramic capacitor connected in between DRV pin to the ground is needed to support the LDO. The LDO output is connected to low gate drive internally, and has to be connected to high gate drive through an external bootstrap circuit. The LDO output voltage is set at 8.2V. The manufacture data and bench tested results show that, for low Rdson MOSFETs run at applied load current, the optimum gate drive voltage is around 8.2V, where the total power losses of power MOSFETs are minimized. COMPONENT SELECTION PC _ TOP = I O2 × Rdson × D PC _ BOT = I O2 × Rdson × (1 - D ) If the requirement of total power losses for each MOSFET is given, the above equations can be used to calculate the values of Rdson and gate charge can be calculated using above equations, then the devices can be determined accordingly. The solution should ensure the MOSFET is within its maximum junction temperature at highest ambient temperature. Output Capacitor The output capacitors should be selected to meet both output ripple and transient response criteria. The output capacitor ESR causes output ripple VRIPPLE during the inductor ripple current flowing in. To meet output ripple criteria, the ESR value should be: General design guideline of switching power supplies can be applied to the component selection for the SC2621A. RESR < Induct or and MOSFET Inductor MOSFETss The selection of inductor and MOSFETs should meet thermal requirement because they are power loss dominant components. Pick an inductor with as high inductance as possible without adding extra cost and size. The higher inductance, the lower ripple current, the smaller core loss and the higher efficiency will be. However, too high inductance slows down output transient response. It is recommended to choose the inductance that gives the inductor ripple current to be approximate 20% of maximum load current. So choose inductor value from: L= L × f OSC × VRIPPLE V VO × (1 - O ) VIN The output capacitor ESR also causes output voltage transient VT during a transient load current IT flowing in. To meet output transient criteria, the ESR value should be: RESR < VT IT To meet both criteria, the smaller one of above two ESRs is required. The output capacitor value also contributes to load transient response. Based on a worst case where the inductor energy 100% dumps to the output capacitor during the load transient, the capacitance then can be calculated by: V 5 × VO × (1 - O ) I O × f osc VIN The MOSFETs are selected from their Rdson, gate charge, and package. The SC2621A provides 1.5A gate drive current. To drive a 50nC gate charge MOSFET gives 50nC/ 1.5A=33ns switching time. The switching time ts contributes to the top MOSFET switching loss: C > L× I T2 VT2 PS = I O ×VIN × t S × f OSC 2007 Semtech Corp. 7 www.semtech.com SC2621A POWER MANAGEMENT Applications Information (Cont.) switching frequency. The transfer function of the model Input Capacitor The input capacitor should be chosen to handle the RMS ripple current of a synchronous buck converter. This value is given by: is given by: VO VIN 1 + sRESRC = × VC Vm 1 + sL / R + s 2 LC 2 I RMS = (1 - D ) × I IN + D × ( I o - I IN )2 where VIN is the power rail voltage, Vm is the amplitude of the 500kHz ramp, and R is the equivalent load. where Io is the load current, IIN is the input average current, and D is the duty cycle. Choosing low ESR input capacitors will help maximize ripple rating for a given size. MOSFET for Linear Regulator The MOSFET in linear regulator operates in linear region with really high power loss. A device with a suitable package has to be selected to handle the loss. To prevent too high load current during short circuit, the Rdson of the MOSFET should not be selected too low. A good choice is to select a MOSFET so that it is almost fully turned on at maximum load current. For example, in a LDO design with 3.3V in and 1.5V/2A out, a MOSFET with 600 to 800mohm Rdson can be chosen. SC2621A AND MOSFET S REF PWM MODULAT OR Vc - L Vo OUT COMP Zf Zs Bootstrap Circuit The SC2621A uses an external bootstrap circuit to provide a voltage at BST pin for the top MOSFET drive. This voltage, referring to the Phase Node, is held up by a bootstrap capacitor. Typically, it is recommended to use a 1uF ceramic capacitor with 16V rating and a commonly available diode IN4148 for the bootstrap circuit. Co Resr Fig. 3. Block diagram of the control loop The model is a second order system with a finite DC gain, a complex pole pair at Fo, and an ESR zero at Fz, as shown in Fig. 4. The locations of the poles and zero are determined by: Filters for Supply Power For each pin of DRV and Vcc, it is recommended to use a 1uF/16V ceramic capacitor for decoupling. In addition, place a small resistor (10 ohm) in between Vcc pin and the supply power for noise reduction. FO = CONTROL LOOP DESIGN FZ = The goal of compensation is to shape the frequency response charateristics of the buck converter to achieve a better DC accuracy and a faster transient response for the output voltage, while maintaining the loop stability. 1 LC 1 RESR C The compensator in Fig. 3 includes an error amplifier and impedance networks Zf and Zs. It is implemented by the circuit in Fig. 5. The compensator provides an integrator, double poles and double zeros. As shown in Fig. 4, the integrator is used to boost the gain at low frequency. Two zeros are introduced to compensate excessive phase lag at the loop gain crossover due to the integrator (-90deg) and complex pole pair (-180deg). Two high frequency poles are designed to compensate the ESR zero and attenuate high frequency noise. The block diagram in Fig. 3 represents the control loop of a buck converter designed with the SC2621A. The control loop consists of a compensator, a PWM modulator, and a LC filter. The LC filter and PWM modulator represent the small signal model of the buck converter operating at fixed 2007 Semtech Corp. + EA FB 8 www.semtech.com SC2621A POWER MANAGEMENT Applications Information (Cont.) (2). Select the open loop crossover frequency Fc located at 10% to 20% of the switching frequency. At Fc, find the required DC gain. 60 Fp1 Fp2 COM PENSATOR GAI N (3). Use the first compensator pole Fp1 to cancel the ESR zero Fz. 30 GAIN (dB) Fz1 LO OP GA IN Fz2 (4). Have the second compensator pole Fp2 at half the switching frequency to attenuate the switching ripple and high frequency noise. Fo 0 CO NV ER TE RG AI N Fz Fc -30 (5). Place the first compensator zero Fz1 at or below 50% of the power stage resonant frequency Fo. -60 100 1K 10K 100 K 1M FR EQ UENCY (Hz ) A MathCAD program is available upon request for the calculation of the compensation parameters. Fig. 4. Bode plots for control loop design C2 C1 LA YOUT GUIDELINES LAY R2 C3 R3 Vo 1 - Vc 2 3 + VREF Rtop Rbot 0.5V Fig. 5. Compensation network The top resistor Rtop of the voltage divider in Fig. 5 can be chosen from 1k to 5k. Then the bottom resistor Rbot is found from: Rbot = (6). Place the second compensator zero Fz2 at or below the power stage resonant frequency Fo. 0.5V × Rtop VO - 0.5V The switching regulator is a high di/dt power circuit. Its Printed Circuit Board (PCB) layout is critical. A good layout can achieve an optimum circuit performance while minimizing the component stress, resulting in better system reliability. During PCB layout, the SC2621A controller, MOSFETs, inductor, and power decoupling capacitors have to be considered as a unit. The following guidelines are typically recommended for using the SC2621A controller. (1). Place a 4.7uF to 10uF ceramic capacitor close to the drain of top MOSFET for the high frequency and high current decoupling. The loop formed by the capacitor, the top and bottom MOSFETs must be as small as possible. Keep the input bulk capacitors close to the drain of the top MOSFETs. (2). Place the SC2621A over a quiet ground plane to avoid pulsing current noise. Keep the ground return of the gate drive short. where 0.5V is the internal reference voltage of the SC2621A. (3). Connect bypass capacitors as close as possible to the decoupling pins (DRV and Vcc) to the ground pin GND. The trace length of the decoupling capasitor on DRV pin should be no more than 0.2” (5mm). The other components of the compensator can be calculated using following design procedure: (4). Locate the components of the bootstrap circuit close to the SC2621A. (1). Plot the converter gain, including LC filter and PWM modulator. 2007 Semtech Corp. 9 www.semtech.com SC2621A POWER MANAGEMENT Applications Information (Cont.) TTypical ypical Application Schematics ffor or PCI-Express with 12V In put Input 12V R1 2R2 C1 10uF Q1 3.3V R3 R4 3.3k 499k 0 Q2 SPD14N06 2 2.5V/2A 3 R11 8k C8 6 + 560uF 7 R12 2k C14 10nF 0 1uF R15 11.5k BST DH OCS PN GND FB 5 0 C5 COMP 4 1800uF IPD05N03 U1 1 + C4 DL LDOG DRV LDFB NC NC VCC 0 SC2621A C15 680pF 14 D1 D1N4148 13 1 L1 1.5V/15A 2 1.2uH 12 Q3 11 R9 1R0 IPD05N03 10 R10 14.7k 9 R6 301 C6 2.2nF + C7 1800uF C9 + C10 10uF 1800uF 8 C11 1uF C13 C12 2.2nF R13 7.32k 0 1uF 0 Bill of Materials (12V Input) Item Quantity Reference Part Vendor 1 1 C1 10uF/16V Vishay 2 1 C9 10uF/6.3V Vishay 3 1 C4 1800uF/16V Rubycon, MBZ 4 2 C7,C10 1800uF/6.3V Rubycon, MBZ 5 3 C5,C11,C13 1uF Vishay 6 1 C6 2.2nF Vishay 7 1 C8 560uF Sanyo 8 1 C12 2.2nF Vishay 9 1 C14 10nF Vishay 10 1 C15 680pF Vishay 11 1 D1 D1N4148 Any 12 1 L1 1.2uH Cooper Electr. Tech 13 2 Q3,Q1 IPD05N03 Infineon 14 1 Q2 SPD14N06 Infineon 15 1 R1 2R2 Vishay 16 1 R3 3.3k Vishay 17 1 R4 499k Vishay 18 1 R6 301 Vishay 19 1 R9 1R0 Vishay 20 1 R10 14.7k Vishay 21 1 R11 8k Vishay 22 1 R12 2k Vishay 23 1 R13 7.32k Vishay 24 1 R15 11.5k Vishay 25 1 U1 SC2621A SEMTECH 2007 Semtech Corp. 10 www.semtech.com SC2621A POWER MANAGEMENT Applications Information (Cont.) P er eristics (12V In put) erfformance Charact Characteristics Input) Start up Efficiency (%) vs Load Current 90 85 80 12V Input (5V/DIV) 75 1.5V Output (1V/DIV) 70 3.3V Input (2V/DIV) 65 2.5V Output (2V/DIV) 60 1 3 5 7 9 11 13 15 X=5ms/DIV Load Current (A) Transient Response Load Characteristics (Output vs Load Current) 1.6 1.4 1.5V Output Response (100mV/DIV) 1.2 1.0 0.8 0.6 0.4 0.2 Step Load Current (10A/DIV) 0.0 0 5 10 15 20 X=20us/DIV Load Current(A) Gate Waveforms (Io=15A) Short Circuit Protection Output Short DL (10V/DIV) 1.5V OUT (1V/DIV) DH (10V/DIV) PN (10V/DIV) Output Current (10A/DIV) X=5ms/DIV X=50ns/DIV 2007 Semtech Corp. 11 www.semtech.com SC2621A POWER MANAGEMENT Applications Information (Cont.) TTypical ypical Application Schematics with 25V In put Input Vin=25V R1 732 C1 10uF Q1 + C4 1800uF 5V R3 IRLR7821 R4 3.3k 0 Q2 SPD14N06 2 3 R11 11.3k 6 + 7 R12 2k C14 4.7nF BST DH OCS PN GND FB 5 C8 0 1uF COMP 4 DL LDOG DRV LDFB NC NC VCC 14 D1 D1N4148 13 1 L1 5V /10A 2 2.2uH 12 Q3 11 10 R9 1R0 R10 22k R6 301 C6 2.2nF IRLR7821 C9 10uF + C10 1800uF 9 8 SC2621A C11 1uF C12 2.2nF R13 2.43k 0 C13 1uF 0 C15 1nF R15 22k 0 C5 U1 1 3.3V/1A 560uF 499k D2 0 BZX84B16LT1 0 Note: Zener diode D2 is required when Vin is 18V or higher. Bill of Materials (25V Input) Item Quantity Reference Part Vendor 1 2 1 C1 10uF/35V Murata 1 C9 10uF/6.3V Vishay 3 1 4 1 C4 1500uF/35V Rubycon C10 1500uF/6.3V Rubycon, MBZ 5 3 6 1 C5,C11,C13 1uF Vishay C6,C12 2.2nF Vishay 7 1 C8 560uF Sanyo 8 1 C14 4.7nF Vishay 9 1 C15 1nF Vishay 10 1 D1 D1N4148 Any 11 1 D2 BZX84B16LT1 ON Semi 12 1 L1 2.2uH Cooper Electr. Tech 13 2 Q3,Q1 IRLR7821 IR 14 1 Q2 SPD14N06 Infineon 15 1 R1 732 Vishay 16 1 R3 3.3k Vishay 17 1 R4 499k Vishay 18 1 R6 301 Vishay 19 1 R9 1R0 Vishay 20 1 R10,R15 22k Vishay 21 1 R11 11.3k Vishay 22 1 R12 2k Vishay 23 1 R13 2.43k Vishay 24 1 U1 SC2621A 2007 Semtech Corp. SEMTECH 12 www.semtech.com SC2621A POWER MANAGEMENT Applications Information (Cont.) P er eristics (25V In put) erfformance Charact Characteristics Input) Start up Efficiency (%) vs Load Current 92 90 88 86 25V Input (10V/DIV) 84 82 5V Output (2V/DIV) 80 78 3.3V Output (1V/DIV) 76 1 2 3 4 5 6 7 8 9 10 X=5ms/DIV Load Current (A) Gate Waveforms (Io=10A) Transient Response 5V Output Response (200mV/DIV) DL (10V/DIV) DH (10V/DIV) PN (10V/DIV) Step Load Current (10A/DIV) X=100ns/DIV 2007 Semtech Corp. X=20us/DIV 13 www.semtech.com SC2621A POWER MANAGEMENT Outline Drawing - SO-14 A D e N DIM A A1 A2 b c D E1 E e h L L1 N 01 aaa bbb ccc E/2 2X E1 ccc C 1 2X N/2 TIPS 2 E 3 B D DIMENSIONS INCHES MILLIMETERS MIN NOM MAX MIN NOM MAX .053 .069 .004 .010 .049 .065 .012 .020 .007 .010 .337 .341 .344 .150 .154 .157 .236 BSC .050 BSC .010 .020 .016 .028 .041 (.041) 14 0° 8° .004 .010 .008 1.35 1.75 0.10 0.25 1.25 1.65 0.31 0.51 0.17 0.25 8.55 8.65 8.75 3.80 3.90 4.00 6.00 BSC 1.27 BSC 0.25 0.50 0.40 0.72 1.04 (1.04) 14 0° 8° 0.10 0.25 0.20 aaa C h A2 A SEATING PLANE C bxN bbb A1 h H C A-B D c GAGE PLANE 0.25 SIDE VIEW SEE DETAIL L (L1) A DETAIL 01 A NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -H- 3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. 4. REFERENCE JEDEC STD MS-012, VARIATION AB. Land Pattern - SO-14 X DIM (C) G C G P X Y Z Z Y DIMENSIONS INCHES MILLIMETERS (.205) .118 .050 .024 .087 .291 (5.20) 3.00 1.27 0.60 2.20 7.40 P NOTES: 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. 2. REFERENCE IPC-SM-782A, RLP NO. 302A. Contact Information Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804 2007 Semtech Corp. 14 www.semtech.com