SC905 CDMA Cellular Phone Power Management IC POWER MANAGEMENT Description Features The SC905 is a power management integrated circuit (PMIC) designed for the latest CDMA chip sets. The device provides four general purpose low dropout regulators (LDOs), and five low noise LDOs designed for analog circuits. The VMOT LDO can be used as a general purpose regulator or as an adjustable motor drive output that can supply up to 150mA to drive a vibrator motor. 9 LDO Linear Regulators CORE: 1.35V - 2.90V @ 300mA ANA: 2.55V - 2.90V @ 200mA PAD: 1.35V - 2.90V @ 300mA RX: 2.55V - 2.90V @ 150mA TX: 2.55V - 2.90V @ 150mA TCXO: 2.55V - 2.90V @ 80mA PLL: 2.55V - 2.90V @ 80mA Camera: 1.35V - 2.90V @ 100mA Motor Drive: 1.35V - 2.90V @ 150mA I2C Interface for Microprocessor Control Less than 1μA Quiescent Current in Shutdown 65dB PSRR for Analog LDOs Over-Temperature Protection Power-On Control Optional Interface for Controlling Semtech Battery Chargers Small 5mm x 5mm 32-Pin QFN Package Each LDOs enable and output voltage are controlled via the I2C bus. An optional three-wire interface compatible with Semtech battery charger ICs is also controlled via the I2C bus. Initial power-on is achieved by activating either the ON or the HFPWR signal, and the PGOOD input is used by the microprocessor to latch power on or disable the device. The small and thermally efficient MLPQ-32 package and use of ceramic bypass capacitors, minimize the required PCB area making the SC905 ideal for space-conscious portable applications. Applications CDMA Cellular Handsets Palmtop/Laptop Computers Battery Powered Equipment Typical Application Circuit VBAT SC905 Battery Charger Circuit VBAT IN1 IN2 IN3 IN4 IN5 IN6 ON DVIN HFPWR VCORE PGOOD VPAD SDA VANA SCL VTCXO PWRON VPLL RESB VTX VRX VMOT VCAM BP VPSEL VCSEL AGND DGND CPB CHRGB FAULTB ON/OFF Handsfree Option 0.1μF MOTOR 1μF 10μF TCXO + Synthesiser BATTERY PLL 1μF Transmitter Section PA 1μF 1μF 1μF Receiver Section 1μF Baseband Processor LNA 1μF Camera Module 1μF Audio Processing Keypad Digital Interface June 7, 2006 1 www.semtech.com SC905 POWER MANAGEMENT Absolute Maximum Ratings Exceeding the specifications below may result in permanent damage to the device or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. Parameter Symbol Maximum Units Input Supply Voltage VIN -0.3 to +7 V Digital Input Voltage VDIG -0.3 to VIN+0.3 V Operating Ambient Temperature Range TA -40 to +85 °C Operating Junction Temperature Range TJ -40 to +125 °C TLEAD 260 °C TSTG -60 to +150 °C θJA 26 °C/W ESD 2 kV Peak IR Reflow Temperature Storage Temperature Thermal Resistance Junction to Ambient (1) ESD Protection Level(2) (1) Calculated from package in still air, mounted to 3” x 4.5”, 4 layer FR4 PCB with thermal vias under the exposed pad as per JESD51 standards. (2) Tested according to JEDEC standard JESD22-A114-B. Electrical Characteristics Unless otherwise noted VIN = 3.7V, TA = -40 to +85°C. Typical values are at TA = +25°C. Parameter Symbol Condition Min Typ Max Units 5.5 V 1 μA General Supply Voltage VIN Shutdown Current ISD Quiescent Supply Current ISU Default Start-up Mode 300 ISTBY I C, VREF Active, All Outputs Disabled 30 CVCC At Each Power Input Pin 1 μF tSU CBP = 0.1μF 25 ms UVLO Descending, Hysteresis = 50mV 2.5 V OT Hysteresis = 20°C 160 °C Supply Bypass Capacitor Start-Up Time Under-Voltage Lockout Over-Temperature 2.7 ON = 0V, HFPWR = 0V, PGOOD = 0V 2 μA 60 μA Digital Inputs Digital Input Voltage(1) VIL 0.4 VIH Digital Input Current 1.25 IDIG Logic Level High or Low VOL ISINK = 1.2mA VOH ISOURCE = 0.5mA, VPAD ≥ 1.8V V V -0.2 0.2 μA 10 %VPAD Digital Outputs Digital Output Voltage(2) 2 90 98 %VPAD LDO Regulator (CORE) - 300mA Output Voltage Accuracy(3) Current Limit Default At Start-Up: ON © 2006 Semtech Corp. ∆VOUT 1.35V ≤ VOUT ≤ 2.90V, IOUT = 1mA, VOUT +0.35V ≤ VIN ≤ 5.5V -75 +75 mV 350 900 mA ILIM VCORE = 0V VOUT-HI VCSEL - High 1.80 V VOUT-LO VCSEL - Low 1.35 V 2 www.semtech.com SC905 POWER MANAGEMENT Electrical Characteristics (Cont.) Parameter Symbol Condition Min Typ Max Units LDO Regulator (CORE) - 300mA (Cont.) Line Regulation REGLINE IOUT = 1mA, VOUT +0.35V < VIN < 5.5V 2.5 12 mV Load Regulation REGLOAD 1mA < IOUT < 300mA -3 -30 mV Dropout Voltage VDO VOUT = 2.90V, IOUT = 300mA 300 350 mV PSRRCORE f = 10Hz - 1kHz, COUT = 1μF, IOUT = 50mA 50 ∆VOUT 1.35V ≤ VOUT ≤ 2.90V, IOUT =1mA, VOUT +0.35V ≤ VIN ≤ 5.5V -75 +75 mV ILIM VPAD = 0V 350 900 mA VOUT-HI VPSEL - High 2.60 V VOUT-LO VPSEL - Low 1.80 V Line Regulation REGLINE IOUT = 1mA, VOUT +0.35V < VIN < 5.5V 2.5 12 mV Load Regulation REGLOAD 1mA < IOUT < 300mA -3 -30 mV Dropout Voltage VDO VOUT = 2.90V, IOUT = 300mA 300 350 mV PSRRPAD f = 10Hz - 1kHz, COUT = 1μF, IOUT = 50mA 50 Power Supply Rejection Ratio dB LDO Regulator (PAD) - 300mA Output Voltage Accuracy(3) Current Limit Default at Start-up: ON Power Supply Rejection Ratio dB LDO Regulator (ANA) - 200mA Output Voltage Accuracy(4) Current Limit Default At Start-up: ON ∆VOUT ILIM 2.55V ≤ VOUT ≤ 2.90V, IOUT = 1mA, VOUT +0.35V ≤ VIN ≤ 5.5V -75 +75 mV VANA = 0V 250 650 mA VOUT 2.60 V Line Regulation REGLINE IOUT = 1mA, VOUT +0.35V < VIN < 5.5V 2.5 12 mV Load Regulation REGLOAD 1mA < IOUT < 200mA -3 -20 mV VOUT = 2.90V, IOUT = 200mA 200 250 mV Dropout Voltage Power Supply Rejection Ratio Output Voltage Noise VDO PSRRANA en f = 10Hz - 1kHz, COUT = 1μF, IOUT = 50mA f = 10Hz to 100kHz, IOUT = 50mA, CBP = 0.1μF, COUT = 1μF 65 dB 45 μVRMS LDO Regulator (TCXO) - 80mA Output Voltage Accuracy(4) Current Limit Default At Start-up: ON Line Regulation Load Regulation Dropout Voltage Power Supply Rejection Ratio © 2006 Semtech Corp. ∆VOUT 2.55V ≤ VOUT ≤ 2.90V, IOUT = 1mA, VOUT +0.35V ≤ VIN ≤ 5.5V -75 +75 mV ILIM VTCXO = 0V 250 650 mA VOUT REGLINE 2.85 V IOUT = 1mA, VOUT +0.35V < VIN < 5.5V 2.5 12 mV 1mA < IOUT < 80mA -3 -20 mV VDO VOUT = 2.90V, IOUT = 80mA 200 250 mV PSRRTCXO f = 10Hz - 1kHz, COUT = 1μF, IOUT = 50mA 65 REGLOAD 3 dB www.semtech.com SC905 POWER MANAGEMENT Electrical Characteristics (Cont.) Parameter Symbol Condition Min Typ Max Units LDO Regulator (TCXO) - 80mA (Cont.) Output Voltage Noise μVRMS en f = 10Hz - 100kHz, IOUT = 50mA, CBP = 0.1μF, COUT = 1μF ∆VOUT 2.55V ≤ VOUT ≤ 2.90V, IOUT = 1mA, VOUT +0.35V ≤ VIN ≤ 5.5V -75 +75 mV ILIM VTX = 0V 250 650 mA 45 LDO Regulator (TX) - 150mA Output Voltage Accuracy(4) Current Limit Default At Start-up: OFF VOUT Line Regulation REGLINE Load Regulation REGLOAD Dropout Voltage Power Supply Rejection Ratio Output Voltage Noise 2.85 2.5 12 mV 1mA < IOUT < 150mA -3 -20 mV VDO VOUT = 2.90V, IOUT = 150mA 200 250 mV PSRRTX f = 10Hz - 1kHz, COUT = 1μF, IOUT = 50mA 65 dB 45 μVRMS en IOUT = 1mA, VOUT +0.35V < VIN < 5.5V V f = 10Hz - 100kHz, IOUT = 50mA, CBP = 0.1μF, COUT = 1μF LDO Regulator (RX) - 150mA Output Voltage Accuracy(4) Current Limit Default At Start-up: OFF ∆VOUT 2.55V ≤ VOUT ≤ 2.90V, IOUT = 1mA, VOUT +0.35V ≤ VIN ≤ 5.5V -75 +75 mV ILIM VRX = 0V 250 650 mA VOUT 2.85 V Line Regulation REGLINE IOUT = 1mA, VOUT+0.35V < VIN < 5.5V 2.5 12 mV Load Regulation REGLOAD 1mA < IOUT < 150mA -3 -20 mV Dropout Voltage VDO VOUT = 2.90V, IOUT = 150mA 200 250 mV PSRRRX f = 10Hz - 1kHz, COUT = 1μF, IOUT = 50mA 65 dB en f = 10Hz - 100kHz, IOUT = 50mA, CBP= 0.1μF, COUT = 1μF 45 μVRMS ∆VOUT 1.35V ≤ VOUT ≤ 2.90V, IOUT = 1mA VOUT +0.35V ≤ VIN ≤ 5.5V -75 +75 mV ILIM VCAM = 0V 250 650 mA Power Supply Rejection Ratio Output Voltage Noise LDO Regulator (CAM) - 100mA Output Voltage Accuracy(3) Current Limit Default At Start-up: OFF VOUT Line Regulation REGLINE Load Regulation REGLOAD Dropout Voltage Power Supply Rejection Ratio © 2006 Semtech Corp. 1.80 IOUT = 1mA, VOUT +0.35V < VIN < 5.5V V 2.5 12 mV 1mA < IOUT < 100mA -3 -20 mV VDO VOUT = 2.90V, IOUT = 100mA 200 250 mV PSRRCAM f = 10Hz - 1kHz, COUT = 1μF, IOUT = 50mA 50 4 dB www.semtech.com SC905 POWER MANAGEMENT Electrical Characteristics (Cont.) Parameter Symbol Condition Min ∆VOUT 2.55V ≤ VOUT ≤ 2.90V, IOUT = 1mA, VOUT +0.35V ≤ VIN ≤ 5.5V ILIM VPLL = 0V Typ Max Units -75 +75 mV 250 650 mA LDO Regulator (PLL) - 80mA Output Voltage Accuracy(4) Current Limit Default At Start Up: OFF VOUT 2.85 V Line Regulation REGLINE IOUT = 1mA, VOUT +0.35V < VIN < 5.5V 2.5 12 mV Load Regulation REGLOAD 1mA < IOUT < 80mA -3 -20 mV Dropout Voltage VDO VOUT = 2.90V, IOUT = 80mA 200 250 mV PSRRPLL f = 10Hz - 1kHz, COUT = 1μF, IOUT = 50mA 65 dB 45 μVRMS Power Supply Rejection Ratio Output Voltage Noise en f = 10Hz - 100kHz, I OUT = 50mA, CBP= 0.1μF, COUT = 1μF LDO Regulator (MOT) - 150mA Output Voltage Accuracy(3) Current Limit Default at Start Up: OFF Line Regulation Load Regulation Dropout Voltage Power Supply Rejection Ratio © 2006 Semtech Corp. ∆VOUT 1.35V ≤ VOUT ≤ 2.90V, IOUT = 1mA, VOUT +0.35V ≤ VIN ≤ 5.5V -75 +75 mV ILIM VMOT = 0V 250 650 mA VOUT REGLINE 1.40 V IOUT = 1mA, VOUT +0.35V < VIN < 5.5V 2.5 12 mV 1mA < IOUT < 150mA -3 -20 mV VDO VOUT = 2.90V, IOUT = 150mA 200 250 mV PSRRMOT f = 10Hz - 1kHz, COUT = 1μF, IOUT = 50mA 50 REGLOAD 5 dB www.semtech.com SC905 POWER MANAGEMENT Electrical Characteristics (Cont.) Parameter Symbol Condition Min Typ Max Units I2C Interface(5) Interface complies with slave mode I2C interface as described by Philips I2C specification version 2.1 dated January, 2000. VIL Digital Input Voltage 0.4 VIH 1.25 SDA Output Low Level Digital Input Current V IDIN (SDA) ≤ 3mA IDG V -0.2 0.4 V 0.2 μA VHYS 0.1 V Maximum Glitch Pulse Rejection tSP 50 ns I/O Pin Capacitance CIN 10 pF Clock Frequency fSCL 400 SCL Low Period tLOW 1.3 μs SCL High Period tHIGH 0.6 μs Data Hold Time tHD_DAT 0 μs Data Setup Time tSU_DAT 100 ns Setup Time for Repeated START Condition tSU_STA 0.6 μs Hold Time for Repeated START Condition tHD_STA 0.6 μs Setup Time for STOP Condition tSU_STO 0.6 μs Bus-Free Time Between STOP and START tBUF 1.3 μs RESET Timeout Delay tRD 75 Hysteresis of Schmitt Trigger Inputs I2C Timing(5) Power-up Delay Between CORE, ANA, PAD, TXCO tDELAY Maximum Glitch Pulse Rejection tSP Interface Start-up Time tEN Delay Between Each Output Activating Bus Start-up Time After EN Pin is Pulled High 100 440 125 kHz ms 100 μs 50 ns 350 μs Notes: (1) Applies to pin names, CPB, CHRGB, FAULTB, ON, HFPWR, PGOOD, VCSEL, VPSEL. (2) Applies to pin names, PWRON, RESB. (3) For VOUT settings see Table A. (4) For VOUT settings see Table B. (5) Guaranteed by design. © 2006 Semtech Corp. 6 www.semtech.com SC905 POWER MANAGEMENT Pin Configuration IN2 1 VCORE 2 VMOT IN3 VCAM IN4 VANA VRX IN5 VTCXO Ordering information 32 31 30 29 28 27 26 25 TOP VIEW 24 VTX 23 IN6 22 VPLL IN1 3 VPAD 4 21 AGND ON 5 20 VBAT HFPWR 6 19 BP SDA 7 18 PGOOD SCL 8 17 RESB 11 12 13 14 15 16 DVIN CHRGB CPB FAULTB VPSEL PACKAGE SC905MLTRT(1) MLP 5x5 32L(2) SC905EVB Evaluation Board Notes: (1) Available in tape and reel only. A reel contains 3,000 devices. (2) Available in lead-free package only. Device is WEEE and RoHS compliant. PWRON 10 VCSEL 9 DGND T DEVICE MLPQ32: 5X5 32 Lead © 2006 Semtech Corp. 7 www.semtech.com SC905 POWER MANAGEMENT Pin Descriptions Pin # Pin Name I/O Pin Function 1 IN2 Input 2 VCORE Output 3 IN1 Input 4 VPAD Output 5 ON Input 6 HFPWR Input 7 SDA 8 SCL 9 DGND - 10 DVIN Input Main digital input voltage terminal. Input voltage terminal to VCORE LDO. 300mA LDO output for MSM core processor supply. Input voltage terminal to VPAD LDO. 300mA LDO PAD output to MSM I/O circuits. Active high power on/off key. When the push button is closed it is shorted to battery. Power on input from accessory, active high. Input/Output Bi-directional open drain digital I/O. I2C serial data. Input Digital input. I2C serial clock. Digital ground. 11 CHRGB Input Logic input. State is recorded in bit 1 of the status register. 12 CPB Input Logic input. State is recorded in bit 0 of the status register. 13 FAULTB Input Logic input. State is recorded in bit 2 of the status register. 14 VPSEL Input Default control for VPAD LDO supply. Ground for 1.80V default, tie high for 2.60V. 15 VCSEL Input Default control for VCORE LDO supply. Ground for 1.35V default, tie high for 1.80V. 16 PWRON Output Logic OR output of ON, HFPWR and PGOOD. Active high. 17 RESB Output 18 PGOOD Input Reset output. Active low. Logic input signal from MSM to indicate power is good, latches the SC905 on. Low disables the SC905. 19 BP Output 20 VBAT Input 21 AGND - 22 VPLL Output 23 IN6 Input 24 VTX Output LDO output for transmitter power. 25 VTCXO Output LDO output for TCXO power. 26 IN5 Input 27 VRX Output LDO output for receiver power. 28 VANA Output LDO output for analog power. 29 IN4 Input 30 VCAM Output 31 IN3 Input 32 VMOT Output T Thermal Pad - © 2006 Semtech Corp. LDO bypass output. Bypass with a 0.1μF capacitor. Main battery supply input terminal. Analog ground pin. LDO output for PLL power. Input voltage terminal for VPLL & VTX LDOs. Input voltage terminal for VTCXO & VRX LDOs. Input voltage terminal to VANA LDO. LDO output for camera power. Input voltage terminal to VCAM & VMOT LDOs. LDO output voltage for vibrator motor power. Can also be a general purpose output. Pad for heatsinking purposes. Connect to ground plane using multiple vias. Not connected internally. 8 www.semtech.com SC905 POWER MANAGEMENT Block Diagram ON 5 HFPWR 6 PGOOD 18 VREF PWRON logic 19 BP 3 IN1 4 VPAD 1 IN2 2 VCORE 31 IN3 CAM 30 VCAM MOT 32 VMOT 29 IN4 28 VANA 26 IN5 TCXO 25 VTCXO RX 27 VRX 23 IN6 PLL 22 VPLL TX 24 VTX UVLO OT VPAD PWRON 16 VPAD RESB RESET 17 EN PAD EN EN REG EN CTRL EN CHRGB 11 FAULTB 13 CPB 12 VPSEL 14 VCSEL 15 CORE EN EN I2C Interface I2C Registers & Controls EN ANA EN SDA 7 SCL 8 EN VBAT 20 DVIN 10 DGND 9 AGND 21 © 2006 Semtech Corp. EN EN 9 www.semtech.com SC905 POWER MANAGEMENT Applications Information General Description The SC905 includes 9 low dropout (LDO) voltage regulators to provide complete power regulation capability for CDMA handsets or other portable electronic equipment. Therefore, if the ON pin transitions high when the PGOOD signal is high, the LDOs and RESB signal will remain in their state until the microprocessor pulls the PGOOD signal low. Once the PGOOD signal is low, all the LDOs immediately power off and all the logic resets to the shutdown condition. The SC905 can be indirectly powered off by using the I2C command to turn off the core supply. This will result in a loss of power to the MSM causing PGOOD to go low, thus disabling the SC905. Five of the LDOs are designed to be used with analog circuitry such as audio, radio frequency, or oscillator circuits. These devices have very low noise levels and high power supply rejection. The output voltage range for these LDOs is 2.55V to 2.9V in 50mV steps. The outputs for these LDOs are VANA, VTCXO, VPLL, VTX, and VRX. The HFPWR pin operates identically to the ON pin. This pin provides a second source for activating power so that remote devices such as battery chargers or system connector pins can be used to enable the device. Three other LDOs are general purpose regulators designed to be used with digital circuits. The noise requirements for these LDOs are relaxed, but their voltage range is expanded to cover the wide range of voltages needed for different types of functions. The outputs for these LDOs are VCORE, VPAD, and VCAM. LDO Programmable Output Voltage The output voltage of each LDO regulator is programmable. Each LDO has a program voltage register that can be accessed through the I2C interface and the output voltage adjusted as necessary. (See the Tables on page 14 and 15 for more information.) The VMOT output is specifically designed to drive a vibrator motor. This output can supply up to 150mA with voltage settings from 1.35V to 2.9V, allowing designers the flexibility to select the output voltage that provides maximum vibration. When not used in conjunction with a vibrator, this output can be used as a general purpose digital regulator. ON/OFF Control Register Each individual LDO may be turned on or off by accessing the ON/OFF control register. LDOs are turned on by setting their respective on/off bits to 1 and disabled by setting the on/off bits to 0. This allows for on/off control with a single write command. Power-On Control The SC905 is activated when the ON pin is pulled high, provided that the input voltage is within the specified operating range. The ON pin responds to logic-high edge triggering to power up the handset. The rising edge ON signal is latched when the CORE, PAD, ANA, and TCXO LDOs are turned on and PGOOD goes high. When the PAD LDO output voltage reaches 77% of its regulation point, the reset timer starts and the RESB signal transitions high after delay of typically 100ms. After a successful power up sequence, any subsequent condition that toggles RESB (e.g. VPAD short-circuit, over-temperature, under voltage lockout, I2C disable of VPAD) will see a delay in the RESB transition back to high of typically 250ms. The microprocessor then raises PGOOD high to keep the SC905 powered on. There is no time limit for the MSM to activate PGOOD. If the MSM fails to raise PGOOD before the ON switch is released, the SC905 will transition back into standby mode. When an on/off bit is toggled, the registered data is maintained. However, all programmed information will be lost when the PGOOD input goes low. VCSEL & VPSEL Pin The VCSEL & VPSEL pins set the default voltage of CORE and PAD LDOs respectively. When the VCSEL pin is set to VIN the default voltage for the CORE LDO is 1.80V. When this pin is set to GND the default voltage for the CORE LDO is 1.35V. Likewise, when the VPSEL pin is set to VIN the default voltage for the PAD LDO is 2.60V. When this pin is set to GND, the default voltage for the PAD LDO is 1.80V. In both cases the VCSEL and VPSEL pins must be tied to GND or VIN prior to the device being powered on. This voltage cannot change “on the fly” by switching the pin voltage between VIN or GND once the device is on. Once the phone is powered on, the SC905 can only be directly powered off when the PGOOD signal goes low. © 2006 Semtech Corp. 10 www.semtech.com SC905 POWER MANAGEMENT Applications Information (Cont.) The voltage can be changed from its default state after start-up by writing to the appropriate voltage code register. correct register information to the SC905 to set it to the user state. 2) The MSM reads back all of the information to verify the data. Then it reads back the DSB again to ensure it is still set to 0. This verifies that no reset took place during the time that the multiple writes and read verifications happened. If the DSB has been reset to 1, this process needs to be repeated since the chip was reset sometime during the initialization. Once the MSM and the SC905 are synchronized, the DSB can be read back as a status check periodically, as needed. If it is ever set back to the default state, a new synchronization process is required. This handshake-style protocol makes sure that the MSM and SC905 are always synchronized. Active Shutdown The shutdown control bits determine how the on-chip active shutdown switches behave. Register 7 is the active shutdown control register and is used to control the shutdown behavior. Each LDO has a specific shutdown bit assigned to it. When the active shutdown bit is enabled (set to 1), the output capacitance on the LDO output is discharged by an on-chip FET when the LDO is disabled. When the active shutdown bit is disabled (set to 0), the output capacitance on the LDO output is discharged by the load. The default state for each LDO active shutdown bit is on. Default Status Bit In many multi-threaded environments it is necessary to maintain synchronization between the host micro-controller and the target IC. The SC905 has a default status bit (DSB) that will facilitate this task. The DSB can be useful in keeping the MSM and the SC905 synchronized. However, this is only useful if the MSM is powered by an external switching regulator such as the SC190. LDO Power-On Sequence When the SC905 first turns on, the four LDOs that default on are sequenced in the following fashion: CORE is the first to turn on, then PAD, then ANA and finally TCXO. During the power-on sequence, each LDO has a 100μs delay from one LDO turning on to the other. This process eliminates large voltage spikes across the battery supply during power-up. For further information on LDO power on sequencing, refer to the Timing Diagram on page 17. The DSB is bit 7 of register 0, and shares this register space with the PAD voltage control bits. The DSB is only set to 1 during power-up to indicate that the part is set to the default state. Moreover, the DSB cannot be written to a 1 through the I2C interface the way the other bits in this register can; it can only be cleared to 0 through the I2C interface. This feature prevents a software race condition by always writing to register 0 with bit 7 high when changing the PAD control voltage. To clear the bit simply write a 0 to bit 7. Protection Circuitry The SC905 contains protection circuitry that prevents the device from operating in an unspecified state. These include Under-voltage Lockout Protection, Over-temperature Protection and Short-circuit Protection. Under-Voltage Lockout The SC905 provides an under-voltage lockout (UVLO) circuit to protect the device from operating in an unknown state if the input voltage supply is too low. Applying the DSB Upon power-up, the SC905 LDOs and internal registers are set to their default state. The DSB is set to a 1 to indicate that the SC905 is in its default state. Upon reading this defaulted state condition, the MSM knows to perform whatever synchronization is needed to set the SC905 into a known user state. This user state is entered by a twostage process. When the battery voltage drops below the UVLO threshold, as defined in the Electrical Characteristics section, the LDOs are disabled and RESB is held low. When the battery voltage is increased above the hysteresis level, the LDOs are re-enabled into their previous states, provided PGOOD has remained high. If PGOOD goes low, the SC905 will shut down. When powering-up with a battery voltage below the UVLO threshold, RESB will be held low. 1) The MSM writes a 0 to the DSB indicating its desire to modify the state of the SC905. It then writes all of the © 2006 Semtech Corp. 11 www.semtech.com SC905 POWER MANAGEMENT Applications Information (Cont.) Over-Temperature Protection The SC905 provides an internal over-temperature (OT) protection circuit that monitors the internal junction temperature. When the temperature exceeds the OT threshold as defined in the Electrical Characteristics section, the OT protection disables all the LDO outputs, holds the RESB signal low and sets the OTF bit low in the status register. When the junction temperature drops below the hysteresis level, the OT protection resets the OTF bit high and re-enables all the LDOs in their previous states, provided PGOOD has remained high. If PGOOD goes low, the SC905 will shut down. This is only useful if the MSM is not powered by the SC905, since during an OT fault the MSM will lose power. An external switching regulator such as the SC190A could power the MSM in the case where monitoring the OTF bit is desired. The following table is a summary of the status register inputs and their functions: FUNCTION FAULTB is Low Charger Fault CPB is Low USB or AC Charger Present CHRGB is Low Charging in Progress CHRGB & FAULTB is Low Battery Fault Layout Considerations The PCB layout associated with the SC905 is straight forward, with the main consideration being given to the value and position of the input bypass capacitors. The device itself has eight input voltage pins which can be powered from a single supply or from a number of individual supplies depending on how much copper is available on the input voltage feed track and how much real estate is available on the PCB for components. If all the supply inputs are fed from one single supply trace or from a power plane, a 10μF low ESR capacitor or two 4.7μF low ESR capacitors should be used. Larger input capacitance and lower ESR provide better supply noise rejection and line transient response. The copper trace to the inputs should be fairly thick in order to keep trace inductance to a minimum and the capacitors should be located as close to the SC905 as possible. If the supply trace is thin then the inputs should be treated as if they were powered from individual supplies, each input should be bypassed by at least one 1μF low ESR capacitor located very close to each input pin. Short-Circuit Protection Each LDO output has short-circuit protection. If a short is applied to any output, the output voltage will drop and the output current will be limited to the short circuit current until the short is removed. Interfacing to Semtech Battery Chargers The SC905 is designed to interface with Semtech battery chargers by providing three control inputs that map the state of the controls to register bits so the host processor can monitor the charger’s status via the I2C interface. For open-drain control outputs from the charger, pull-up resistors must be connected to the lines for the SC905 registers to display the correct status. Status Register The status register monitors these inputs for changes, and the MSM can periodically poll this register to determine the status of the charger. This is a read-only register. This register is useful when the MSM needs to determine charging status before performing an LCD update. The SC905 is designed to have excellent stability with a minimum output capacitance of 1μF. Low ESR ceramic capacitors are recommended and should be located as close to the LDO output pins as possible. The MSM can control other aspects of the charger with general purpose I/O. These include enable/disable and charge time-out functions. Many of the chargers functions can be statically set and do not need MSM intervention. The amount of MSM intervention is determined by the intended application. © 2006 Semtech Corp. CONDITION 12 www.semtech.com SC905 POWER MANAGEMENT Register Map Register Name VPAD Register Address Bit 7 DSB 0 (1) 1 0 Default State User State Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 X X VPAD4 VPAD3 VPAD2 VPAD1 VPAD0 VCORE 1 X X X VCORE4 VCORE3 VCORE2 VCORE1 VCORE0 VMOT 2 VMOT_EN VMOT Active SHDN X VMOT4 VMOT3 VMOT2 VMOT1 VMOT0 1 0 1 0 ON OFF ON OFF VANA/VCAM 3 VANA2 VANA1 VANA0 VCAM4 VCAM3 VCAM2 VCAM1 VCAM0 VTCXO/VRX 4 X VRX2 VRX1 VRX0 X VTCXO2 VTCXO1 VTCXO0 VPLL/VTX 5 X VTX2 VTX1 VTX0 X VPLL2 VPLL1 VPLL0 ON/OFF CONTROL 6 VPAD_EN VCORE_EN VANA_EN VCAM_EN VTCXO_EN VPLL_EN VTX_EN VRX_EN 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ACTIVE(2) SHUTDOWN 7 VPAD Active SHDN VANA Active SHDN VCAM Active SHDN VTCXO Active SHDN VPLL Active SHDN VTX Active SHDN VRX Active SHDN 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF 8 STATUS (READ ONLY) VCORE Active SHDN X X X X CHRGB FAULTB OTF CPB 1 0 1 0 1 0 1 0 OK FAULT OK FAULT OFF ON OFF ON Defaults are indicated in BOLD. SC905 Slave Address: DEVICE ADDRESS 0 0 0 1 0 R/W 0 0 X Notes: (1) The default status bit (DSB) is set to 1 only when the SC905 is enabled by either the HFPWR pin or the ON pin being pulled high, and it cannot be set to one through the I2C interface. When changing the VPAD control voltage, always write to register 0 with bit seven high. Set bit seven low only when the DSB is to be cleared by the MSM. This will prevent any software race condition in a multi-tasking environment. See the applications section for more information on using the DSB. (2) The Active Shutdown defaults ON at power-up, but the registers maintain their settings as the LDOs are enabled and disabled during normal operation. © 2006 Semtech Corp. 13 www.semtech.com SC905 POWER MANAGEMENT Register Map (Cont.) Digital LDO Voltage Table A A 5-bit linear DAC controls the output voltage of each LDO. The DAC and error-amp gain are scaled so that the LSB size at the output is 50mV. Output voltage can be set by writing the proper code to the desired LDO register. See Table A for the bitcodes and their corresponding voltages. TABLE A - Output Voltage Code Bits for VCORE, VPAD, VMOT and VCAM © 2006 Semtech Corp. X4 X3 X2 X1 X0 LDO Output Voltage 0 0 0 0 0 1.35V 0 0 0 0 1 1.40V 0 0 0 1 0 1.45V 0 0 0 1 1 1.50V 0 0 1 0 0 1.55V 0 0 1 0 1 1.60V 0 0 1 1 0 1.65V 0 0 1 1 1 1.70V 0 1 0 0 0 1.75V 0 1 0 0 1 1.80V 0 1 0 1 0 1.85V 0 1 0 1 1 1.90V 0 1 1 0 0 1.95V 0 1 1 0 1 2.00V 0 1 1 1 0 2.05V 0 1 1 1 1 2.10V 1 0 0 0 0 2.15V 1 0 0 0 1 2.20V 1 0 0 1 0 2.25V 1 0 0 1 1 2.30V 1 0 1 0 0 2.35V 1 0 1 0 1 2.40V 1 0 1 1 0 2.45V 1 0 1 1 1 2.50V 1 1 0 0 0 2.55V 1 1 0 0 1 2.60V 1 1 0 1 0 2.65V 1 1 0 1 1 2.70V 1 1 1 0 0 2.75V 1 1 1 0 1 2.80V 1 1 1 1 0 2.85V 1 1 1 1 1 2.90V 14 www.semtech.com SC905 POWER MANAGEMENT Register Map (Cont.) Analog LDO Voltage Table B The bit code controls the output voltage of each LDO. The LSB size at the output is 50mV. Output voltage can be set by writing the proper code to the desired LDO register. See Table B for the bitcodes and their corresponding voltages. TABLE B - Output Voltage Code Bits for LDOs VANA, VTCXO, VTX, VRX, VPLL X2 X1 X0 LDO Output Voltage 0 0 0 2.55V 0 0 1 2.60V 0 1 0 2.65V 0 1 1 2.70V 1 0 0 2.75V 1 0 1 2.80V 1 1 0 2.85V 1 1 1 2.90V The I2C General Specification The SC905 is a read-write slave-mode I2C device and complies with the Philips I2C standard Version 2.1 dated January, 2000. The SC905 has eight user-accessible internal 8-bit registers. The I2C interface has been designed for program flexibility, in that once the slave address has been sent to the SC905 enabling it to be a slave transmitter/receiver, any register can be written or read independently of each other. While there is no auto increment/decrement capability in the SC905 I2C logic, a tight software loop can be designed to randomly access the next register independent of which register you begin accessing. The start and stop commands frame the data-packet and the repeat start condition is allowed if necessary. SC905 Limitations to the I2C specifications: Seven bit addressing is used and ten bit addressing is not allowed. Any general call address will be ignored by the SC905. The SC905 is not CBUS compatible. The SC905 can operate in standard mode (100kbit/s) or fast mode (400kbit/s). Supported Formats: Direct Format - Write The simplest format for an I2C write is given below. After the start condition [S], the slave address is sent, followed by an eighth bit indicating a write. The SC905 I2C then acknowledges that it is being addressed, and the master responds with an 8 bit data byte consisting of the register address. The slave acknowledges and the master sends the appropriate 8 bit data byte. Once again the slave acknowledges and the master terminates the transfer with the stop condition [P]. © 2006 Semtech Corp. 15 www.semtech.com SC905 POWER MANAGEMENT Using the I2C Serial Port I2C Direct Format - Write S Slave Address W A Register Address S: Start Condition W: Write = ‘0’ A: Acknowledge (sent by slave) P: Stop condition A Data A P Slave Address: 7 bit Register Address: 8 bit Data: 8 bit Combined Format - Read After the start condition [S], the slave address is sent, followed by an eighth bit indicating a write. The SC905 I2C then acknowledges that it is being addressed, and the master responds with an 8 bit data byte consisting of the register address. The slave acknowledges and the master sends the repeated start condition [Sr]. Once again, the slave address is sent, followed by an eighth bit indicating a read. The slave responds with an acknowledge and the previously addressed 8 bit data byte; the master then sends a non-acknowledge (NACK). Finally, the master terminates the transfer with the stop condition [P]. I2C Combined Format - Read S Slave Address W A Register Address S: Start Condition W: Write = ‘0’ R: Read = ‘1’ A: Acknowledge (sent by slave) NACK: Non-Acknowledge (sent by master) Sr: Repeated Start Condition P: Stop condition A Sr Slave Address R A Data NACK P Slave Address: 7 bit Register Address: 8 bit Data: 8 bit Stop Separated Reads Stop-separated reads can also be used. This format allows a master to set up the register address pointer for a read and return to that slave at a later time to read the data. In this format the slave address followed by a write command are sent after a start [S] condition. The SC905 then acknowledges it is being addressed, and the master responds with the 8-bit register address. The master sends a stop or restart condition and may then address another slave. After performing other tasks, the master can send a start or restart condition to the SC905 with a read command. The SC905 acknowledges this request and returns the data from the register location that had previously been set up. I2C Stop Separated Format - Read Register Address Setup Access Master Addresses other Slaves S Slave Address W A Register Address A P S Slave Address B S: Start Condition W: Write = ‘0’ R: Read = ‘1’ A: Acknowledge (sent by slave) NACK: Non-Acknowledge (sent by master) Sr: Repeated Start Condition P: Stop condition © 2006 Semtech Corp. Register Read Access S/Sr Slave Address A R A Data NACK P Slave Address: 7 bit Register Address: 8 bit Data: 8 bit 16 www.semtech.com SC905 POWER MANAGEMENT Timing Diagram Power On-Off Timing Diagram ON or HFPWR MSM DETERMINED DSB BP 25ms VCORE 25ms 77% 77% 100μs 77% 100μs VPAD 100μs 100μs VANA 100μs 100μs VTCXO 100ms 100ms RESB MSM DETERMINED PGOOD MSM DETERMINED PWRON © 2006 Semtech Corp. 17 www.semtech.com SC905 POWER MANAGEMENT Typical Characteristics Dropout Voltage vs. Load Current (Analog LDOs) Dropout Voltage vs. Load Current (Digital LDOs) 200 225 200 175 Dropout Voltage (mV) Dropout Voltage (mV) T = 85˚C 150 125 100 75 T = 25˚C 50 T = 85˚C 175 150 125 100 75 T = 25˚C 50 T = -40˚C 25 T = -40˚C 25 0 80 100 120 140 160 180 0 100 200 125 150 200 225 250 275 300 Load Current (mA) Load Current (mA) Load Regulation (Analog LDOs) VIN = 3.7V Load Regulation (Digital LDOs) VIN = 3.7V 0 0 T = 85˚C Output Voltage Variation (mV) Ouptut Voltage Variation (mV) 175 -3 -6 -9 -12 T = -40˚C -15 T = 85˚C -3 -6 T = -40˚C -9 T = 25˚C -12 T = 25˚C -18 -15 0 25 50 75 100 125 150 175 200 0 50 Load Current (mA) 150 200 250 300 Load Current (mA) Line Regulation (Analog LDOs) Load Current = 1mA Line Regulation (Digital LDOs) Load Current = 1mA 5 6 Output Voltage Variation (mV) Output Voltage Variation (mV) 100 4 T = 85˚C 3 T = 25˚C 2 1 5 T = 85˚C 4 T = 25˚C 3 2 1 T = -40˚C T = -40˚C 0 0 3 3.5 4 4.5 5 5.5 3 4 4.5 5 5.5 Input Voltage (V) Input Voltage (V) © 2006 Semtech Corp. 3.5 18 www.semtech.com SC905 POWER MANAGEMENT Typical Characteristics (Cont.) PSRR vs. Frequency (Digital LDOs) VOUT = 2.90V, VIN = 3.7V, Load Current = 50mA PSRR vs. Frequency (Analog LDOs) VOUT = 2.90V, VIN = 3.7V, Load Current = 50mA 0 Power Supply Rejection (dB) Power Supply Rejection (dB) 0 -10 -20 -30 -40 -50 -60 -70 -10 -20 -30 -40 -50 -60 -70 -80 -80 -90 10 100 1000 10 10000 100 Frequency (Hz) 45 1.4 40 0.6 VOUT = 1.35V 0.4 Output Noise (μV) 1.2 Maximum Recommended Input Voltage Maximum Output Current (A) 1.6 0.8 VOUT = 2.90V 10000 Output Noise vs. Load Current (Analog LDOs) VOUT = 2.90V, VIN = 3.7V Safe Operating Limits 1 1000 Frequency (Hz) T = 25˚C 35 30 25 T = -40˚C 20 T = 85˚C 15 10 0.2 5 0 0 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 5.9 0 Input Voltage (V) © 2006 Semtech Corp. 25 50 75 100 125 150 175 200 Load Current (mA) 19 www.semtech.com SC905 POWER MANAGEMENT Outline Drawing - MLPQ-32 5x5 Marking Information Top Marking yyww = Date Code (Example: 0552) xxxxx = Semtech Lot Number (Example: E90101-100) © 2006 Semtech Corp. 20 www.semtech.com SC905 POWER MANAGEMENT Land Pattern - MLPQ-32 5x5 Contact Information Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805) 498-2111 FAX (805)498-3804 © 2006 Semtech Corp. 21 www.semtech.com