FUJITSU SEMICONDUCTOR DATA SHEET DS05-20891-4E FLASH MEMORY CMOS 16 M (2 M × 8/1 M × 16) BIT Dual Operation MBM29DS163TE/BE10 ■ DESCRIPTION The MBM29DS163TE/BE is 16 M-bit, 1.8 V-only Flash memory organized as 2 M bytes of 8 bits each or 1 M words of 16 bits each. The device is offered in 48-pin TSOP (1) and 48-ball FBGA packages. This device is designed to be programmed in system with standard system 1.8 V VCC supply. 12.0 V VPP and 5.0 V VCC are not required for write or erase operations. The device can also be reprogrammed in standard EPROM programmers. (Continued) ■ PRODUCT LINE UP Part No. MBM29DS163TE/BE10 V VCC = 2.0 V +0.2 −0.2 V Power Supply Voltage (V) Max Address Access Time (ns) 100 Max CE Access Time (ns) 100 Max OE Access Time (ns) 35 ■ PACKAGES 48-pin plastic TSOP (1) 48-pin plastic TSOP (1) 48-ball plastic FBGA Marking Side (FPT-48P-M19) Marking Side (FPT-48P-M20) (BGA-48P-M11) MBM29DS163TE/BE10 (Continued) The device is organized into two banks, Bank 1 and Bank 2, which can be considered to be two separate memory arrays as far as certain operations are concerned. This device is the same as Fujitsu’s standard 1.8 V only Flash memories with the additional capability of allowing a normal non-delayed read access from a non-busy bank of the array while an embedded write (either a program or an erase) operation is simultaneously taking place on the other bank. The standard device offers access time 100 ns, allowing operation of high-speed microprocessors without wait state. To eliminate bus contention the device has separate chip enable (CE) , write enable (WE) , and output enable (OE) controls. The device is pin and command set compatible with JEDEC standard E2PROMs. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from 5.0 V and 12.0 V Flash or EPROM devices. The device is programmed by executing the program command sequence. This will invoke the Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. Typically, each sector can be programmed and verified in about 0.5 seconds. Erase is accomplished by executing the erase command sequence. This invokes the Embedded Erase Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. During erase, the device automatically times the erase pulse widths and verify proper cell margin. A sector is typically erased and verified in 1.0 second (if already completely preprogrammed) . The device also features a sector erase architecture. The sector mode allows each sector to be erased and reprogrammed without affecting other sectors. The device is erased when shipped from the factory. The device features single 1.8 V power supply operation for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. A low VCC detector automatically inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7, by the Toggle Bit feature on DQ6, or the RY/BY output pin. Once the end of a program or erase cycle is completed, the device internally resets to the read mode. The device also has a hardware RESET pin. When this pin is driven low, execution of any Embedded Program Algorithm or Embedded Erase Algorithm is terminated. The internal state machine is then reset to the read mode. The RESET pin may be tied to the system reset circuitry. Therefore, if a system reset occurs during the Embedded Program Algorithm or Embedded Erase Algorithm, the device is automatically reset to the read mode and will have erroneous data stored in the address locations being programmed or erased. These locations need re-writing after the Reset. Resetting the device enables the system’s microprocessor to read the boot-up firmware from the Flash memory. Fujitsu’s Flash technology combines years of EPROM and E2PROM experience to produce the highest levels of quality, reliability, and cost effectiveness. The device memory electrically erases the entire chip or all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/word at a time using the EPROM programming mechanism of hot electron injection. 2 MBM29DS163TE/BE10 ■ FEATURES • 0.23 µm Process Technology • Simultaneous Read/Write Operations (Dual Bank) Host system can program or erase in one bank, and then read immediately and simultaneously from the other bank with zero latency between read and write operations Read-while-erase Read-while-program • Single 1.8 V Read, Program, and Erase Minimized system level power requirements • Compatible with JEDEC-standard Commands Use the same software commands as E2PROMs • Compatible with JEDEC-standard Worldwide Pinouts 48-pin TSOP (1) (Package suffix : TN − Normal Bend Type, TR − Reversed Bend Type) 48-ball FBGA (Package suffix : PBT) • Minimum 100,000 Program/Erase Cycles • High Performance 100 ns maximum access time • Sector Erase Architecture Eight 4 K word and thirty-one 32 K word sectors in word mode Eight 8 K byte and thirty-one 64 K byte sectors in byte mode Any combination of sectors can be concurrently erased. Also supports full chip erase. • Boot Code Sector Architecture T = Top sector B = Bottom sector • HiddenROM Region 64 K byte of HiddenROM, accessible through a new “HiddenROM Enable” command sequence Factory serialized and protected to provide a secure electronic serial number (ESN) • WP/ACC Input Pin At VIL, allows protection of boot sectors, regardless of sector protection/unprotection status At VIH, allows removal of boot sector protection At VACC, increases program performance • Embedded EraseTM* Algorithms Automatically pre-programs and erases the chip or any sector • Embedded ProgramTM* Algorithms Automatically writes and verifies data at specified address • Data Polling and Toggle Bit feature for detection of program or erase cycle completion • Ready/Busy output (RY/BY) Hardware method for detection of program or erase cycle completion • Automatic Sleep Mode When addresses remain stable, automatically switch themselves to low power mode. • Program Suspend/Resume • Erase Suspend/Resume Suspends the erase operation to allow a read data and/or program in another sector within the same device • Sector Group Protection Hardware method disables any combination of sector groups from program or erase operations • Sector Group Protection Set function by Extended sector group protection command • Fast Programming Function by Extended Command • Temporary Sector Group Unprotection Temporary sector group unprotection via the RESET pin. • In accordance with CFI (Common Flash Memory Interface) *: Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc. 3 MBM29DS163TE/BE10 ■ PIN ASSIGNMENTS TSOP (1) A15 A14 A13 A12 A11 A10 A9 A8 A19 N.C. WE RESET N.C. WP/ACC RY/BY A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 (Marking Side) MBM29DS163TE/BE Normal Bend 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE VSS CE A0 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 A0 CE VSS OE DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11 VCC DQ4 DQ12 DQ5 DQ13 DQ6 DQ14 DQ7 DQ15/A-1 VSS BYTE A16 (FPT-48P-M19) A1 A2 A3 A4 A5 A6 A7 A17 A18 RY/BY WP/ACC N.C. RESET WE N.C. A19 A8 A9 A10 A11 A12 A13 A14 A15 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 (Marking Side) MBM29DS163TE/BE Reverse Bend (FPT-48P-M20) (Continued) 4 MBM29DS163TE/BE10 (Continued) FBGA (TOP VIEW) Marking Side A6 B6 C6 D6 E6 F6 G6 H6 A13 A12 A14 A15 A16 BYTE VSS A5 B5 C5 D5 E5 F5 DQ15/ A-1 G5 A9 A8 A10 A11 DQ7 DQ14 DQ13 DQ6 A4 B4 C4 D4 E4 F4 G4 H4 WE RESET N.C. A19 DQ5 DQ12 VCC DQ4 H5 A3 B3 C3 D3 E3 F3 G3 H3 RY/BY A18 N.C. DQ2 DQ10 DQ11 DQ3 A2 WP/ ACC B2 C2 D2 E2 F2 G2 H2 A7 A17 A6 A5 DQ0 DQ8 DQ9 DQ1 A1 B1 C1 D1 E1 F1 G1 H1 A3 A4 A2 A1 A0 CE OE VSS (BGA-48P-M11) 5 MBM29DS163TE/BE10 ■ PIN DESCRIPTION Pin A19 to A0, A-1 Address Inputs DQ15 to DQ0 Data Inputs/Outputs CE Chip Enable OE Output Enable WE Write Enable RY/BY Ready/Busy Output RESET Hardware Reset Pin/Temporary Sector Group Unprotection BYTE WP/ACC 6 Function Selects 8-bit or 16-bit mode Hardware Write Protection/Program Acceleration N.C. No Internal Connection VSS Device Ground VCC Device Power Supply MBM29DS163TE/BE10 ■ BLOCK DIAGRAM VCC Bank 2 Address Cell Matrix A19 to A0 (A-1) (Bank 2) Y-Gating & Data Latch VSS X-Decoder RESET WE CE OE RY/BY State Control & Command Register Status DQ15 to DQ0 Control BYTE WP/ACC DQ15 to DQ0 Bank 1 Address Cell Matrix (Bank 1) Y-Gating & Data Latch X-Decoder ■ LOGIC SYMBOL A-1 20 A19 to A0 16 or 8 DQ15 to DQ0 CE OE WE RY/BY RESET BYTE WP/ACC 7 MBM29DS163TE/BE10 ■ DEVICE BUS OPERATION MBM29DS163TE/BE User Bus Operations (BYTE = VIH) Table CE OE WE A0 Operation A1 A6 A9 DQ15 to DQ0 RESET WP/ ACC Auto-Select Manufacturer Code*1 L L H L L L VID Code H X Auto-Select Device Code*1 L L H H L L VID Code H X Read*3 L L H A0 A1 A6 A9 DOUT H X Standby H X X X X X X High-Z H X Output Disable L H H X X X X High-Z H X Write (Program/Erase) L H L A0 A1 A6 A9 DIN H X L VID L H L VID X H X L L H L H L VID Code H X X X X X X X X X VID X Reset (Hardware) /Standby X X X X X X X High-Z L X Boot Block Sector Write Protection X X X X X X X X X L Enable Sector Group Protection*2, *4 2, 4 Verify Sector Group Protection* * Temporary Sector Group Unprotection* 5 MBM29DS163TE/BE User Bus Operations (BYTE = VIL) Table Operation CE OE WE DQ15/ A-1 A0 A1 A6 A9 DQ7 to DQ0 RESET WP/ ACC Auto-Select Manufacturer Code*1 L L H L L L L VID Code H X Auto-Select Device Code*1 L L H L H L L VID Code H X Read*3 L L H A-1 A0 A1 A6 A9 DOUT H X Standby H X X X X X X X High-Z H X Output Disable L H H X X X X X High-Z H X Write (Program/Erase) L H L A-1 A0 A1 A6 A9 DIN H X Enable Sector Group Protection *2, *4 L VID L L H L VID X H X Verify Sector Group Protection*2, *4 L L H L L H L VID Code H X Temporary Sector Group Unprotection*5 X X X X X X X X X VID X Reset (Hardware) /Standby X X X X X X X X High-Z L X Boot Block Sector Write Protection X X X X X X X X X X L Legend : L = VIL, H = VIH, X = VIL or VIH, = Pulse input. See DC Characteristics for voltage levels. *1 : Manufacturer and device codes may also be accessed via a command register write sequence. See “MBM29DS163TE/BE Command Definitions” Table. *2 : Refer to the section on Sector Group Protection. *3 : WE can be VIL if OE is VIL, OE at VIH initiates the write operations. *4 : VCC must be between the minimum and maximum of the operation range. *5 : Also used for the extended sector group protection. 8 MBM29DS163TE/BE10 MBM29DS163TE/BE Command Definitions Table Command Sequence Read/Reset*1 Read/Reset*1 Word Byte Word Byte Bus Second Fourth Bus First Bus Third Bus Fifth Bus Sixth Bus Write Bus Read/Write Write Cycle Write Cycle Write Cycle Write Cycle CyWrite Cycle Cycle cles Req’d Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data 1 3 555h AAAh 3 Autoselect Byte 4 2AAh 555h AAh 555h AAAh 55h 2AAh AAAh Byte Word AAh 555h Word Program XXXh F0h 55h 555h AAh 2AAh 555h 55h 555h AAAh (BA) 555h (BA) AAAh 555h AAAh F0h RA*7 RD*7 90h IA*7 ID*7 A0h PA PD Program Suspend 1 BA B0h Program Resume 1 BA 30h Chip Erase Sector Erase Word Byte Word Byte 6 6 555h AAAh 555h AAAh AAh AAh 2AAh 555h 2AAh 555h 55h 55h 555h AAAh 555h AAAh 80h 80h 555h AAAh 555h AAAh AAh AAh 2AAh 555h 2AAh 555h 55h 555h AAAh 10h 55h SA 30h Erase Suspend 1 BA B0h Erase Resume 1 BA 30h 20h Set to Fast Mode Word Fast Program*2 Word Reset from Fast Mode*2 Word Byte Byte Byte Word Extended Sector Group Byte Protection*3 Query*4 Word Byte HiddenROM Entry Word HiddenROM Program*5 Word Byte Byte 3 2 2 3 1 3 4 555h AAAh XXXh XXXh BA BA AAh A0h 90h XXXh 60h 55h AAh 555h AAAh 555h AAAh 98h AAh AAh 2AAh 555h PA 55h PD XXXh *6 XXXh F0h 555h AAAh SPA 60h SPA 2AAh 555h 2AAh 555h 55h 55h 555h AAAh 555h AAAh 40h SPA*7 SD*7 88h PD A0h (HRA) PA (Continued) 9 MBM29DS163TE/BE10 (Continued) Command Sequence HiddenROM Word Erase*5 Byte HiddenROM Exit*5 Bus Second Fourth Bus First Bus Third Bus Fifth Bus Sixth Bus Write Bus Read/Write Write Cycle Write Cycle Write Cycle Write Cycle CyWrite Cycle Cycle cles Req’d Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data 6 555h AAAh 555h Word 4 Byte AAh 2AAh 555h 55h 2AAh AAh AAAh 55h 555h 555h AAAh (HRBA) 555h (HRBA) AAAh 80h 555h AAAh AAh 90h XXXh 00h 2AAh 555h 55h HRA 30h *1 : Both of these reset commands one equivalent. *2 : This command is valid while Fast Mode. *3 : This command is valid while RESET = VID. *4 : The valid addresses are A6 to A0. *5 : This command is valid while HiddenROM mode. *6 : The data "00h" is also acceptable. *7 : The fourth bus cycle is only for read. Notes : • • • • • • • • 10 Address bits A19 to A11 = X = “H” or “L” for all address commands except or Program Address (PA) , Sector Address (SA) , and Bank Address (BA) . Bus operations are defined in “MBM29DS163TE/BE User Bus Operation (BYTE = VIH)” Table and “MBM29DS163TE/BE User Bus Operation (BYTE = VIL)” Table. RA = Address of the memory location to be read IA = Autoselect read address sets both the bank address specified at (A19, A18, A17, A16, A15) and all the other A6, A1, A0, (A−1) . PA = Address of the memory location to be programmed Addresses are latched on the falling edge of the write pulse. SA = Address of the sector to be erased. The combination of A19, A18, A17, A16, A15, A14, A13, and A12 will uniquely select any sector. BA = Bank Address (A19 to A15) RD = Data read from location RA during read operation. ID = Device code/manufacture code for the address located by IA. PD = Data to be programmed at location PA. Data is latched on the rising edge of write pulse. SPA = Sector group address to be protected. Set sector group address (SGA) and (A6, A1, A0) = (0, 1, 0) . SD = Sector group protection verify data. Output 01h at protected sector group addresses and output 00h at unprotected sector group addresses. HRA = Address of the HiddenROM area 29DS163TE (Top Boot Type) Word Mode : 0F8000h to 0FFFFFh Byte Mode : 1F0000h to 1FFFFFh 29DS163BE (Bottom Boot Type) Word Mode : 000000h to 007FFFh Byte Mode : 000000h to 00FFFFh HRBA = Bank Address of the HiddenROM area 29DS163TE (Top Boot Type) : A19 = A18 = A17 = A16 = A15 = VIH 29DS163BE (Bottom Boot Type) : A19 = A18 = A17 = A16 = A15 = VIL The system should generate the following address patterns : Word Mode : 555h or 2AAh to addresses A10 to A0 Byte Mode : AAAh or 555h to addresses A10 to A0, and A-1 MBM29DS163TE/BE10 • • Both Read/Reset commands are functionally equivalent, resetting the device to the read mode. Command combinations not described in “MBM29DS163TE/BE Command Definitions” Table are illegal. 11 MBM29DS163TE/BE10 MBM29DS163TE/BE Sector Group Protection Verify Autoselect Codes Table A19 to A12 A6 A1 A0 A-1*1 Code (HEX) BA*3 VIL VIL VIL VIL 04h BA*3 VIL VIL VIH VIL 95h X 2295h BA*3 VIL VIL VIH VIL 96h X 2296h BA*3 VIL VIH VIH VIL 05h X 2205h Sector Group Addresses VIL VIH VIL VIL 01h*2 Type Manufacture’s Code Byte MBM29DS163TE Word Device Code Byte MBM29DS163BE Extend Code Word MBM29DS163TE/BE Byte Word Sector Group Protection *1 : A-1 is for Byte mode. *2 : Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses. *3 : BA is Bank Address which is needed only in Command Autoselect mode. Expanded Autoselect Code Table Type Manufacturer’s Code DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 0 0 0 0 95h A-1 MBM29DS (B) 163TE (W) 2295h 0 Device Code 96h A-1 MBM29DS (B) 163BE (W) 2296h 0 HZ HZ HZ HZ 0 1 0 0 HZ HZ HZ HZ 0 1 0 0 05h A-1 Extend MBM29DS (B) Code 163TE/BE (W) 2205h 0 HZ HZ HZ HZ 0 1 0 0 0 1 0 0 0 0 0 0 Sector Group Protection (B) : Byte mode (W) : Word mode HZ : High-Z 12 Code 04h A-1/0 01h A-1/0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 1 0 1 1 0 0 1 0 1 0 1 1 0 0 1 0 1 1 0 1 0 0 1 0 1 1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 1 HZ HZ HZ 0 1 0 HZ HZ HZ 0 1 0 HZ HZ HZ MBM29DS163TE/BE10 ■ FLEXIBLE SECTOR-ERASE ARCHITECTURE Sector Address Table (MBM29DS163TE) Sector Address Bank Sector Bank Address A19 A18 A17 A16 A15 A14 A13 A12 Bank 2 Sector Size (Kbytes/ Kwords) (×8) Address Range (×16) Address Range SA0 0 0 0 0 0 X X X 64/32 000000h to 00FFFFh 000000h to 007FFFh SA1 0 0 0 0 1 X X X 64/32 010000h to 01FFFFh 008000h to 00FFFFh SA2 0 0 0 1 0 X X X 64/32 020000h to 02FFFFh 010000h to 017FFFh SA3 0 0 0 1 1 X X X 64/32 030000h to 03FFFFh 018000h to 01FFFFh SA4 0 0 1 0 0 X X X 64/32 040000h to 04FFFFh 020000h to 027FFFh SA5 0 0 1 0 1 X X X 64/32 050000h to 05FFFFh 028000h to 02FFFFh SA6 0 0 1 1 0 X X X 64/32 060000h to 06FFFFh 030000h to 037FFFh SA7 0 0 1 1 1 X X X 64/32 070000h to 07FFFFh 038000h to 03FFFFh SA8 0 1 0 0 0 X X X 64/32 080000h to 08FFFFh 040000h to 048000h SA9 0 1 0 0 1 X X X 64/32 090000h to 09FFFFh 048000h to 04FFFFh SA10 0 1 0 1 0 X X X 64/32 0A0000h to 0AFFFFh 050000h to 058000h SA11 0 1 0 1 1 X X X 64/32 0B0000h to 0BFFFFh 058000h to 05FFFFh SA12 0 1 1 0 0 X X X 64/32 0C0000h to 0CFFFFh 060000h to 068000h SA13 0 1 1 0 1 X X X 64/32 0D0000h to 0DFFFFh 068000h to 06FFFFh SA14 0 1 1 1 0 X X X 64/32 0E0000h to 0EFFFFh 070000h to 078FFFh SA15 0 1 1 1 1 X X X 64/32 0F0000h to 0FFFFFh 078000h to 07FFFFh SA16 1 0 0 0 0 X X X 64/32 100000h to 10FFFFh 080000h to 088000h SA17 1 0 0 0 1 X X X 64/32 110000h to 11FFFFh 088000h to 08FFFFh SA18 1 0 0 1 0 X X X 64/32 120000h to 12FFFFh 090000h to 098000h SA19 1 0 0 1 1 X X X 64/32 130000h to 13FFFFh 098000h to 09FFFFh SA20 1 0 1 0 0 X X X 64/32 140000h to 14FFFFh 0A0000h to 0A7FFFh SA21 1 0 1 0 1 X X X 64/32 150000h to 15FFFFh 0A8000h to 00AFFFh SA22 1 0 1 1 0 X X X 64/32 160000h to 16FFFFh 0B0000h to 0B7000h SA23 1 0 1 1 1 X X X 64/32 170000h to 17FFFFh 0B8000h to 0BFFFFh (Continued) 13 MBM29DS163TE/BE10 (Continued) Sector Address Bank Sector Bank Address A19 A18 A17 A16 A15 A14 A13 A12 Sector Size (Kbytes/ Kwords) (×8) Address Range (×16) Address Range SA24 1 1 0 0 0 X X X 64/32 180000h to 18FFFFh 0C0000h to 0C7FFFh SA25 1 1 0 0 1 X X X 64/32 190000h to 19FFFFh 0C8000h to 0CFFFFh SA26 1 1 0 1 0 X X X 64/32 1A0000h to 1AFFFFh 0D0000h to 0D7FFFh SA27 1 1 0 1 1 X X X 64/32 1B0000h to 1BFFFFh 0D8000h to 0DFFFFh SA28 1 1 1 0 0 X X X 64/32 1C0000h to 1CFFFFh 0E0000h to 0E7FFFh SA29 1 1 1 0 1 X X X 64/32 1D0000h to 1DFFFFh 0E8000h to 0EFFFFh SA30 1 1 1 1 0 X X X 64/32 1E0000h to 1EFFFFh 0F0000h to 0F7000h Bank 1 SA31 1 1 1 1 1 0 0 0 8/4 1F0000h to 1F1FFFh 0F8000h to 0F8FFFh SA32 1 1 1 1 1 0 0 1 8/4 1F2000h to 1F3FFFh 0F9000h to 0F9FFFh SA33 1 1 1 1 1 0 1 0 8/4 1F4000h to 1F5FFFh 0FA000h to 0FAFFFh SA34 1 1 1 1 1 0 1 1 8/4 1F6000h to 1F7FFFh 0FB000h to 0FBFFFh SA35 1 1 1 1 1 1 0 0 8/4 1F8000h to 1F9FFFh 0FC000h to 0FCFFFh SA36 1 1 1 1 1 1 0 1 8/4 1FA000h to 1FBFFFh 0FD000h to 0FDFFFh SA37 1 1 1 1 1 1 1 0 8/4 1FC000h to 1FDFFFh 0FE000h to 0FEFFFh SA38 1 1 1 1 1 1 1 1 8/4 1FE000h to 1FFFFFh Notes : • The address range is A19 : A-1 if in byte mode (BYTE = VIL) . • The address range is A19 : A0 if in word mode (BYTE = VIH) . 14 0FF000h to 0FFFFFh MBM29DS163TE/BE10 Sector Address Table (MBM29DS163BE) Sector Address Bank Sector Bank Address A19 A18 A17 A16 A15 A14 A13 A12 Bank 2 Sector Size (Kbytes/ Kwords) (×8) Address Range (×16) Address Range SA38 1 1 1 1 1 X X X 64/32 1F0000h to 1FFFFFh 0F8000h to 0FFFFFh SA37 1 1 1 1 0 X X X 64/32 1E0000h to 1EFFFFh 0F0000h to 0F7FFFh SA36 1 1 1 0 1 X X X 64/32 1D0000h to 1DFFFFh 0E8000h to 0EFFFFh SA35 1 1 1 0 0 X X X 64/32 1C0000h to 1CFFFFh 0E0000h to 0E7FFFh SA34 1 1 0 1 1 X X X 64/32 1B0000h to 1BFFFFh 0D8000h to 0DFFFFh SA33 1 1 0 1 0 X X X 64/32 1A0000h to 1AFFFFh 0D0000h to 0D7FFFh SA32 1 1 0 0 1 X X X 64/32 190000h to 19FFFFh 0C8000h to 0CFFFFh SA31 1 1 0 0 0 X X X 64/32 180000h to 18FFFFh 0C0000h to 0C7FFFh SA30 1 0 1 1 1 X X X 64/32 170000h to 17FFFFh 0B8000h to 0BFFFFh SA29 1 0 1 1 0 X X X 64/32 160000h to 16FFFFh 0B0000h to 0B7FFFh SA28 1 0 1 0 1 X X X 64/32 150000h to 15FFFFh 0A8000h to 0AFFFFh SA27 1 0 1 0 0 X X X 64/32 140000h to 14FFFFh 0A0000h to 0A7FFFh SA26 1 0 0 1 1 X X X 64/32 130000h to 13FFFFh 098000h to 09FFFFh SA25 1 0 0 1 0 X X X 64/32 120000h to 12FFFFh 090000h to 097FFFh SA24 1 0 0 0 X X X X 64/32 110000h to 11FFFFh 088000h to 08FFFFh SA23 1 0 0 0 0 X X X 64/32 100000h to 10FFFFh 080000h to 087FFFh SA22 0 1 1 1 1 X X X 64/32 0F0000h to 0FFFFFh 078000h to 07FFFFh SA21 0 1 1 1 0 X X X 64/32 0E0000h to 0EFFFFh 070000h to 077FFFh SA20 0 1 1 0 1 X X X 64/32 0D0000h to 0DFFFFh 068000h to 06FFFFh SA19 0 1 1 0 0 X X X 64/32 0C0000h to 0CFFFFh 060000h to 067FFFh SA18 0 1 0 1 1 X X X 64/32 0B0000h to 0BFFFFh 058000h to 05FFFFh SA17 0 1 0 1 0 X X X 64/32 0A0000h to 0AFFFFh 050000h to 057FFFh SA16 0 1 0 0 1 X X X 64/32 090000h to 0FFFFFh 048000h to 04FFFFh SA15 0 1 0 0 0 X X X 64/32 080000h to 08FFFFh 040000h to 047FFFh (Continued) 15 MBM29DS163TE/BE10 (Continued) Sector Address Bank Sector Bank Address A19 A18 A17 A16 A15 A14 A13 A12 Bank 1 Sector Size (Kbytes/ Kwords) (×8) Address Range (×16) Address Range SA14 0 0 1 1 1 X X X 64/32 070000h to 07FFFFh 038000h to 03FFFFh SA13 0 0 1 1 0 X X X 64/32 060000h to 06FFFFh 030000h to 037FFFh SA12 0 0 1 0 1 X X X 64/32 050000h to 05FFFFh 028000h to 02FFFFh SA11 0 0 1 0 0 X X X 64/32 040000h to 04FFFFh 020000h to 027FFFh SA10 0 0 0 1 1 X X X 64/32 030000h to 03FFFFh 018000h to 01FFFFh SA9 0 0 0 1 0 X X X 64/32 020000h to 02FFFFh 010000h to 017FFFh SA8 0 0 0 0 1 X X X 64/32 010000h to 01FFFFh 008000h to 008FFFh SA7 0 0 0 0 0 1 1 1 8/4 00E000h to 00FFFFh 007000h to 007FFFh SA6 0 0 0 0 0 1 1 0 8/4 00C000h to 00DFFFh 006000h to 006FFFh SA5 0 0 0 0 0 1 0 1 8/4 00A000h to 00BFFFh 005000h to 005FFFh SA4 0 0 0 0 0 1 0 0 8/4 008000h to 009FFFh 004000h to 004FFFh SA3 0 0 0 0 0 0 1 1 8/4 006000h to 007FFFh 003000h to 003FFFh SA2 0 0 0 0 0 0 1 0 8/4 004000h to 005FFFh 002000h to 002FFFh SA1 0 0 0 0 0 0 0 1 8/4 002000h to 003FFFh 001000h to 001FFFh SA0 0 0 0 0 0 0 0 0 8/4 000000h to 001FFFh 000000h to 000FFFh Notes : • The address range is A19 : A-1 if in byte mode (BYTE = VIL) . • The address range is A19 : A0 if in word mode (BYTE = VIH) . 16 MBM29DS163TE/BE10 Sector Group Addresses (MBM29DS163TE) Table (Top Boot Block) Sector Group A19 A18 A17 A16 A15 A14 A13 A12 Sectors SGA0 0 0 0 0 0 X X X SA0 0 0 0 0 1 X X X 0 0 0 1 0 X X X 0 0 0 1 1 X X X SGA2 0 0 1 X X X X X SA4 to SA7 SGA3 0 1 0 X X X X X SA8 to SA11 SGA4 0 1 1 X X X X X SA12 to SA15 SGA5 1 0 0 X X X X X SA16 to SA19 SGA6 1 0 1 X X X X X SA20 to SA23 SGA7 1 1 0 X X X X X SA24 to SA27 1 1 1 0 0 X X X 1 1 1 0 1 X X X 1 1 1 1 0 X X X SGA9 1 1 1 1 1 0 0 0 SA31 SGA10 1 1 1 1 1 0 0 1 SA32 SGA11 1 1 1 1 1 0 1 0 SA33 SGA12 1 1 1 1 1 0 1 1 SA34 SGA13 1 1 1 1 1 1 0 0 SA35 SGA14 1 1 1 1 1 1 0 1 SA36 SGA15 1 1 1 1 1 1 1 0 SA37 SGA16 1 1 1 1 1 1 1 1 SA38 SGA1 SGA8 SA1 to SA3 SA28 to SA30 17 MBM29DS163TE/BE10 Sector Group Addresses (MBM29DS163BE) Table (Bottom Boot Block) Sector Group A19 A18 A17 A16 A15 A14 A13 A12 Sectors SGA0 0 0 0 0 0 0 0 0 SA0 SGA1 0 0 0 0 0 0 0 1 SA1 SGA2 0 0 0 0 0 0 1 0 SA2 SGA3 0 0 0 0 0 0 1 1 SA3 SGA4 0 0 0 0 0 1 0 0 SA4 SGA5 0 0 0 0 0 1 0 1 SA5 SGA6 0 0 0 0 0 1 1 0 SA6 SGA7 0 0 0 0 0 1 1 1 SA7 0 0 0 0 1 X X X 0 0 0 1 0 X X X 0 0 0 1 1 X X X SGA9 0 0 1 X X X X X SA11 to SA14 SGA10 0 1 0 X X X X X SA15 to SA18 SGA11 0 1 1 X X X X X SA19 to SA22 SGA12 1 0 0 X X X X X SA23 to SA26 SGA13 1 0 1 X X X X X SA27 to SA30 SGA14 1 1 0 X X X X X SA31 to SA34 1 1 1 0 0 X X X 1 1 1 0 1 X X X 1 1 1 1 0 X X X 1 1 1 1 1 X X X SGA8 SGA15 SGA16 18 SA8 to SA10 SA35 to SA37 SA38 MBM29DS163TE/BE10 Common Flash Memory Interface Code Table Description A6 to A0 DQ15 to DQ0 Query-unique ASCII string “QRY” 10h 11h 12h 0051h 0052h 0059h Primary OEM Command Set 2h : AMD/FJ standard type 13h 14h 0002h 0000h Address for Primary Extended Table 15h 16h 0040h 0000h Alternate OEM Command Set (00h = not applicable) 17h 18h 0000h 0000h Address for Alternate OEM Extended Table 19h 1Ah 0000h 0000h VCC Min (write/erase) DQ7 to DQ4 : V, DQ3 to DQ0 : 100 mV 1Bh 0018h VCC Max (write/erase) DQ7 to DQ4 : V, DQ3 to DQ0 : 100 mV 1Ch 0022h VPP Min voltage 1Dh 0000h VPP Max voltage 1Eh 0000h Typical timeout per single byte/word write 2N µs 1Fh 0004h Typical timeout for Min size buffer write 2 µs 20h 0000h Typical timeout per individual block erase 2 ms 21h 000Ah Typical timeout for full chip erase 2N ms 22h 0000h Max timeout for byte/word write 2N times typical 23h 0005h 24h 0000h Max timeout per individual block erase 2 times typical 25h 0004h Max timeout for full chip erase 2N times typical 26h 0000h Device Size = 2N byte 27h 0015h Flash Device Interface description 28h 29h 0002h 0000h Max number of byte in multi-byte write = 2N 2Ah 2Bh 0000h 0000h Number of Erase Block Regions within device 2Ch 0002h Erase Block Region 1 Information 2Dh 2Eh 2Fh 30h 0007h 0000h 0020h 0000h Erase Block Region 2 Information 31h 32h 33h 34h 001Eh 0000h 0000h 0001h N N N Max timeout for buffer write 2 times typical N (Continued) 19 MBM29DS163TE/BE10 (Continued) Description 20 A6 to A0 DQ15 to DQ0 Query-unique ASCII string “PRI” 40h 41h 42h 0050h 0052h 0049h Major version number, ASCII 43h 0031h Minor version number, ASCII 44h 0032h Address Sensitive Unlock 0h = Required 1h = Not Required 45h 0000h Erase Suspend 0h = Not Supported 1h = To Read Only 2h = To Read & Write 46h 0002h Sector Protection 0h = Not Supported X = Number of sectors in per group 47h 0001h Sector Temporary Unprotection 00h = Not Supported 01h = Supported 48h 0001h Sector Protection Algorithm 49h 0004h Number of Sector for Bank 2 00h = Not Supported 4Ah 0018h Burst Mode Type 00h = Not Supported 4Bh 0000h Page Mode Type 00h = Not Supported 4Ch 0000h ACC (Acceleration) Supply Minimum 00h = Not Supported, DQ7 to DQ4 : V, DQ3 to DQ0 : 100 mV 4Dh 0085h ACC (Acceleration) Supply Maximum 00h = Not Supported, DQ7 to DQ4 : V, DQ3 to DQ0 : 100 mV 4Eh 0095h Boot Type 02h = MBM29DS163BE 03h = MBM29DS163TE 4Fh 00XXh Program Suspend 00h = Not Supported 01h = Supported 50h 0001h MBM29DS163TE/BE10 ■ FUNCTIONAL DESCRIPTION Simultaneous Operation The device has a feature, that is capable of reading data from one bank of memory while a program or erase operation is in progress in the other bank of memory (simultaneous operation) , in addition to the conventional features (read, program, erase, erase-suspend read, and erase-suspend program) . The bank selection can be selected by bank address (A19 to A15) with zero latency. The device has two banks which contain Bank 1 (8 KB × eight sectors, 64 KB × seven sectors) and Bank 2 (64 KB × twenty-four sectors) . The simultaneous operation cannot execute multi-function mode in the same bank. “Simultaneous Operation” Table shows the combinations for simultaneous operation (refer to “Bank-to-Bank Read/Write Timing Diagram” in “■ TIMING DIAGRAM”) . Simultaneous Operation Table Case Bank 1 Status Bank 2 Status 1 Read mode Read mode 2 Read mode Autoselect mode 3 Read mode Program mode 4 Read mode Erase mode * 5 Autoselect mode Read mode 6 Program mode Read mode 7 Erase mode * Read mode * : Erase operation may also be supended to read from or program to a sector not being erased. Read Mode The device has two control functions to be satisfied to obtaining data at the outputs. CE is the power control and should be used for a device selection. OE is the output control and should be used to gate data to the output pins if a device is selected. Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable access time (tCE) is the delay from stable addresses and stable CE to valid data at the output pins. The output enable access time is the delay from the falling edge of OE to valid data at the output pins (assuming the addresses have been stable for at least tACC-tOE time) . When reading out data without changing addresses after power-up, it is necessary to input hardware reset or to change CE pin from “H” or “L”. The RESET pin must be held low during VCC rampup to insure that device powers up correctly. (Refer to “Power On/Off Timing Diagram” in “■ TIMING DIAGRAM”.) Standby Mode There are two ways to implement the standby mode on the device, one using both the CE and RESET pins; the other via the RESET pin only. When using both pins, a CMOS standby mode is achieved with CE and RESET inputs both held at VCC ± 0.3 V. Under this condition the current consumed is less than 5 µA max. During Embedded Algorithm operation, VCC active current (ICC2) is required even CE = “H”. The device can be read with standard access time (tCE) from either of these standby modes. When using the RESET pin only, a CMOS standby mode is achieved with RESET input held at VSS ± 0.3 V (CE = “H” or “L”) . Under this condition the current consumed is less than 5 µA max. Once the RESET pin is taken high, the device requires tRH as wake up time for outputs to be valid for read access. In the standby mode the outputs are in the high impedance state, independently of the OE input. 21 MBM29DS163TE/BE10 Automatic Sleep Mode There is a function called automatic sleep mode to restrain power consumption during read-out of the device data. This mode can be useful in the application such as a handy terminal which requires low power consumption. To activate this mode, the device automatically switches themselves to low power mode when the device addresses remain stable during access time of 150 ns. It is not necessary to control CE, WE, and OE on the mode. Under the mode, the current consumed is typically 1 µA (CMOS Level) . During simultaneous operation, VCC active current (ICC2) is required. Since the data are latched during this mode, the data are read-out continuously. If the addresses are changed, the mode is canceled automatically, and the device reads the data for changed addresses. Output Disable With the OE input at a logic high level (VIH) , output from the device is disabled. This will cause the output pins to be in a high impedance state. Autoselect The autoselect mode allows the reading out of a binary code from the device and will identify its manufacturer and type. This mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional over the entire temperature range of the device. To activate this mode, the programming equipment must force VID (10.0 V to 11.0 V) on address pin A9. Two identifier bytes may then be sequenced from the device outputs by toggling address A0 from VIL to VIH. All addresses are DON’T CARES except A0, A1, and A6 (A-1) . (See “MBM29DS163TE/BE User Bus Operations (BYTE = VIH)” Table and “MBM29DS163TE/BE User Bus Operations (BYTE = VIL)” Table in “■ DEVICE BUS OPERATION”.) The manufacturer and device codes may also be read via the command register, for instances when the device is erased or programmed in a system without access to high voltage on the A9 pin. The command sequence is illustrated in “ MBM29DS163TE/BE Command Definitions” Table in “■ DEVICE BUS OPERATION”. Word 0 (A0 = VIL) represents the manufacturer’s code (Fujitsu = 04h) and word 1 (A0 = VIH) represents the device identifier code. These two bytes/words are given in MBM29DS163TE/BE Sector Group Protection Verify Autoselect Codes” Table and “Expanded Autoselect Code “ Table in “■ DEVICE BUS OPERATION”. In order to read the proper device codes when executing the autoselect, A1 must be VIL. (See “MBM29DS163TE/BE Sector Group Protection Verify Autoselect Codes” Table and “Expanded Autoselect Code “ Table in “■ DEVICE BUS OPERATION”.) In case of applying VID on A9, since both Bank 1 and Bank 2 enters Autoselect mode, the simultenous operation can not be executed. Write Device erasure and programming are accomplished via the command register. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. The command register itself does not occupy any addressable memory location. The register is a latch used to store the commands, along with the address and data information needed to execute the command. The command register is written by bringing WE to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on the falling edge of WE or CE, whichever happens later; while data is latched on the rising edge of WE or CE, whichever happens first. Standard microprocessor write timings are used. Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters. Sector Group Protection The device features hardware sector group protection. This feature will disable both program and erase operations in any combination of twenty five sector groups of memory. (See “Sector Group Addresses (MBM29DS163TE)” Table and “Sector Group Addresses (MBM29DS163BE)” Table in “■ FLEXIBLE SECTOR22 MBM29DS163TE/BE10 ERASE ARCHITECTURE”.) The sector group protection feature is enabled using programming equipment at the user’s site. The device is shipped with all sector groups unprotected. To activate this mode, the programming equipment must force VID on address pin A9 and control pin OE, (suggest VID = 11.5 V) , CE = VIL and A6 = A0 = VIL, A1 = VIH. The sector group addresses (A19, A18, A17, A16, A15, A14, A13, and A12) should be set to the sector to be protected. “Sector Address (MBM29DS163TE)” Table and “Sector Address (MBM29DS163BE)” Table in “■ FLEXIBLE SECTOR-ERASE ARCHITECTURE” define the sector address for each of the seventy one (71) individual sectors, and t“Sector Group Addresses (MBM29DS163TE)” Table and “Sector Group Addresses (MBM29DS163BE)” Table in “■ FLEXIBLE SECTOR-ERASE ARCHITECTURE” define the sector group address for each of the twenty five (25) individual group sectors. Programming of the protection circuitry begins on the falling edge of the WE pulse and is terminated with the rising edge of the same. Sector group addresses must be held constant during the WE pulse. See “Sector Group Protection Timing Diagram” in “■ TIMING DIAGRAM” and ”Sector Group Protection Algorithm” in “■ FLOW CHART” for sector group protection waveforms and algorithm. To verify programming of the protection circuitry, the programming equipment must force VID on address pin A9 with CE and OE at VIL and WE at VIH. Scanning the sector group addresses (A19, A18, A17, A16, A15, A14, A13, and A12) while (A6, A1, A0) = (0, 1, 0) will produce a logical “1” code at device output DQ0 for a protected sector. Otherwise the device will produce “0” for unprotected sector. In this mode, the lower order addresses, except for A0, A1, and A6 are DON’T CARES. Address locations with A1 = VIL are reserved for Autoselect manufacturer and device codes. A-1 requires to apply to VIL on byte mode. It is also possible to determine if a sector group is protected in the system by writing an Autoselect command. Performing a read operation at the address location XX02h, where the higher order addresses (A19, A18, A17, A16, A15, A14, A13, and A12) are the desired sector group address will produce a logical “1” at DQ0 for a protected sector group. See “MBM29DS163TE/BE Sector Group Protection Verify Autoselect Codes” Table and “Expanded Autoselect Code “ Table in “■ DEVICE BUS OPERATION” for Autoselect codes. Temporary Sector Group Unprotection This feature allows temporary unprotection of previously protected sector groups of the device in order to change data. The Sector Group Unprotection mode is activated by setting the RESET pin to high voltage (VID) . During this mode, formerly protected sector groups can be programmed or erased by selecting the sector group addresses. Once the VID is taken away from the RESET pin, all the previously protected sector groups will be protected again. Refer to “Temporary Sector Group Unprotection Timing Diagram” in “■ TIMING DIAGRAM” and ”Temporary Sector Group Unprotection Algorithm” in “■ FLOW CHART”. Extended Sector Group Protection In addition to normal sector group protection, the device has Extended Sector Group Protection as extended function. This function enables to protect sector group by forcing VID on RESET pin and write a command sequence. Unlike conventional procedure, it is not necessary to force VID and control timing for control pins. The only RESET pin requires VID for sector group protection in this mode. The extended sector group protection requires VID on RESET pin. With this condition, the operation is initiated by writing the set-up command (60h) into the command register. Then, the sector group addresses pins (A19, A18, A17, A16, A15, A14, A13 and A12) and (A6, A1, A0) = (0, 1, 0) should be set to the sector group to be protected (recommend to set VIL for the other addresses pins) , and write extended sector group protection command (60h) . A sector group is typically protected in 250 µs. To verify programming of the protection circuitry, the sector group addresses pins (A19, A18, A17, A16, A15, A14, A13 and A12) and (A6, A1, A0) = (0, 1, 0) should be set and write a command (40h) . Following the command write, a logical “1” at device output DQ0 will produce for protected sector in the read operation. If the output is logical “0”, please repeat to write extended sector group protection command (60h) again. To terminate the operation, it is necessary to set RESET pin to VIH. (Refer to “Extended Sector Group Protection Timing Diagram” in “■ TIMING DIAGRAM” and ”Extended Sector Group Protection Algorithm” in “■ FLOW CHART”.) 23 MBM29DS163TE/BE10 RESET Hardware Reset The device may be reset by driving the RESET pin to VIL. The RESET pin has a pulse requirement and has to be kept low (VIL) for at least “tRP” in order to properly reset the internal state machine. Any operation in the process of being executed will be terminated and the internal state machine will be reset to the read mode “tREADY” after the RESET pin is driven low. Furthermore, once the RESET pin goes high, the device requires an additional “tRH” before it will allow read access. When the RESET pin is low, the device will be in the standby mode for the duration of the pulse and all the data output pins will be tri-stated. If a hardware reset occurs during a program or erase operation, the data at that particular location will be corrupted. Please note that the RY/BY output signal should be ignored during the RESET pulse. See “RESET, RY/BY Timing Diagram” in “■ TIMING DIAGRAM” for the timing diagram. Refer to Temporary Sector Group Unprotection for additional functionality. Boot Block Sector Protection The Write Protection function provides a hardware method of protecting certain boot sectors without using VID. This function is one of two provided by the WP/ACC pin. If the system asserts VIL on the WP/ACC pin, the device disables program and erase functions in the two “outermost” 8 K byte boot sectors independently of whether those sectors are protected or unprotected using the method described in “Sector Protection/Unprotection”. The two outermost 8 K byte boot sectors are the two sectors containing the lowest addresses in a bottom-boot-configured device, or the two sectors containing the highest addresses in a top-boot-congfigured device. (MBM29DS163TE : SA37 and SA38, MBM29DS163BE : SA0 and SA1) If the system asserts VIH on the WP/ACC pin, the device reverts to whether the two outermost 8 K byte boot sectors were last set to be protected or unprotected. That is, sector protection or unprotection for these two sectors depends on whether they were last protected or unprotected using the method described in “Sector protection/unprotection”. Accelerated Program Operation The device offers accelerated program operation which enables the programming in high speed. If the system asserts VACC to the WP/ACC pin, the device automatically enters the acceleration mode and the time required for program operation will reduce to about 60%. This function is primarily intended to allow high speed program, so caution is needed as the sector group will temporarily be unprotected. The system would use a fast program command sequence when programming during acceleration mode. Set command to fast mode and reset command from fast mode are not necessary. When the device enters the acceleration mode, the device automatically set to fast mode. Therefore, the pressent sequence could be used for programming and detection of completion during acceleration mode. Removing VACC from the WP/ACC pin returns the device to normal operation. Do not remove VACC from WP/ ACC pin while programming. See “Accelerated Program Timing Diagram” in “■ TIMING DIAGRAM”. 24 MBM29DS163TE/BE10 ■ COMMAND DEFINITIONS The device operations are selected by writing specific address and data sequences into the command register. Writing incorrect address and data values or writing them in the improper sequence will reset the device to the read mode. Some commands require Bank Address (BA) input. When command sequences are inputed to bank being read, the commands have priority over reading. “MBM29DS163TE/BE Command Definitions” Table in “■ DEVICE BUS OPERATION” defines the valid register command sequences. Note that the Erase Suspend (B0h) and Erase Resume (30h) commands are valid only while the Sector Erase operation is in progress. Also the Program Suspend (B0h) and Program Resume (30h) commands are valid only while the Program operation is in progress. Moreover both Read/Reset commands are functionally equivalent, resetting the device to the read mode. Please note that commands are always written at DQ7 to DQ0 and DQ15 to DQ8 bits are ignored. Read/Reset Command In order to return from Autoselect mode or Exceeded Timing Limits (DQ5 = 1) to Read/Reset mode, the Read/ Reset operation is initiated by writing the Read/Reset command sequence into the command register. Microprocessor read cycles retrieve array data from the memory. The device remain enabled for reads until the command register contents are altered. The device will automatically power-up in the Read/Reset state. In this case, a command sequence is not required to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no spurious alteration of the memory content occurs during the power transition. Refer to the AC Read Characteristics and Waveforms for the specific timing parameters. Autoselect Command Flash memories are intended for use in applications where the local CPU alters memory contents. As such, manufacture and device codes must be accessible while the device resides in the target system. PROM programmers typically access the signature codes by raising A9 to a high voltage. However, multiplexing high voltage onto the address lines is not generally desired system design practice. The device contains an Autoselect command operation to supplement traditional PROM programming methodology. The operation is initiated by writing the Autoselect command sequence into the command register. The Autoselect command sequence is initiated by firstly writing two unlock cycles. This is followed by a third write cycle that contains the bank address (BA) and the Autoselect command. Then the manufacture and device codes can be read from the bank, and actual data of memory cell can be read from the another bank. Following the command write, a read cycle from address (BA) 00h retrieves the manufacture code of 04h. A read cycle from address (BA) 01h for ×16 ( (BA) 02h for ×8) returns the device code. (See “MBM29DS163TE/ BE Sector Group Protection Verify Autoselect Codes” Table and “Expanded Autoselect Code “ Table in “■ DEVICE BUS OPERATION”.) The sector state (protection or unprotection) will be informed by address (BA) 02h for ×16 ( (BA) 04h for ×8) . Scanning the sector group addresses (A19, A18, A17, A16, A15, A14, A13, and A12) while (A6, A1, A0) = (0, 1, 0) will produce a logical “1” at device output DQ0 for a protected sector group. The programming verification should be performed by verify sector group protection on the protected sector. (See “MBM29DS163TE/BE User Bus Operations (BYTE = VIH)” Table and “MBM29DS163TE/BE User Bus Operations (BYTE = VIL)” Table in “■ DEVICE BUS OPERATION”.) The manufacture and device codes can be allowed reading from selected bank. To read the manufacture and device codes and sector protection status from non-selected bank, it is necessary to write Read/Reset command sequence into the register and then Autoselect command should be written into the bank to be read. If the software (program code) for Autoselect command is stored into the Flash memory, the device and manufacture codes should be read from the other bank which doesn’t contain the software. To terminate the operation, it is necessary to write the Read/Reset command sequence into the register. To execute the Autoselect command during the operation, writing Read/Reset command sequence must precede the Autoselect command. 25 MBM29DS163TE/BE10 Byte/Word Programming The device is programmed on a byte-by-byte (or word-by-word) basis. Programming is a four bus cycle operation. There are two “unlock” write cycles. These are followed by the program set-up command and data write cycles. Addresses are latched on the falling edge of CE or WE, whichever happens later and the data is latched on the rising edge of CE or WE, whichever happens first. The rising edge of CE or WE (whichever happens first) begins programming. Upon executing the Embedded Program Algorithm command sequence, the system is not required to provide further controls or timings. The device automatically provides adequate internally generated program pulses and verify programmed cell margin. The system can determine the status of the program operation by using DQ7 (Data Polling) , DQ6 (Toggle Bit) , or RY/BY. The Data Polling and Toggle Bit must be performed at the memory location being programmed. The automatic programming operation is completed when the data on DQ7 is equivalent to data written to this bit at which the device return to the read mode and addresses are no longer latched. (See “Hardware Sequence Flags” , Hardware Sequence Flags.) Therefore the device requires that a valid address to the device be supplied by the system at this particular moment. Hence Data Polling must be performed at the memory location being programmed. Any commands written to the chip during this period are ignored. If hardware reset occurs during the programming operation, it is impossible to guarantee the data being written. Programming is allowed in any sequence and across sector boundaries. Beware that a data “0” cannot be programmed back to a “1”. Attempting to do so may either hang up the device or result in an apparent success according to the data polling algorithm but a read from Read/Reset mode will show that the data is still “0”. Only erase operations can convert “0”s to “1”s. “Embedded ProgramTM Algorithm” in “■ FLOW CHART” illustrates the Embedded ProgramTM Algorithm using typical command strings and bus operations. Program Suspend/Resume The Program Suspend command allows the system to interrupt a program operation so that data can be read from any address. Writing the Program Suspend command (B0h) during the Embedded Program operation immediately suspends the programming. The Program Suspend command may also be issued during a programming operation while an erase is suspended. The bank addresses of sector being programed should be set when writing the Program Suspend command. When the Program Suspend command is written during a programming process, the device halts the program operation within 1 µs and updates the status bits. After the program operation has been suspended, the system can read data from any address. The data at program-suspended address is not valid. Normal read timing and command definitions apply. After the Program Resume command (30h) is written, the device reverts to programming. The bank addresses of sector being suspended should be set when writing the Program Resume command. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard program operation. See “Write Operation Status” for more information. The system may also write the autoselect command sequence when the device in the Program Suspend mode. The device allows reading autoselect codes at the addresses within programming sectors, since the codes are not stored in the memory. When the device exits the autoselect mode, the device reverts to the Program Suspend mode, and is ready for another valid operation. See “Autoselect Command Sequence” for more information. The system must write the Program Resume command (address bits are “Bank Address”) to exit the Program Suspend mode and continue the programming operation. Further writes of the Resume command are ignored. Another Program Suspend command can be written after the device has resumed programming. Chip Erase Chip erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the “set-up” command. Two more “unlock” write cycles are then followed by the chip erase command. 26 MBM29DS163TE/BE10 Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase Algorithm command sequence the device will automatically program and verify the entire memory for an all zero data pattern prior to electrical erase (Preprogram function) . The system is not required to provide any controls or timings during these operations. The system can determine the status of the erase operation by using DQ7 (Data Polling) , DQ6 (Toggle Bit) , or RY/BY. The chip erase begins on the rising edge of the last CE or WE, whichever happens first in the command sequence and terminates when the data on DQ7 is “1” (See Write Operation Status section.) at which the device returns to read the mode. Chip Erase Time : Sector Erase Time × All sectors + Chip Program Time (Preprogramming) “Embedded EraseTM Algorithm” in “■ FLOW CHART” illustrates the Embedded EraseTM Algorithm using typical command strings and bus operations. Sector Erase Sector erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the “set-up” command. Two more “unlock” write cycles are then followed by the Sector Erase command. The sector address (any address location within the desired sector) is latched on the falling edge of CE or WE whichever happens later, while the command (Data = 30h) is latched on the rising edge of CE or WE which happens first. After time-out of “tTOW” from the rising edge of the last sector erase command, the sector erase operation begins. Multiple sectors are erased concurrently by writing the six bus cycle operations on “MBM29DS163TE/BE Command Definitions” in “■ USER BUS OPERATION”. This sequence is followed with writes of the Sector Erase command to addresses in other sectors desired to be concurrently erased. The time between writes must be less than “tTOW” otherwise that command will not be accepted and erasure does not start. It is recommended that processor interrupts be disabled during this time to guarantee this condition. The interrupts can be reenabled after the last Sector Erase command is written. A time-out of “tTOW” from the rising edge of last CE or WE whichever happens first will initiate the execution of the Sector Erase command (s) . If another falling edge of CE or WE, whichever happens first occurs within the “tTOW” time-out window the timer is reset. (Monitor DQ3 to determine if the sector erase timer window is still open, see section DQ3, Sector Erase Timer.) Any command other than Sector Erase or Erase Suspend during this time-out period will reset the device to the read mode, ignoring the previous command string. Resetting the device once execution has begun will corrupt the data in the sector. In that case, restart the erase on those sectors and allow them to complete. (Refer to the Write Operation Status section for Sector Erase Timer operation.) Loading the sector erase buffer may be done in any sequence and with any number of sectors (0 to 70) . Sector erase does not require the user to program the device prior to erase. The device automatically programs all memory locations in the sector (s) to be erased prior to electrical erase (Preprogram function) . When erasing a sector or sectors the remaining unselected sectors are not affected. The system is not required to provide any controls or timings during these operations. The system can determine the status of the erase operation by using DQ7 (Data Polling) , DQ6 (Toggle Bit) , or RY/BY. The sector erase begins after the “tTOW” time out from the rising edge of CE or WE whichever happens first for the last sector erase command pulse and terminates when the data on DQ7 is “1” (See Write Operation Status section.) at which time the device return to the read mode. Data polling and Toggle Bit must be performed at an address within any of the sectors being erased. Multiple Sector Erase Time : [Sector Erase Time + Sector Program Time (Preprogramming) ] × Number of Sector Erase In case of multiple sector erase across bank boundaries, a read from bank (read-while-erase) can not performe. “Embedded EraseTM Algorithm” in “■ FLOW CHART” illustrates the Embedded EraseTM Algorithm using typical command strings and bus operations. 27 MBM29DS163TE/BE10 Erase Suspend/Resume The Erase Suspend command allows the user to interrupt Sector Erase operation and then perform data reads from or programs to a sector not being erased. This command is applicable ONLY during the Sector Erase operation which includes the time-out period for sector erase. The Erase Suspend command is ignored if written during the Chip Erase operation or Embedded Program Algorithm. Writting the Erase Suspend command (B0h) during the Sector Erase time-out results in immediate termination of the time-out period and suspension of the erase operation. Writing the Erase Resume command (30h) resumes the erase operation. The bank addresses of sector being erased or erase-suspended should be set when writting the Erase Suspend or Erase Resume command. When the Erase Suspend command is written during the Sector Erase operation, the device takes a maximum of “tSPD” to suspend the erase operation. When the device has entered the erase-suspended mode, the RY/BY output pin is at HIGH-Z and the DQ7 bit is at logic “1”, and DQ6 will stop toggling. The user must use the address of the erasing sector for reading DQ6 and DQ7 to determine if the erase operation is suspended. Further writes of the Erase Suspend command are ignored. When the erase operation has been suspended, the device defaults to the erase-suspend-read mode. Reading data in this mode is the same as reading from the standard read mode except that the data must be read from sectors that have not been erase-suspended. Successively reading from the erase-suspended sector while the device is in the erase-suspend-read mode will cause DQ2 to toggle. (See the section on DQ2.) After entering the erase-suspend-read mode, the user can program the device by writing the appropriate command sequence for Program. This program mode is known as the erase-suspend-program mode. Again, programming in this mode is the same as programming in the regular Program mode except that the data must be programmed to sectors that are not erase-suspended. Successively reading from the erase-suspended sector while the device is in the erase-suspend-program mode will cause DQ2 to toggle. The end of the erase-suspended Program operation is detected by the RY/BY output pin, Data polling of DQ7 or by the Toggle Bit I (DQ6) which is the same as the regular Program operation. Note that DQ7 must be read from the Program address while DQ6 can be read from any address within bank being erase-suspended. To resume the operation of Sector Erase, the Resume command (30h) should be written to the bank being erase suspended. Any further writes of the Resume command at this point is ignored. Another Erase Suspend command is written after the chip resumes erasing. Extended Command (1) Fast Mode The device has Fast Mode function. This mode dispenses with the initial two unclock cycles required in the standard program command sequence by writing Fast Mode command into the command register. In this mode, the required bus cycle for programming is two cycles instead of four bus cycles in standard program command. (Do not write erase command in this mode.) The read operation is also executed after exiting this mode. To exit this mode, it is necessary to write Fast Mode Reset command into the command register. The first cycle must contain the bank address. (Refer to “Embedded ProgramTM Algorithm for Fast Mode” in “■ FLOW CHART”.) The VCC active current is required even CE = VIH during Fast Mode. (2) Fast Programming During Fast Mode, the programming can be executed with two bus cycles operation. The Embedded Program Algorithm is executed by writing program set-up command (A0h) and data write cycles (PA/PD) . (Refer to “Embedded ProgramTM Algorithm for Fast Mode” in “■ FLOW CHART”.) (3) CFI (Common Flash Memory Interface) The CFI (Common Flash Memory Interface) specification outlines device and host system software interrogation handshake which allows specific vendor-specified software algorithms to be used for entire families of device. This allows device-independent, JEDEC ID-independent, and forward-and backward-compatible software support for the specified flash device families. Refer to CFI specification in detail. 28 MBM29DS163TE/BE10 The operation is initiated by writing the query command (98h) into the command register. The bank address should be set when writing this command. Then the device information can be read from the bank, and an actual data of memory cell be read from the another bank. Following the command write, a read cycle from specific address retrives device information. Please note that output data of upper byte (DQ15 to DQ8) is “0” in word mode (16 bit) read. Refer to the CFI code table. To terminate operation, it is necessary to write the read/reset command sequence into the register. (See “Command Flash Memory Interface Code” in “■ FLEXIBLE SECTOR-ERASE ARCHITECTURE”.) HiddenROM Region The HiddenROM feature provides Flash memory region that the system may access through a new command sequence. This is primarily intended for customers who wish to use an Electronic Serial Number (ESN) in the device with the ESN protected against modification. Once the HiddenROM region is protected, any further modification of that region is not allowed. This ensures the security of the ESN once the product is shipped to the field. The HiddenROM region is 64 K bytes in length and is stored at the same address of the 8 KB ×8 sectors. The MBM29DS163TE occupies the address of the byte mode 1F0000h to 1FFFFFh (word mode 0F8000h to 0FFFFFh) and the MBM29DS163BE type occupies the address of the byte mode 000000h to 00FFFFh (word mode 000000h to 007FFFh) . After the system writes the Enter HiddenROM command sequence, the system reads the HiddenROM region by using the addresses normally occupied by the boot sectors. That is, the device sends all commands that would normally be sent to the boot sectors to the HiddenROM region. This mode of operation continues until the system issues the Exit HiddenROM command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to sending commands to the boot sectors. HiddenROM Entry Command The device has HiddenROM area with One Time Protect function. This area is to enter the security code and to unable the change of the code once set. Program/erase is possible in this area until it becomes protected. However once it is protected, it is impossible to unprotect, use this command with caution. HiddenROM area is 64 K Byte and in the same address area of 8 KB sector. The address of top boot is 1F0000h to 1FFFFFh at byte mode (0F8000h to 0FFFFFh at word mode) and the bottom boot is 000000h to 00FFFFh at byte mode (000000h to 007FFFh at word mode) . These areas are normally the boot block area (8KB ×8 sector) . Therefore, write the HiddenROM entry command sequence to enter the HiddenROM area. This is called HiddenROM mode as the HiddenROM area appears. Sector other than the boot block area could be read during HiddenROM mode. Read/program/earse of the HiddenROM area is allowed during HiddenROM mode. Write the HiddenROM reset command sequence to exit the HiddenROM mode. The bank address of the HiddenROM should be set on the third cycle of this reset command sequence. HiddenROM Program Command To program data to HiddenROM area, write the HiddenROM program command sequence during HiddenROM mode. This command is the same as the program command in usual except to write the command during HiddenROM mode. Therefore the detection of completion method is the same as described, using the DQ7 data poling, DQ6 toggle bit and RY/BY pin. Need to pay attention to the address to be programmed. If the address other than the HiddenROM area is selected to program, data of the address will be changed. HiddenROM Erase Command To erase the HiddenROM area, write the HiddenROM erase command sequence during HiddenROM mode. This command is same as the sector erase command in the past except to write the command during HiddenROM mode. Therefore the detection of completion method is the same as in the past, using the DQ7 data poling, DQ6 toggle bit and RY/BY pin. Need to pay attention to the sector address to be erased. If the sector address other than the HiddenROM area is selected, the data of the sector will be changed. 29 MBM29DS163TE/BE10 HiddenROM Protect Command There are two methods to protect the HiddenROM area. One is to write the sector group protect setup command (60h) , set the sector address in the HiddenROM area and (A6, A1, A0) = (0, 1, 0) , and write the sector group protect command (60h) during the HiddenROM mode. The same command sequence could be used because, it is just as the extension sector group protect in the past except that it is in the HiddenROM mode and it does not apply high voltage to RESET pin. Please refer to “Function Explanation Extentended Sector Group Protection” for details of extention sector group protect setting. The other method is to apply high voltage (VID) to A9 and OE, set the sector address in the HiddenROM area and (A6, A1, A0) = (0, 1, 0) , and apply the write pulse during the HiddenROM mode. To verify the protect circuit, apply high voltage (VID) to A9, specify (A6, A1, A0) = (0, 1, 0) and the sector address in the HiddenROM area, and read. When “1” appears on DQ0, the protect setting is completed. “0” will appear on DQ0 if it is not protected. Please apply write pulse again. The same command sequence could be used for the above method because other than the HiddenROM mode, it is the same with the sector group protect in the past. Please refer to “Function Explanation Sector Group Protection” for details of the sector group protect setting. Other sector group will be effected if the address other than those for HiddenROM area is selected for the sector group address. Once it is protected, protection cannot be cancelled; so pay the closest attention. Write Operation Status Detailed in “Hardware Sequence Flags” Table are all the status flags that determine the status of the bank for the current mode operation. The read operation from the bank which does not operate Embedded Algorithm returns data of memory cells. These bits offer a method for determining whether a Embedded Algorithm is properly completed. The information on DQ2 is address sensitive. This means that if an address from an erasing sector is consectively read, then the DQ2 bit will toggle. However, DQ2 will not toggle if an address from a nonerasing sector is consectively read. This allows users to determine which sectors are in erase and which are not. The status flag is not output from bank (non-busy bank) which does not execute Embedded Algorithm. For example, there is bank (busy bank) now executing Embedded Algorithm. When the read sequence is [1] < busy bank > , [2] < non-busy bank > , [3] < busy bank > , the DQ6 is toggling in the case of [1] and [3]. In case of [2], the data of memory cells are outputted. In the erase-suspend read mode with the same read sequence, DQ6 will not be toggled in the [1] and [3]. In the erase suspend read mode, DQ2 is toggled in the [1] and [3]. In case of [2], the data of memory cell is outputted. Hardware Sequence Flags Table Status Embedded Program Algorithm Embedded Erase Algorithm In Progress Program Suspend Read Program (Program Suspended Sector) Suspended Program Suspend Read Mode (Non-Program Suspended Sector) Erase Suspend Read (Erase Suspended Sector) Erase Erase Suspend Read Suspended (Non-Erase Suspended Sector) Mode Erase Suspend Program (Non-Erase Suspended Sector) Embedded Program Algorithm Embedded Erase Algorithm Exceeded Time Limits Erase Erase Suspend Program Suspended (Non-Erase Suspended Sector) Mode 30 DQ7 DQ6 DQ5 DQ3 DQ2 DQ7 Toggle 0 0 1 0 Toggle 0 1 Toggle* Data Data Data Data Data Data Data Data Data Data 1 1 Data Data DQ7 Toggle 0 0 1* DQ7 Toggle 1 0 1 0 Toggle 1 1 N/A DQ7 Toggle 1 0 N/A 0 0 Data Data Toggle Data MBM29DS163TE/BE10 * : Successive reads from the erasing or erase-suspend sector cause DQ2 to toggle. Reading from non-erase suspend sector address indicates logic “1” at the DQ2 bit. Notes : • DQ0 and DQ1 are reserve pins for future use. • DQ4 is Fujitsu internal use only. DQ7 Data Polling The device features Data Polling as a method to indicate to the host that the Embedded Algorithms are in progress or completed. During the Embedded Program Algorithm an attempt to read device will produce a complement of data last written to DQ7. Upon completion of the Embedded Program Algorithm, an attempt to read device will produce true data last written to DQ7. During the Embedded Erase Algorithm, an attempt to read device will produce a “0” at the DQ7 output. Upon completion of the Embedded Erase Algorithm an attempt to read device will produce a “1” on DQ7. The flowchart for Data Polling (DQ7) is shown in “Data Polling Algorithm” in “■ FLOW CHART”. For programming, the Data Polling is valid after the rising edge of the fourth write pulse in the four write pulse sequence. For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth write pulse in the six write pulse sequence. Data Polling must be performed at sector address of sectors being erased, not protected sectors. Otherwise, the status may be invalid. If a program address falls within a protected sector, Data Polling on DQ7 is active for approximately 1 µs, then that bank returns to the read mode. After an erase command sequence is written, if all sectors selected for erasing are protected, Data Polling on DQ7 is active for approximately 400 µs, then the bank returns to read mode. Once the Embedded Algorithm operation is close to completion, the device data pins (DQ7) may change asynchronously while the output enable (OE) is asserted low. This means that device is driving status information on DQ7 at one instant of time and then that byte’s valid data at the next instant of time. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if device has completed the Embedded Algorithm operation and DQ7 has a valid data, data outputs on DQ0 to DQ6 may be still invalid. The valid data on DQ0 to DQ7 will be read on the successive read attempts. The Data Polling feature is active only during the Embedded Programming Algorithm, Embedded Erase Algorithm or sector erase time-out. (See “Hardware Sequence Flags” Table.) See “Data Polling during Embedded Algorithm Operation Timing Diagram” in “■ TIMING DIAGRAM” for the Data Polling timing specifications and diagrams. DQ6 Toggle Bit I The device also features the “Toggle Bit I” as a method to indicate to the host system that the Embedded Algorithms are in progress or completed. During Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from the device will results in DQ6 toggling between one and zero. Once the Embedded Program or Erase Algorithm cycle is completed, DQ6 will stop toggling and valid data will be read on the next successive attempts. During programming, the Toggle Bit I is valid after the rising edge of the fourth write pulse in the four write pulse sequence. For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth write pulse in the six write pulse sequence. The Toggle Bit I is active during the sector time out. In programming, if the sector being written is protected, the toggle bit will toggle for about 1 µs and then stop toggling with data unchanged. In erase, device will erase all selected sectors except for ones that are protected. If all selected sectors are protected, the chip will toggle the toggle bit for about 400 µs and then drop back into read mode, having data unchanged. Either CE or OE toggling will cause DQ6 to toggle. The system can use DQ6 to determine whether a sector is actively erased or is erase-suspended. When a bank is actively erased (that is, the Embedded Erase Algorithm is in progress) , DQ6 toggles. When a bank enters the Erase Suspend mode, DQ6 stops toggling. Successive read cycles during erase-suspend-program cause DQ6 to toggle.To operate toggle bit function properly, CE or OE must be high when bank address is changed. 31 MBM29DS163TE/BE10 See “Toggle Bit during Embedded Algorithm Operation Timing Diagram” in “■ TIMING DIAGRAM” for the Toggle Bit I timing specifications and diagrams. DQ5 Exceeded Timing Limits DQ5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count) . Under these conditions DQ5 will produce a “1”. This is a failure condition which indicates that the program or erase cycle was not successfully completed. Data Polling is the only operating function of device under this condition. The CE circuit will partially power down device under these conditions (to approximately 2 mA) . The OE and WE pins will control the output disable functions as described in MBM29DS163TE/BE User Bus Operations (BYTE = VIH)” Table and “MBM29DS163TE/BE User Bus Operations (BYTE = VIL)” Table at “■ DEVICE BUS OPERATION” The DQ5 failure condition may also appear if a user tries to program a non blank location without pre-erase. In this case the device locks out and never complete the Embedded Algorithm operation. Hence, the system never read valid data on DQ7 bit and DQ6 never stop toggling. Once device has exceeded timing limits, the DQ5 bit will indicate a “1.” Please note that this is not a device failure condition since device was incorrectly used. If this occurs, reset device with command sequence. DQ3 Sector Erase Timer After completion of the initial sector erase command sequence sector erase time-out will begin. DQ3 will remain low until the time-out is completed. Data Polling and Toggle Bit are valid after the initial sector erase command sequence. If Data Polling or the Toggle Bit I indicates device has been written with a valid erase command, DQ3 may be used to determine if the sector erase timer window is still open. If DQ3 is high (“1”) the internally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by Data Polling or Toggle Bit I. If DQ3 is low (“0”) , the device will accept additional sector erase commands. To insure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent Sector Erase command. If DQ3 were high on the second status check, the command may not have been accepted. See “Hardware Sequence Flags” Table : Hardware Sequence Flags. DQ2 Toggle Bit II This toggle bit II, along with DQ6, can be used to determine whether the device is in the Embedded Erase Algorithm or in Erase Suspend. Successive reads from the erasing sector will cause DQ2 to toggle during the Embedded Erase Algorithm. If the device is in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause DQ2 to toggle. When the device is in the erase-suspended-program mode, successive reads from the byte address of the non-erase suspended sector will indicate a logic “1” at the DQ2 bit. DQ6 is different from DQ2 in that DQ6 toggles only when the standard program or Erase, or Erase Suspend Program operation is in progress. The behavior of these two status bits, along with that of DQ7, is summarized as follows : For example, DQ2 and DQ6 can be used together to determine if the erase-suspend-read mode is in progress. (DQ2 toggles while DQ6 does not.) See also “Toggle Bit Status” and “DQ2 vs. DQ6” in “■ TIMING DIAGRAM”. Furthermore, DQ2 can also be used to determine which sector is being erased. When device is in the erase mode, DQ2 toggles if this bit is read from an erasing sector. To operate toggle bit function properly, CE or OE must be high when bank address is changed. Reading Toggle Bits DQ6/DQ2 Whenever the system initially begins reading toggle bit status, it must read DQ7 to DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, a system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the 32 MBM29DS163TE/BE10 first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7 to DQ0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5) . If it is the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation. (Refer to “Toggle Bit Algorithm” in “■ FLOW CHART”.) Table 11 Toggle Bit Status DQ7 DQ6 DQ2 DQ7 Toggle 1 Erase 0 Toggle Toggle* Erase-Suspend Read (Erase-Suspended Sector) 1 1 Toggle DQ7 Toggle 1* Mode Program Erase-Suspend Program * : Successive reads from the erasing or erase-suspend sector will cause DQ2 to toggle. Reading from non-erase suspend sector address will indicate logic “1” at the DQ2 bit. RY/BY Ready/Busy The device provides a RY/BY open-drain output pin as a way to indicate to the host system that Embedded Algorithms are either in progress or has been completed. If output is low, device is busy with either a program or erase operation. If output is high, device is ready to accept any read/write or erase operation. When RY/BY pin is low, device will not accept any additional program or erase commands. If the device is placed in an Erase Suspend mode, RY/BY output will be high. During programming, RY/BY pin is driven low after the rising edge of the fourth write pulse. During an erase operation, RY/BY pin is driven low after the rising edge of the sixth write pulse. RY/BY pin will indicate a busy condition during RESET pulse. Refer to “RY/BY Timing Diagram during Program/Erase Operations” and “RESET, RY/BY Timing Diagram” in “■ TIMING DIAGRAM” for a detailed timing diagram. RY/BY pin is pulled high in standby mode. Since this is an open-drain output, RY/BY pins can be tied together in parallel with a pull-up resistor to VCC. Byte/Word Configuration BYTE pin selects byte (8-bit) mode or word (16-bit) mode for the device. When this pin is driven high, device operates in word (16-bit) mode. Data is read and programmed at DQ15 to DQ0. When this pin is driven low, device operates in byte (8-bit) mode. Under this mode, the DQ15/A-1 pin becomes the lowest address bit, and DQ14 to DQ8 bits are tri-stated. However, the command bus cycle is always an 8-bit operation and hence commands are written at DQ15 to DQ8 and DQ7 to DQ0 bits are ignored. Refer to “Word Mode Configuration Timing”, “Byte Mode Configuration Timing Diagram” and “BYTE Timing Diagram for Write Operations” in “■ TIMING DIAGRAM” for the timing diagram. Data Protection The device is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. During power up device automatically resets internal state 33 MBM29DS163TE/BE10 machine in Read mode. Also, with its control register architecture, alteration of memory contents only occurs after successful completion of specific multi-bus cycle command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting from VCC power-up and power-down transitions or system noise. Write Pulse “Glitch” Protection Noise pulses of less than 3 ns (typical) on OE, CE, or WE will not initiate a write cycle. Logical Inhibit Writing is inhibited by holding any one of OE = VIL, CE = VIH, or WE = VIH. To initiate a write cycle CE and WE must be a logical zero while OE is a logical one. Power-Up Write Inhibit Power-up of the device with WE = CE = VIL and OE = VIH will not accept commands on the rising edge of WE. The internal state machine is automatically reset to the read mode on power-up. 34 MBM29DS163TE/BE10 ■ ABSOLUTE MAXIMUM RATINGS Parameter Rating Symbol Unit Min Max Tstg −55 +125 °C TA −40 +85 °C VIN, VOUT −0.5 VCC + 0.5 V Power Supply Voltage *1 VCC −0.5 +3.0 V A9, OE, and RESET *2 VIN −0.5 +11.5 V 3 VACC −0.5 +10.5 V Storage Temperature Ambient Temperature with Power Applied Voltage with Respect to Ground All pins except A9, OE, and RESET *1 WP/ACC * *1 : Minimum DC voltage on input or I/O pins is −0.5 V. During voltage transitions, input or I/O pins may undershoot VSS to −2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCC +0.5 V. During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods of up to 20 ns. *2 : Minimum DC input voltage on A9, OE and RESET pins is −0.5 V. During voltage transitions, A9, OE and RESET pins may undershoot VSS to −2.0 V for periods of up to 20 ns. Voltage difference between input and supply voltage (VIN-VCC) does not exceed +9.0 V.Maximum DC input voltage on A9, OE and RESET pins is +11.5 V which may positive overshoot to +12.5 V for periods of up to 20 ns. *3 : Minimum DC input voltage on WP/ACC pin is −0.5 V. During voltage transitions, WP/ACC pin may undershoot VSS to −2.0 V for periods of up to 20 ns. Maximum DC input voltage on WP/ACC pin is +10.5 V which may positive overshoot to +12.0 V for periods of up to 20 ns when Vcc is applied. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. ■ RECOMMENDED OPERATING CONDITIONS Parameter Symbol Ranges Min Max Unit Ambient Temperature TA −40 +85 °C Power Supply Voltage VCC +1.8 +2.2 V Note : Operating ranges define those limits between which the functionality of the device is guaranteed. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. 35 MBM29DS163TE/BE10 ■ MAXIMUM OVERSHOOT/MAXIMUM UNDERSHOOT 0.2 × VCC 20 ns 20 ns −0.5 V −2.0 V 20 ns Maximum Undershoot Waveform 20 ns VCC + 2.0 V VCC + 0.5 V 0.8 × VCC 20 ns 20 ns Maximum Overshoot Waveform 1 20 ns +12.0 V +11.0 V VCC + 0.5 V 20 ns 20 ns Note : This waveform is applied for A9, OE, and RESET. Maximum Overshoot Waveform 2 36 MBM29DS163TE/BE10 ■ DC CHARACTERISTICS Parameter Symbol Test Conditions Min Max Unit Input Leakage Current ILI VIN = VSS to VCC, VCC = VCC Max −1.0 +1.0 µA Output Leakage Current ILO VOUT = VSS to VCC, VCC = VCC Max −1.0 +1.0 µA A9, OE, RESET Inputs Leakage Current ILIT VCC = VCC Max A9, OE, RESET = 11.0 V 35 µA CE = VIL, OE = VIH, f = 5 MHz VCC Active Current *1 ICC1 CE = VIL, OE = VIH, f = 1 MHz Byte Word Byte Word 16 16 4 4 mA mA VCC Active Current *2 ICC2 CE = VIL, OE = VIH 25 mA VCC Current (Standby) ICC3 VCC = VCC Max, CE = VCC ± 0.3 V, RESET = VCC ± 0.3 V 5 µA VCC Current (Standby, Reset) ICC4 VCC = VCC Max, WE/ACC = VCC ± 0.3 V, RESET = VSS ± 0.3 V 5 µA VCC Current (Automatic Sleep Mode) *3 ICC5 VCC = VCC Max, CE = VSS ± 0.3 V, RESET = VCC ± 0.3 V VIN = VCC ± 0.3 V or VSS ± 0.3 V 5 µA VCC Active Current *5 (Read-While-Program) ICC6 CE = VIL, OE = VIH Byte 25 Word 25 VCC Active Current *5 (Read-While-Erase) ICC7 CE = VIL, OE = VIH Byte 25 Word 25 VCC Active Current (Erase-Suspend-Program) ICC8 CE = VIL, OE = VIH 15 mA WP/ACC Accelerated Program Current IACC VCC = VCC Max WP/ACC = VACC Max 10 mA Input Low Level VIL −0.5 0.2 × VCC V Input High Level VIH 0.8 × VCC VCC + 0.3 V VACC 8.5 9.5 V Voltage for Autoselect and Sector Protection (A9, OE, RESET) *4 VID 10.0 11.0 V Output Low Voltage Level VOL IOL = 100 µA, VCC = VCC Min 0.1 V Output High Voltage Level VOH IOH = −100 µA VCC − 0.1 V Voltage for WP/ACC Sector Protection/Unprotection and Program Acceleration *4 mA mA *1 : ICC current listed includes both the DC operating current and the frequency dependent component. *2 : IICC active while Embedded Algorithm (program or erase) is in progress. *3 : Automatic sleep mode enables the low power mode when address remain stable for 150 ns. *4 : Applicable for only VCC applying. *5 : Embedded Algorithm (program or erase) is in progress. (@5 MHz) 37 MBM29DS163TE/BE10 ■ AC CHARACTERISTICS • Read Only Operations Characteristics Parameter Symbol JEDEC Standard Read Cycle Time tAVAV tRC Address to Output Delay tAVQV tACC Chip Enable to Output Delay tELQV tCE Output Enable to Output Delay tGLQV tOE Chip Enable to Output High-Z tEHQZ Output Enable to Output High-Z Output Hold Time From Addresses, CE or OE, Whichever Occurs First Value * Unit Min Max 100 ns CE = VIL OE = VIL 100 ns OE = VIL 100 ns 35 ns tDF 30 ns tGHQZ tDF 30 ns tAXQX tOH 0 ns RESET Pin Low to Read Mode tREADY 20 µs CE or BYTE Switching Low or High tELFL tELFH 5 ns * : Test Conditions : Output Load : CL = 30 pF Input rise and fall times : 5 ns Input pulse levels : 0.0 V or 2.0 V Timing measurement reference level Input : 0.5 × VCCf Output : 0.5 × VCCf Device Under Test CL Note : CL = 30 pF including jig capacitance 38 Condition MBM29DS163TE/BE10 • Write/Erase/Program Operations Parameter Symbol Value *1 Unit JEDEC Standard Min Typ Max Write Cycle Time tAVAV tWC 100 ns Address Setup Time tAVWL tAS 0 ns tASO 15 ns tWLAX tAH 50 ns tAHT 0 ns Data Setup Time tDVWH tDS 50 ns Data Hold Time tWHDX tDH 0 ns tOEH 0 ns 10 ns CE High During Toggle Bit Polling tCEPH 20 ns OE High During Toggle Bit Polling tOEPH 20 ns Read Recover Time Before Write tGHWL tGHWL 0 ns Read Recover Time Before Write tGHEL tGHEL 0 ns CE Setup Time tELWL tCS 0 ns WE Setup Time tWLEL tWS 0 ns CE Hold Time tWHEH tCH 0 ns WE Hold Time tEHWH tWH 0 ns Write Pulse Width tWLWH tWP 50 ns CE Pulse Width tELEH tCP 50 ns Write Pulse Width High tWHWL tWPH 35 ns CE Pulse Width High tEHEL tCPH 35 ns tWHWH1 tWHWH1 8 µs 16 µs tWHWH2 tWHWH2 1 s Address Setup Time to OE Low During Toggle Bit Polling Address Hold Time Address Hold Time from CE or OE High During Toggle Bit Polling Output Enable Hold Time Programming Operation Read Toggle and Data Polling Byte Word Sector Erase Operation*1 tVCS 50 µs ID 2 tVIDR 500 ns ACC 3 tVACCR 500 ns tVLHT 4 µs VCC Setup Time Rise Time to V * Rise Time to V * Voltage Transition Time*2 tWPP 100 µs 2 tOESP 4 µs 2 tCSP 4 µs Recover Time From RY/BY tRB 0 ns RESET Pulse Width tRP 500 ns Write Pulse Width*2 OE Setup Time to WE Active* CE Setup Time to WE Active* (Continued) 39 MBM29DS163TE/BE10 (Continued) Parameter Value *1 Unit JEDEC Standard Min Typ Max RESET High Level Period Before Read tRH 200 ns BYTE Switching Low to Output High-Z tFLQZ 30 ns BYTE Switching High to Output Active tFHQV 90 ns Program/Erase Valid to RY/BY Delay tBUSY 90 ns Delay Time from Embedded Output Enable tEOE 90 ns Erase Time-out Time tTOW 50 µs Erase Suspend Transition Time tSPD 20 µs Power On / Off Time tPS 100 ns *1 : Does not include the preprogramming time. *2 : For Sector Group Protection operation. *3 : For Accelerated Program operation. 40 Symbol MBM29DS163TE/BE10 ■ ERASE AND PROGRAMMING PERFORMANCE Limit Parameter Unit Min Typ Max Sector Erase Time 1 10 s Word Programming Time 16 360 µs Byte Programming Time 8 300 µs Chip Programming Time 50 s 100,000 cycle Program/Erase Cycle Comments Excludes programming time prior to erasure Excludes system-level overhead Excludes system-level overhead ■ TSOP (1) PIN CAPACITANCE Parameter Input Capacitance Symbol CIN Test Setup Typ Max Unit VIN = 0 6.0 7.5 pF Output Capacitance COUT VOUT = 0 8.5 12.0 pF Control Pin Capacitance CIN2 VIN = 0 8.0 11.0 pF WP/ACC Pin Capacitance CIN3 VIN = 0 21.5 22.5 pF Typ Max Unit VIN = 0 6.0 7.5 pF Notes : • Test conditions TA = + 25 °C, f = 1.0 MHz • DQ15/A-1 pin capacitance is stipulated by output capacitance. ■ FBGA PIN CAPACITANCE Parameter Input Capacitance Symbol CIN Test Setup Output Capacitance COUT VOUT = 0 8.5 12.0 pF Control Pin Capacitance CIN2 VIN = 0 8.0 10.0 pF WP/ACC Pin Capacitance CIN3 VIN = 0 17.0 18.0 pF Notes : • Test conditions TA = + 25 °C, f = 1.0 MHz • DQ15/A-1 pin capacitance is stipulated by output capacitance. 41 MBM29DS163TE/BE10 ■ TIMING DIAGRAM • Key to Switching Waveforms WAVEFORM INPUTS OUTPUTS Must Be Steady Will Be Steady May Change from H to L Will Change from H to L May Change from L to H Will Change from L to H "H" or "L" Any Change Permitted Changing State Unknown Does Not Apply Center Line is HighImpedance "Off" State tRC Address Address Stable tACC CE tOE tDF OE tOEH WE tOH tCE Data High-Z Outputs Output Valid Read Operation Timing Diagram 42 High-Z MBM29DS163TE/BE10 tRC Address Address Stable tACC CE tRH tRP tRH tCE RESET tOH High-Z Outputs Output Valid Hardware Reset/Read Operation Timing Diagram tPS tPS RESET VCC VCC 1.8 V 1.8 V 0V Address Valid Data In Valid Data Out Data tRH tACC Power On/Off Timing Diagram 43 MBM29DS163TE/BE10 3rd Bus Cycle Data Polling 555h Address tWC PA tAS PA tRC tAH CE tCS tCH tCE OE tGHWL tWP tOE tWPH tWHWH1 WE Data A0h PD DQ7 DOUT Notes : • PA is address of the memory location to be programmed. • PD is data to be programmed at byte address. • DQ7 is the output of the complement of the data written to the device. • DOUT is the output of the data written to the device. • Figure indicates the last two bus cycles out of four bus cycle sequence. • These waveforms are for the ×16 mode (the addresses differ from ×8 mode) . Alternate WE Controlled Program Operation Timing Diagram 44 tOH tDF tDS tDH DOUT MBM29DS163TE/BE10 3rd Bus Cycle Data Polling 555h Address tWC PA tAS PA tAH WE tWS tWH OE tGHEL tCP tCPH tWHWH1 CE tDS Data A0h tDH PD DQ7 DOUT Notes : • PA is address of the memory location to be programmed. • PD is data to be programmed at byte address. • DQ7 is the output of the complement of the data written to the device. • DOUT is the output of the data written to the device. • Figure indicates the last two bus cycles out of four bus cycle sequence. • These waveforms are for the ×16 mode (the addresses differ from ×8 mode) . Alternate CE Controlled Program Operation Timing Diagram 45 MBM29DS163TE/BE10 555h Address tWC 2AAh tAS 555h 555h 2AAh SA* tAH CE tCS tCH OE tGHWL tWP tWPH tDS tDH WE AAh 30h for Sector Erase 55h 80h AAh 55h 10h Data tVCS VCC * : SA is the sector address for Sector Erase. Addresses = 555h (Word) , AAAh (Byte) for Chip Erase. Note: These waveforms are for the ×16 mode (the addresses differ from ×8 mode) . Chip/Sector Erase Operation Timing Diagram 46 MBM29DS163TE/BE10 CE tCH tDF tOE OE tOEH WE tCE * Data DQ7 DQ7 DQ7 = Valid Data High-Z tWHWH1 or 2 DQ6 to DQ0 DQ6 to DQ0 = Output Flag Data tBUSY DQ6 to DQ0 Valid Data High-Z tEOE RY/BY * : DQ7 = Valid Data (the device has completed the Embedded operation) . Data Polling during Embedded Algorithm Operation Timing Diagram 47 MBM29DS163TE/BE10 Address tAHT tASO tAHT tAS CE tCEPH WE tOEPH tOEH tOEH OE tDH tOE tCE * DQ6/DQ2 Data Toggle Data Toggle Data Toggle Data Stop Toggling tBUSY RY/BY * : DQ6 stops toggling (the device has completed the Embedded operation) . Toggle Bit I during Embedded Algorithm Operation Timing Diagram 48 Output Valid MBM29DS163TE/BE10 Address Read tRC Command tWC Read tRC Command tWC Read tRC Read tRC BA1 BA2 (555h) BA1 BA2 (PA) BA1 BA2 (PA) tAS tACC tAH tAS tAHT tCE CE tCEPH tOE OE tGHWL tOEH tWP tDF WE tDH tDS Valid Output DQ Valid Input tDF Valid Output (A0h) Valid Input Valid Output Status (PD) Notes : • This is example of Read for Bank 1 and Embedded Algorithm (program) for Bank 2. • BA1 : Address corresponding to Bank 1 • BA2 : Address corresponding to Bank 2 Bank-to-Bank Read/Write Timing Diagram Enter Embedded Erasing WE Erase Suspend Erase Enter Erase Suspend Program Erase Suspend Read Erase Suspend Program Erase Resume Erase Suspend Read Erase Erase Complete DQ6 DQ2 Toggle DQ2 and DQ6 with OE or CE Note : DQ2 is read from the erase-suspended sector. DQ2 vs. DQ6 49 MBM29DS163TE/BE10 CE Rising edge of the last write signal WE Entire programming or erase operations RY/BY tBUSY RY/BY Timing Diagram during Program/Erase Operations WE RESET tRB tRP RY/BY tREADY RESET, RY/BY Timing Diagram 50 MBM29DS163TE/BE10 CE tCE BYTE Data Output (DQ7 to DQ0) DQ14 to DQ0 tELFH Data Output (DQ14 to DQ0) tFHQV A-1 DQ15/A-1 DQ15 Word Mode Configuration Timing Diagram CE BYTE DQ14 to DQ0 tELFL Data Output (DQ7 to DQ0) Data Output (DQ14 to DQ0) tACC DQ15/A-1 A-1 DQ15 tFLQZ Byte Mode Configuration Timing Diagram Falling edge of the last write signal CE or WE Input Valid BYTE tSET (tAS) tHOLD (tAH) BYTE Timing Diagram for Write Operations 51 MBM29DS163TE/BE10 A19, A18, A17 A16, A15, A14 A13, A12 SPAX SPAY A6, A0 A1 VID VIH A9 tVLHT VID VIH OE tVLHT tVLHT tVLHT tWPP WE tOESP tCSP CE 01h Data tOE tVCS VCC SPAX : Sector Group Address to be protected SPAY : Sector Group Address to be protected Note : A-1 is VIL on byte mode. Sector Group Protection Timing Diagram 52 MBM29DS163TE/BE10 VCC tVIDR tVCS tVLHT VID VIH RESET CE WE tVLHT Program or Erase Command Sequence tVLHT RY/BY Unprotection Period Temporary Sector Group Unprotection Timing Diagram 53 MBM29DS163TE/BE10 VCC tVCS RESET tVLHT tVIDR tWC Add tWC SPAX SPAX SPAY A0 A1 A6 CE OE TIME-OUT tWP WE Data 60h 60h 40h 01h tOE SPAX : Sector Group Address to be protected SPAY : Next Sector Group Address to be protected TIME-OUT : Time-Out window = 250 µs (Min) Extended Sector Group Protection Timing Diagram 54 60h MBM29DS163TE/BE10 VCC tVCS tVACCR tVLHT VACC VIH WP/ACC CE WE tVLHT tVLHT Program Command Sequence RY/BY Acceleration Period Accelerated Program Timing Diagram 55 MBM29DS163TE/BE10 ■ FLOW CHART EMBEDDED ALGORITHM Start Write Program Command Sequence (See Below) Data Polling No Increment Address No Verify Data ? Yes Embedded Program Algorithm in progress Last Address ? Yes Programming Completed Program Command Sequence (Address/Command): 555h/AAh 2AAh/55h 555h/A0h Program Address/Program Data Notes : • The sequence is applied for × 16 mode. • The addresses differ from × 8 mode. Embedded ProgramTM Algorithm 56 MBM29DS163TE/BE10 EMBEDDED ALGORITHM Start Write Erase Command Sequence (See Below) Data Polling No Data = FFh ? Yes Embedded Erase Algorithm in progress Erasure Completed Chip Erase Command Sequence* (Address/Command): Individual Sector/Multiple Sector* Erase Command Sequence (Address/Command): 555h/AAh 555h/AAh 2AAh/55h 2AAh/55h 555h/80h 555h/80h 555h/AAh 555h/AAh 2AAh/55h 2AAh/55h 555h/10h Sector Address /30h Sector Address /30h Sector Address /30h Additional sector erase commands are optional. * : • The sequence is applied for × 16 mode. • The addresses differ from × 8 mode. Embedded EraseTM Algorithm 57 MBM29DS163TE/BE10 VA = Address for programming = Any of the sector addresses within the sector being erased during sector erase or multiple erases operation = Any of the sector addresses within the sector not being protected during sector erase or multiple sector erases operation Start Read Byte (DQ7 to DQ0) Addr. = VA DQ7 = Data? Yes No No DQ5 = 1? Yes Read Byte (DQ7 to DQ0) Addr. = VA DQ7 = Data? * No Fail Yes Pass * : DQ7 is rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5. Data Polling Algorithm 58 MBM29DS163TE/BE10 Start Read DQ7 to DQ0 Addr. = VA *1 VA = Bank addrerss being executed Embedded Algorithm Read DQ7 to DQ0 Addr. = VA DQ6 = Toggle? No Yes No DQ5 = 1? Yes *1, *2 Read DQ7 to DQ0 Addr. = VA Read DQ7 to DQ0 Addr. = VA DQ6 = Toggle? *1, *2 No Yes Program/Erase Operation Not Complete.Write Reset Command Program/Erase Operation Complete *1 : Read toggle bit twice to determine whether it is toggling. *2 : Recheck toggle bit because it may stop toggling as DQ5 changes to “1”. Toggle Bit Algorithm 59 MBM29DS163TE/BE10 Start Setup Sector Group Addr. A19, A18, A17,A16, A15, A14, A13, A12 ( ) PLSCNT = 1 OE = VID, A9 = VID, A6 = CE = VIL, RESET = VIH A0 = VIL, A1 = VIH Activate WE Pulse Increment PLSCNT Time out 100 µs WE = VIH, CE = OE = VIL (A9 should remain VID) Read from Sector Group = SPA, A0 = VIL, * ( Addr. A1 = VIH, A6 = VIL ) No PLSCNT = 25? Yes Remove VID from A9 Write Reset Command No Data = 01h? Yes Protect Another Sector Group ? No Device Failed Remove VID from A9 Write Reset Command Sector Group Protection Completed * : A-1 is V IL on byte mode. Sector Group Protection Algorithm 60 Yes MBM29DS163TE/BE10 Start RESET = VID *1 Perform Erase or Program Operations RESET = VIH Temporary Sector Group Unprotection Completed *2 *1 : All protected sectors are unprotected. *2 : All previously protected sectors are protected once again. Temporary Sector Group Unprotection Algorithm 61 MBM29DS163TE/BE10 Start RESET = VID Wait to 4 µs Device is Operating in Temporary Sector Group Unprotection Mode No Extended Sector Group Protection Entry? Yes To Setup Sector Group Protection Write XXXh/60h PLSCNT = 1 To Sector Group Protection Write SGA/60h (A0 = VIL, A1 = VIH, A6 = VIL) Time Out 250 µs To Verify Sector Group Protection Write SGA/40h (A0 = VIL, A1 = VIH, A6 = VIL) Increment PLSCNT Read from Sector Group Address (A0 = VIL, A1 = VIH, A6 = VIL)* No PLSCNT = 25? Yes Remove VID from RESET Write Reset Command No Setup Next Sector Group Address Data = 01h? Yes Yes Protection Other Sector Group ? No Remove VID from RESET Write Reset Command Device Failed Sector Group Protection Completed * : A-1 is V IL on byte mode. Extended Sector Group Protection Algorithm 62 MBM29DS163TE/BE10 FAST MODE ALGORITHM Start 555h/AAh Set Fast Mode 2AAh/55h 555h/20h XXXh/A0h Program Address/Program Data Data Polling Device In Fast Program Verify Data? No Yes Increment Address No Last Address ? Yes Programming Completed (BA) XXXh/90h Reset Fast Mode XXXh/F0h Embedded ProgrammingTM Algorithm for Fast Mode 63 MBM29DS163TE/BE10 ■ ORDERING INFORMATION Standard Products Fujitsu standard products are available in several packages. The order number is formed by a combination of : MBM29DS163 T E 10 TN PACKAGE TYPE TN = 48-Pin Thin Small Outline Package (TSOP) Normal Bend TR = 48-Pin Thin Small Outline Package (TSOP) Reverse Bend PBT = 48-Ball Fine pitch Ball Grid Array Package (FBGA) SPEED OPTION See Product Selector Guide DEVICE REVISION BOOT CODE SECTOR ARCHITECTURE T = Top sector B = Bottom sector DEVICE NUMBER/DESCRIPTION MBM29DS163 16 Mega-bit (2 M × 8-Bit or 1 M × 16-Bit) CMOS Flash Memory 1.8 V-only Read, Program, and Erase Valid Combinations MBM29DS163TE/BE 64 10 Valid Combinations TN TR PBT Valid Combinations list configurations planned to be supported in volume for this device. Consult the local Fujitsu sales office to confirm availability of specific valid combinations and to check on newly released combinations. MBM29DS163TE/BE10 ■ PACKAGE DIMENSIONS Note 1) * : Values do not include resin protrusion. Resin protrusion and gate protrusion are +0.15(.006)Max(each side). Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 48-pin plastic TSOP(1) (FPT-48P-M19) LEAD No. 1 48 INDEX Details of "A" part 0.25(.010) 0~8˚ 0.60±0.15 (.024±.006) 24 25 * 12.00±0.20 20.00±0.20 (.787±.008) * 18.40±0.20 (.724±.008) "A" (.472±.008) +0.10 1.10 –0.05 +.004 .043 –.002 (Mounting height) 0.10±0.05 (.004±.002) (Stand off height) 0.50(.020) 0.10(.004) +0.03 0.22±0.05 (.009±.002) 0.17 –0.08 +.001 .007 –.003 C 0.10(.004) 2003 FUJITSU LIMITED F48029S-c-6-7 M Dimensions in mm (inches) Note 1) * : Values do not include resin protrusion. Resin protrusion and gate protrusion are +0.15(.006)Max(each side). Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 48-pin plastic TSOP(1) (FPT-48P-M20) LEAD No. 1 48 Details of "A" part INDEX 0.60±0.15 (.024±.006) 0~8˚ 0.25(.010) 24 25 +0.03 0.17 –0.08 +.001 0.10(.004) .007 –.003 0.50(.020) 0.22±0.05 (.009±.002) M 0.10±0.05 (.004±.002) (Stand off height) +0.10 "A" 1.10 –0.05 +.004 * 18.40±0.20 (.724±.008) 20.00±0.20 (.787±.008) C 0.10(.004) 2003 FUJITSU LIMITED F48030S-c-6-7 .043 –.002 (Mounting height) * 12.00±0.20(.472±.008) Dimensions in mm (inches) (Continued) 65 MBM29DS163TE/BE10 (Continued) 48-pin plastic FBGA (BGA-48P-M11) +0.15 8.00±0.20(.315±.008) +.006 1.05 –0.10 .041 –.004 (Mounting height) 0.38±0.10(.015±.004) (Stand off) (5.60(.220)) 0.80(.031)TYP 6 5 INDEX 6.00±0.20 (.236±.008) 4 (4.00(.157)) 3 2 1 H C0.25(.010) G F E D 48-ø0.45±0.10 (48-ø.018±.004) C B A ø0.08(.003) M 0.10(.004) C 66 2001 FUJITSU LIMITED B48011S-c-5-3 Dimensions in mm (inches) MBM29DS163TE/BE10 FUJITSU LIMITED All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. 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Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. F0303 FUJITSU LIMITED Printed in Japan