SPANSION MBM29LV008TA-90

TM
SPANSION Flash Memory
Data Sheet
September 2003
TM
This document specifies SPANSION memory products that are now offered by both Advanced Micro Devices and
Fujitsu. Although the document is marked with the name of the company that originally developed the specification,
these products will be offered to customers of both AMD and Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a SPANSION
revisions will occur when appropriate, and changes will be noted in a revision summary.
TM
product. Future routine
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with "Am" and "MBM". To order these
products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about SPANSION
solutions.
TM
memory
FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-20858-6E
FLASH MEMORY
CMOS
8M (1M × 8) BIT
MBM29LV008TA-70/-90/MBM29LV008BA-70/-90
■ GENERAL DESCRIPTION
The MBM29LV008TA/BA are a 8M-bit, 3.0 V-only Flash memory organized as 1M bytes of 8 bits each. The
MBM29LV008TA/BA are offered in a 40-pin TSOP(1) package. These devices are designed to be programmed
in-system with the standard system 3.0 V VCC supply. 12.0 V VPP and 5.0 V VCC are not required for write or erase
operations. The devices can also be reprogrammed in standard EPROM programmers.
The standard MBM29LV008TA/BA offer access times 70 ns and 90 ns, allowing operation of high-speed
microprocessors without wait states. To eliminate bus contention the devices have separate chip enable (CE),
write enable (WE), and output enable (OE) controls.
(Continued)
■ PRODUCT LINE UP
Part No.
MBM29LV008TA/MBM29LV008BA
VCC = 3.3 V
+0.3 V
–0.3 V
-70
—
VCC = 3.0 V
+0.6 V
–0.3 V
—
-90
Max Address Access Time (ns)
70
90
Max CE Access Time (ns)
70
90
Max OE Access Time (ns)
30
35
Ordering Part No.
■ PACKAGES
40-pin plastic TSOP (1)
40-pin plastic TSOP (1)
Marking Side
Marking Side
(FPT-40P-M06)
(FPT-40P-M07)
MBM29LV008TA/BA-70/90
(Continued)
The MBM29LV008TA/BA are pin and command set compatible with JEDEC standard E2PROMs. Commands
are written to the command register using standard microprocessor write timings. Register contents serve as
input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally
latch addresses and data needed for the programming and erase operations. Reading data out of the devices
is similar to reading from 5.0 V and 12.0 V Flash or EPROM devices.
The MBM29LV008TA/BA are programmed by executing the program command sequence. This will invoke the
Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths
and verifies proper cell margin. Typically, each sector can be programmed and verified in about 0.5 seconds.
Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase
Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed
before executing the erase operation. During erase, the devices automatically time the erase pulse widths and
verify proper cell margin.
Any individual sector is typically erased and verified in 1.0 second. (If already completely preprogrammed.)
The devices also feature a sector erase architecture. The sector mode allows each sector to be erased and
reprogrammed without affecting other sectors. The MBM29LV008TA/BA are erased when shipped from the
factory.
The devices feature single 3.0 V power supply operation for both read and write functions. Internally generated
and regulated voltages are provided for the program and erase operations. A low VCC detector automatically
inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7,
by the Toggle Bit feature on DQ6, or the RY/BY output pin. Once the end of a program or erase cycle has been
completed, the devices internally reset to the read mode.
Fujitsu’s Flash technology combines years of EPROM and E2PROM experience to produce the highest levels
of quality, reliability, and cost effectiveness. The MBM29LV008TA/BA memories electrically erase the entire chip
or all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes are programmed one byte
at a time using the EPROM programming mechanism of hot electron injection.
2
MBM29LV008TA/BA-70/90
■ FEATURES
• Single 3.0 V read, program, and erase
Minimizes system level power requirements
• Compatible with JEDEC-standard commands
Uses same software commands as E2PROMs
• Compatible with JEDEC-standard world-wide pinouts
40-pin TSOP(1) (Package suffix: PTN – Normal Bend Type, PTR – Reversed Bend Type)
• Minimum 100,000 program/erase cycles
• High performance
70 ns maximum access time
• Sector erase architecture
One 16K byte, two 8K bytes, one 32K byte, and fifteen 64K bytes
Any combination of sectors can be concurrently erased. Also supports full chip erase
• Boot Code Sector Architecture
T = Top sector
B = Bottom sector
• Embedded EraseTM Algorithms
Automatically pre-programs and erases the chip or any sector
• Embedded ProgramTM Algorithms
Automatically writes and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready/Busy output (RY/BY)
Hardware method for detection of program or erase cycle completion
• Automatic sleep mode
When addresses remain stable, automatically switch themselves to low power mode
• Low VCC write inhibit ≤ 2.5 V
• Erase Suspend/Resume
Suspends the erase operation to allow a read data in another sector within the same device
• Sector protection
Hardware method disables any combination of sectors from program or erase operations
• Sector Protection Set function by Extended sector protection command
• Temporary sector unprotection
Temporary sector unprotection via the RESET pin
Note : Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.
3
MBM29LV008TA/BA-70/90
■ PIN ASSIGNMENTS
TSOP (1)
A16
A15
A14
A13
A12
A11
A9
A8
WE
RESET
N.C.
RY/BY
A18
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
(Marking Side)
MBM29LV008TA/MBM29LV008BA
Normal Bend
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A17
VSS
N.C.
A19
A10
DQ7
DQ6
DQ5
DQ4
VCC
VCC
N.C.
DQ3
DQ2
DQ1
DQ0
OE
VSS
CE
A0
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
A0
CE
VSS
OE
DQ0
DQ1
DQ2
DQ3
N.C.
VCC
VCC
DQ4
DQ5
DQ6
DQ7
A10
A19
N.C.
VSS
A17
(FPT-40P-M06)
A1
A2
A3
A4
A5
A6
A7
A18
RY/BY
N.C.
RESET
WE
A8
A9
A11
A12
A13
A14
A15
A16
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
(Marking Side)
MBM29LV008TA/MBM29LV008BA
Reverse Bend
(FPT-40P-M07)
4
MBM29LV008TA/BA-70/90
■ PIN DESCRIPTION
Pin
A19 to A0
DQ7 to DQ0
Function
Address Inputs
Data Inputs/Outputs
CE
Chip Enable
OE
Output Enable
WE
Write Enable
RY/BY
Ready/Busy Output
RESET
Hardware Reset Pin/Temporary Sector Unprotection
N.C.
No Internal Connection
VSS
Device Ground
VCC
Device Power Supply
5
MBM29LV008TA/BA-70/90
■ BLOCK DIAGRAM
DQ7 to DQ0
RY/BY
Buffer
RY/BY
VCC
VSS
Erase Voltage
Generator
Input/Output
Buffers
WE
State
Control
RESET
Command
Register
Program Voltage
Generator
Chip Enable
Output Enable
Logic
CE
STB
Data Latch
OE
STB
Low VCC Detector
Timer for
Program/Erase
Address
Latch
A19 to A0
■ LOGIC SYMBOL
20
A19 to A0
8
DQ7 to DQ0
CE
OE
WE
RESET
6
RY/BY
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
MBM29LV008TA/BA-70/90
■ DEVICE BUS OPERATION
MBM29LV008TA/008BA User Bus Operations
CE
OE
WE
A0
A1
A6
A9
A10
Auto-Select Manufacturer Code*1
L
L
H
L
L
L
VID
L
Code
H
Auto-Select Device Code*1
L
L
H
H
L
L
VID
L
Code
H
Read*3
L
L
H
A0
A1
A6
A9
A10
DOUT
H
Standby
H
X
X
X
X
X
X
X
High-Z
H
Output Disable
L
H
H
X
X
X
X
X
High-Z
H
Write (Program/Erase)
L
H
L
A0
A1
A6
A9
A10
DIN
H
Enable Sector Protection*2, *4
L
VID
L
H
L
VID
X
X
H
Verify Sector Protection*2, *4
L
L
H
L
H
L
VID
L
Code
H
Temporary Sector Unprotection*5
X
X
X
X
X
X
X
X
X
VID
Reset (Hardware)/Standby
X
X
X
X
X
X
X
X
High-Z
L
Operation
Legend: L = VIL, H = VIH, X = VIL or VIH,
DQ7 to DQ0 RESET
= Pulse input. See “■ DC CHARACTERISTICS” for voltage levels.
*1 : Manufacturer and device codes may also be accessed via a command register write sequence.
See “MBM29LV008TA/008BA Standard Command Definitions”.
*2 : Refer to “Sector Protection” in ■ FUNCTIONAL DESCRIPTION.
*3 : WE can be VIL if OE is VIL, OE at VIH initiates the write operations.
*4 : VCC = 3.3 V ± 10%
*5 : It is also used for the extended sector protection.
7
MBM29LV008TA/BA-70/90
MBM29LV008TA/008BA Standard Command Definitions
Command
Sequence
Bus
First Bus Second Bus Third Bus Fourth
Fifth Bus
Sixth Bus
Bus
Read/Write Write
Cycle Write Cycle
Write Write Cycle Write Cycle Write Cycle
Cycle
Cycles
Req’d
Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data
Read/Reset
1
XXXh
F0h
—
—
—
—
—
—
—
—
—
—
Read/Reset
3
555h
AAh
2AAh
55h
555h
F0h
RA*
RD*
—
—
—
—
Autoselect
3
555h
AAh
2AAh
55h
555h
90h
IA*
ID*
—
—
—
—
Program
4
555h
AAh
2AAh
55h
555h
A0h
PA
PD
—
—
—
—
Chip Erase
6
555h
AAh
2AAh
55h
555h
80h
555h
AAh
2AAh
55h
555h
10h
Sector Erase
6
555h
AAh
2AAh
55h
555h
80h
555h
AAh
2AAh
55h
SA
30h
Sector Erase Suspend
Erase can be suspended during sector erase with Addr. (“H” or “L”). Data (B0h)
Sector Erase Resume
Erase can be resumed after suspend with Addr. (“H” or “L”). Data (30h)
* : The fourth bus cycle is only for read.
Notes: • Address bits A19 to A11 = X = “H” or “L” for all address commands except or Program Address (PA) and
Sector Address (SA)
• Bus operations are defined in “MBM29LV008TA/008BA User Bus Operations”.
• RA = Address of the memory location to be read
IA = Autoselect read address that sets A10, A6, A1, A0.
PA = Address of the memory location to be programmed
Addresses are latched on the falling edge of the write pulse.
SA = Address of the sector to be erased. The combination of A19, A18, A17, A16, A15, A14, and A13 will
uniquely select any sector.
• RD = Data read from location RA during read operation.
ID = Device code / manufacture code for the address located by IA.
PD = Data to be programmed at location PA. Data is latched on the rising edge of write pulse.
• Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.
• Command combinations not described in Standard Command Definitions table are illegal.
8
MBM29LV008TA/BA-70/90
MBM29LV008TA/BA Extended Command Definitions
Bus Write
Cycles
Req'd
Command
Sequence
First Bus
Write Cycle
Second Bus
Write Cycle
Third Bus
Write Cycle
Fourth Bus
Read Cycle
Addr.
Data
Addr.
Data
Addr.
Data
Addr.
Data
Set to
Fast Mode
3
555h
AAh
2AAh
55h
555h
20h
—
—
Fast Program*1
2
XXXh
A0h
PA
PD
—
—
—
—
Reset from Fast
Mode *1
2
XXXh
90h
XXXh
F0h*3
—
—
—
—
Extended Sector
Protect *2
4
XXXh
60h
SPA
60h
SPA
40h
SPA
SD
SPA: Sector address to be protected. Set sector address (SA) and (A10, A6, A1, A0) = (0, 0, 1, 0).
SD: Sector protection verify data. Output “01h” at protected sector addresses and output “00h” at unprotected
sector addresses.
*1: This command is valid while Fast Mode.
*2: This command is valid while RESET= VID.
*3: The data "00h" is also acceptable.
MBM29LV008TA/008BA Sector Protection Verify Autoselect Codes
A19 to A13
A10
A6
A1
A0
Code (HEX)
X
VIL
VIL
VIL
VIL
04h
MBM29LV008TA
X
VIL
VIL
VIL
VIH
3Eh
MBM29LV008BA
X
VIL
VIL
VIL
VIH
37h
Sector
Addresses
VIL
VIL
VIH
VIL
01h*
Type
Manufacture’s Code
Device Code
Sector Protection
* : Outputs “01h” at protected sector addresses and outputs “00h” at unprotected sector addresses.
Extended Autoselect Code Table
Code
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
04h
0
0
0
0
0
1
0
0
MBM29LV008TA
3Eh
0
0
1
1
1
1
1
0
MBM29LV008BA
37h
0
0
1
1
0
1
1
1
01h
0
0
0
0
0
0
0
1
Type
Manufacture’s Code
Device Code
Sector Protection
9
MBM29LV008TA/BA-70/90
■ FLEXIBLE SECTOR-ERASE ARCHITECTURE
• One 16K byte, two 8K bytes, one 32K byte, and fifteen 64K bytes
• Individual-sector, multiple-sector, or bulk-erase capability
• Individual or multiple-sector protection is user definable.
FFFFFh
16K byte
FFFFFh
64K byte
FC000h
8K byte
F0000h
64K byte
FA000h
8K byte
E0000h
64K byte
F8000h
32K byte
D0000h
64K byte
F0000h
64K byte
C0000h
64K byte
E0000h
64K byte
B0000h
64K byte
D0000h
64K byte
A0000h
64K byte
C0000h
64K byte
90000h
64K byte
B0000h
64K byte
80000h
64K byte
A0000h
64K byte
70000h
64K byte
90000h
64K byte
60000h
64K byte
80000h
64K byte
50000h
64K byte
70000h
64K byte
40000h
64K byte
60000h
64K byte
30000h
64K byte
50000h
64K byte
20000h
64K byte
40000h
64K byte
10000h
32K byte
30000h
64K byte
08000h
8K byte
20000h
64K byte
06000h
8K byte
10000h
64K byte
00000h
MBM29LV008TA Sector Architecture
10
04000h
16K byte
00000h
MBM29LV008BA Sector Architecture
MBM29LV008TA/BA-70/90
Sector Address Tables (MBM29LV008TA)
Sector
Address
A19
A18
A17
A16
A15
A14
A13
Address Range
SA0
0
0
0
0
X
X
X
00000h to 0FFFFh
SA1
0
0
0
1
X
X
X
10000h to 1FFFFh
SA2
0
0
1
0
X
X
X
20000h to 2FFFFh
SA3
0
0
1
1
X
X
X
30000h to 3FFFFh
SA4
0
1
0
0
X
X
X
40000h to 4FFFFh
SA5
0
1
0
1
X
X
X
50000h to 5FFFFh
SA6
0
1
1
0
X
X
X
60000h to 6FFFFh
SA7
0
1
1
1
X
X
X
70000h to 7FFFFh
SA8
1
0
0
0
X
X
X
80000h to 8FFFFh
SA9
1
0
0
1
X
X
X
90000h to 9FFFFh
SA10
1
0
1
0
X
X
X
A0000h to AFFFFh
SA11
1
0
1
1
X
X
X
B0000h to BFFFFh
SA12
1
1
0
0
X
X
X
C0000h to CFFFFh
SA13
1
1
0
1
X
X
X
D0000h to DFFFFh
SA14
1
1
1
0
X
X
X
E0000h to EFFFFh
SA15
1
1
1
1
0
X
X
F0000h to F7FFFh
SA16
1
1
1
1
1
0
0
F8000h to F9FFFh
SA17
1
1
1
1
1
0
1
FA000h to FBFFFh
SA18
1
1
1
1
1
1
X
FC000h to FFFFFh
11
MBM29LV008TA/BA-70/90
Sector Address Tables (MBM29LV008BA)
12
Sector
Address
A19
A18
A17
A16
A15
A14
A13
Address Range
SA0
0
0
0
0
0
0
X
00000h to 03FFFh
SA1
0
0
0
0
0
1
0
04000h to 05FFFh
SA2
0
0
0
0
0
1
1
06000h to 07FFFh
SA3
0
0
0
0
1
X
X
08000h to 0FFFFh
SA4
0
0
0
1
X
X
X
10000h to 1FFFFh
SA5
0
0
1
0
X
X
X
20000h to 2FFFFh
SA6
0
0
1
1
X
X
X
30000h to 3FFFFh
SA7
0
1
0
0
X
X
X
40000h to 4FFFFh
SA8
0
1
0
1
X
X
X
50000h to 5FFFFh
SA9
0
1
1
0
X
X
X
60000h to 6FFFFh
SA10
0
1
1
1
X
X
X
70000h to 7FFFFh
SA11
1
0
0
0
X
X
X
80000h to 8FFFFh
SA12
1
0
0
1
X
X
X
90000h to 9FFFFh
SA13
1
0
1
0
X
X
X
A0000h to AFFFFh
SA14
1
0
1
1
X
X
X
B0000h to BFFFFh
SA15
1
1
0
0
X
X
X
C0000h to CFFFFh
SA16
1
1
0
1
X
X
X
D0000h to DFFFFh
SA17
1
1
1
0
X
X
X
E0000h to EFFFFh
SA18
1
1
1
1
X
X
X
F0000h to FFFFFh
MBM29LV008TA/BA-70/90
■ FUNCTIONAL DESCRIPTION
Read Mode
The MBM29LV008TA/BA have two control functions which must be satisfied in order to obtain data at the outputs.
CE is the power control and should be used for a device selection. OE is the output control and should be used
to gate data to the output pins if a device is selected.
Address access time (tACC) is equal to the delay from stable addresses to valid output data. The chip enable
access time (tCE) is the delay from stable addresses and stable CE to valid data at the output pins. The output
enable access time is the delay from the falling edge of OE to valid data at the output pins. (Assuming the
addresses have been stable for at least tACC-tOE time.) When reading out a data without changing addresses after
power-up, it is necessary to input hardware reset or change CE pin from “H” or “L”.
Standby Mode
There are two ways to implement the standby mode on the MBM29LV008TA/BA devices, one using both the CE
and RESET pins; the other via the RESET pin only.
When using both pins, a CMOS standby mode is achieved with CE and RESET inputs both held at VCC ± 0.3 V.
Under this condition the current consumed is less than 5 µA. The device can be read with standard access time
(tCE) from either of these standby modes. During Embedded Algorithm operation, VCC active current (ICC2) is
required even CE = “H”.
When using the RESET pin only, a CMOS standby mode is achieved with RESET input held at VSS ± 0.3 V (CE
= “H” or “L”). Under this condition the current is consumed is less than 5 µA. Once the RESET pin is taken high,
the device requires tRH of wake up time before outputs are valid for read access.
In the standby mode the outputs are in the high impedance state, independent of the OE input.
Automatic Sleep Mode
There is a function called automatic sleep mode to restrain power consumption during read-out of
MBM29LV008TA/BA data. This mode can be used effectively with an application requested low power
consumption such as handy terminals.
To activate this mode, MBM29LV008TA/BA automatically switch themselves to low power mode when
MBM29LV008TA/BA addresses remain stably during access fine of 150 ns. It is not necessary to control CE,
WE, and OE on the mode. Under the mode, the current consumed is typically 1 µA (CMOS Level).
Since the data are latched during this mode, the data are read-out continuously. If the addresses are changed,
the mode is canceled automatically and MBM29LV008TA/BA read-out the data for changed addresses.
Output Disable
With the OE input at a logic high level (VIH), output from the devices are disabled. This will cause the output pins
to be in a high impedance state.
Autoselect
The autoselect mode allows the reading out of a binary code from the devices and will identify its manufacturer
and type. This mode is intended for use by programming equipment for the purpose of automatically matching
the devices to be programmed with its corresponding programming algorithm. This mode is functional over the
entire temperature range of the devices.
To activate this mode, the programming equipment must force VID (11.5 V to 12.5 V) on address pin A9. Two
identifier bytes may then be sequenced from the devices outputs by toggling address A0 from VIL to VIH. All
addresses are DON’T CARES except A0, A1, A6, and A10. (See “MBM29LV008TA/008BA Sector Protection Verify
Autoselect Codes” in ■ DEVICE BUS OPERATION.)
13
MBM29LV008TA/BA-70/90
The manufacturer and device codes may also be read via the command register, for instances when the
MBM29LV008TA/BA are erased or programmed in a system without access to high voltage on the A9 pin. The
command sequence is illustrated in “MBM29LV008TA/008BA Standard Command Definitions” in ■ DEVICE
BUS OPERATION. (Refer to “Autoselect Command”.)
Byte 0 (A0 = VIL) represents the manufacturer’s code (Fujitsu = 04h) and (A0 = VIH) represents the device identifier
code (MBM29LV008TA = 3Eh and MBM29LV008BA = 37h). These two bytes/words are given in
“MBM29LV008TA/008BA Sector Protection Verify Autoselect Codes” and “Expanded Autoselect Code Table” in
■ DEVICE BUS OPERATION. All identifiers for manufactures and device will exhibit odd parity with DQ7 defined
as the parity bit. In order to read the proper device codes when executing the autoselect, A1 must be VIL. (See
“MBM29LV008TA/008BA Sector Protection Verify Autoselect Codes” and “Expanded Autoselect Code Table” in
■ DEVICE BUS OPERATION.)
Write
Device erasure and programming are accomplished via the command register. The contents of the register serve
as inputs to the internal state machine. The state machine outputs dictate the function of the device.
The command register itself does not occupy any addressable memory location. The register is a latch used to
store the commands, along with the address and data information needed to execute the command. The
command register is written by bringing WE to VIL, while CE is at VIL and OE is at VIH. Addresses are latched on
the falling edge of WE or CE, whichever happens later; while data is latched on the rising edge of WE or CE,
whichever happens first. Standard microprocessor write timings are used.
Refer to “AC Waveforms for Alternate WE Controlled Program Operations” and “AC Waveforms for Alternate CE
Controlled Program Operations” in ■ TIMING DIAGRAM.
Sector Protection
The MBM29LV008TA/BA feature hardware sector protection. This feature will disable both program and erase
operations in any number of sectors (0 through 18). The sector protection feature is enabled using programming
equipment at the user’s site. The devices are shipped with all sectors unprotected. Alternatively, Fujitsu may
program and protect sectors in the factory prior to shiping the device.
To activate this mode, the programming equipment must force VID on address pin A9 and control pin OE, (suggest
VID = 11.5 V), CE = VIL, and A6 = VIL. The sector addresses (A19, A18, A17, A16, A15, A14, and A13) should be set to
the sector to be protected. “Sector Address Tables (MBM29LV008TA) ” and “Sector Address Tables
(MBM29LV008BA) ” in ■ FLEXIBLE SECTOR-ERASE ARCHITECTURE define the sector address for each of
the nineteen (19) individual sectors. Programming of the protection circuitry begins on the falling edge of the
WE pulse and is terminated with the rising edge of the same. Sector addresses must be held constant during
the WE pulse. See “ (10) AC Waveforms for Sector Protection Timing Diagram” in ■ TIMING DIAGRAM and “
(5) Sector Protection Algorithm” in ■ FLOW CHART for sector protection waveforms and algorithm.
To verify programming of the protection circuitry, the programming equipment must force VID on address pin A9
with CE and OE at VIL and WE at VIH. Scanning the sector addresses (A19, A18, A17, A16, A15, A14, and A13) while
(A10, A6, A1, A0) = (0, 0, 1, 0) will produce a logical “1” code at device output DQ0 for a protected sector. Otherwise
the devices will read 00h for unprotected sector. In this mode, the lower order addresses, except for A0, A1, A6,
and A10 are DON’T CARES. Address locations with A1 = VIL are reserved for Autoselect manufacturer and device
codes.
It is also possible to determine if a sector is protected in the system by writing an Autoselect command. Performing
a read operation at the address location XX02h, where the higher order addresses (A19, A18, A17, A16, A15, A14,
and A13) are the desired sector address will produce a logical “1” at DQ0 for a protected sector. See
“MBM29LV008TA/008BA Sector Protection Verify Autoselect Codes” and “Expanded Autoselect Code Table”
in ■ DEVICE BUS OPERATION for Autoselect codes.
14
MBM29LV008TA/BA-70/90
Temporary Sector Unprotection
This feature allows temporary unprotection of previously protected sectors of the MBM29LV008TA/BA devices
in order to change data. The Sector Unprotection mode is activated by setting the RESET pin to high voltage
(12 V). During this mode, formerly protected sectors can be programmed or erased by selecting the sector
addresses. Once the 12 V is taken away from the RESET pin, all the previously protected sectors will be protected
again. See “ (11) Temporary Sector Unprotection Timing Diagram” in ■ TIMING DIAGRAM and “ (6) Temporary
Sector Unprotection Algorithm” in ■ FLOW CHART.
Command Definitions
Device operations are selected by writing specific address and data sequences into the command register.
Writing incorrect address and data values or writing them in the improper sequence will reset the devices to the
read mode. “MBM29LV008TA/008BA Standard Command Definitions” in ■ DEVICE BUS OPERATION defines
the valid register command sequences. Note that the Erase Suspend (B0h) and Erase Resume (30h) commands
are valid only while the Sector Erase operation is in progress. Moreover both Read/Reset commands are
functionally equivalent, resetting the device to the read mode.
Read/Reset Command
In order to return from Autoselect mode or Exceeded Timing Limits (DQ5 = 1) to read/reset mode, the read/reset
operation is initiated by writing the Read/Reset command sequence into the command register. Microprocessor
read cycles retrieve array data from the memory. The devices remain enabled for reads until the command
register contents are altered.
The devices will automatically power-up in the read/reset state. In this case, a command sequence is not required
to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no
spurious alteration of the memory content occurs during the power transition. Refer to the AC Read
Characteristics and Waveforms for the specific timing parameters.
Autoselect Command
Flash memories are intended for use in applications where the local CPU alters memory contents. As such,
manufacture and device codes must be accessible while the devices reside in the target system. PROM
programmers typically access the signature codes by raising A9 to a high voltage. However, multiplexing high
voltage onto the address lines is not generally desired system design practice.
The device contains an Autoselect command operation to supplement traditional PROM programming
methodology. The operation is initiated by writing the Autoselect command sequence into the command register.
Following the command write, a read cycle from address XX00h retrieves the manufacture code of 04h. A read
cycle from address XX01h returns the device code (MBM29LV008TA = 3Eh and MBM29LV008BA = 37h). (See
“MBM29LV008TA/008BA Sector Protection Verify Autoselect Codes” and “Expanded Autoselect Code Table”
in ■ DEVICE BUS OPERATION.) All manufacturer and device codes will exhibit odd parity with DQ7 defined as
the parity bit. Sector state (protection or unprotection) will be informed by address XX02h.
Scanning the sector addresses (A19, A18, A17, A16, A15, A14, and A13) while (A10, A6, A1, A0) = (0, 0, 1, 0) will produce
a logical “1” at device output DQ0 for a protected sector. The programming verification should be perform margin
mode on the protected sector. (See “MBM29LV008TA/008BA Sector Protection Verify Autoselect Codes” and
“Expanded Autoselect Code Table” in ■ DEVICE BUS OPERATION.)
To terminate the operation, it is necessary to write the Read/Reset command sequence into the register, and
also to write the Autoselect command during the operation, execute it after writing Read/Reset command
sequence.
15
MBM29LV008TA/BA-70/90
Byte Programming
The devices are programmed on a byte-by-byte basis. Programming is a four bus cycle operation. There are
two “unlock” write cycles. These are followed by the program set-up command and data write cycles. Addresses
are latched on the falling edge of CE or WE, whichever happens later and the data is latched on the rising edge
of CE or WE, whichever happens first. The rising edge of CE or WE (whichever happens first) begins
programming. Upon executing the Embedded Program Algorithm command sequence, the system is not required
to provide further controls or timings. The device will automatically provide adequate internally generated
program pulses and verify the programmed cell margin.
The automatic programming operation is completed when the data on DQ7 is equivalent to data written to this
bit at which time the devices return to the read mode and addresses are no longer latched. (See “Hardware
Sequence Flags”.) Therefore, the devices require that a valid address to the devices be supplied by the system
at this particular instance of time. Hence, Data Polling must be performed at the memory location which is being
programmed.
Any commands written to the chip during this period will be ignored. If hardware reset occurs during the
programming operation, it is impossible to guarantee the data are being written.
Programming is allowed in any sequence and across sector boundaries. Beware that a data “0” cannot be
programmed back to a “1”. Attempting to do so may either hang up the device or result in an apparent success
according to the data polling algorithm but a read from read/reset mode will show that the data is still “0”. Only
erase operations can convert “0”s to “1”s.
“ (1) Embedded ProgramTM Algorithm” in ■ FLOW CHART illustrates the Embedded ProgramTM Algorithm using
typical command strings and bus operations.
Chip Erase
Chip erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then followed by the chip erase command.
Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase
Algorithm command sequence the devices will automatically program and verify the entire memory for an all
zero data pattern prior to electrical erase (Preprogram function). The system is not required to provide any
controls or timings during these operations.
The automatic erase begins on the rising edge of the last write pulse in the command sequence and terminates
when the data on DQ7 is “1” (See “Write Operation Status”.) at which time the device returns to read the mode.
Chip Erase Time : Sector Erase Time × All sectors + Chip Program Time (Preprogramming)
“ (2) Embedded EraseTM Algorithm” in ■ FLOW CHART illustrates the Embedded EraseTM Algorithm using typical
command strings and bus operations.
Sector Erase
Sector erase is a six bus cycle operation. There are two “unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then followed by the Sector Erase command. The sector
address (any address location within the desired sector) is latched on the falling edge of write pulse, while the
command (Data=30h) is latched on the rising edge of write pulse. After time-out of 50 µs from the rising edge
of the last sector erase command, the sector erase operation will begin.
Multiple sectors may be erased concurrently by writing the six bus cycle operations on “MBM29LV008TA/008BA
Standard Command Definitions” in ■ DEVICE BUS OPERATION. This sequence is followed with writes of the
Sector Erase command to addresses in other sectors desired to be concurrently erased. The time between
writes must be less than 50 µs otherwise that command will not be accepted and erasure will start. It is
recommended that processor interrupts be disabled during this time to guarantee this condition. The interrupts
can be re-enabled after the last Sector Erase command is written. A time-out of 50 µs from the rising edge of
the last write pulse will initiate the execution of the Sector Erase command(s). If another falling edge of the write
16
MBM29LV008TA/BA-70/90
pulse occurs within the 50 µs time-out window the timer is reset. (Monitor DQ3 to determine if the sector erase
timer window is still open, see “DQ3 Sector Erase Timer”.) Any command other than Sector Erase or Erase
Suspend during this time-out period will reset the devices to the read mode, ignoring the previous command
string. Resetting the devices once execution has begun will corrupt the data in the sector. In that case, restart
the erase on those sectors and allow them to complete. (Refer to “Write Operation Status” for Sector Erase
Timer operation.) Loading the sector erase buffer may be done in any sequence and with any number of sectors
(18 to 0).
Sector erase does not require the user to program the devices prior to erase. The devices automatically program
all memory locations in the sector(s) to be erased prior to electrical erase (Preprogram function). When erasing
a sector or sectors the remaining unselected sectors are not affected. The system is not required to provide any
controls or timings during these operations.
The automatic sector erase begins after the 50 µs time out from the rising edge of the write pulse for the last
sector erase command pulse and terminates when the data on DQ7 is “1” (see “Write Operation Status”) at which
time the devices return to the read mode. Data polling must be performed at an address within any of the sectors
being erased. Multiple Sector Erase Time : [Sector Erase Time + Sector Program Time (Preprogramming)] ×
Number of Sector Erase
“ (2) Embedded EraseTM Algorithm” in ■ FLOW CHART illustrates the Embedded EraseTM Algorithm using typical
command strings and bus operations.
Erase Suspend
The Erase Suspend command allows the user to interrupt a Sector Erase operation and then perform data reads
from or programs to a sector not being erased. This command is applicable ONLY during the Sector Erase
operation which includes the time-out period for sector erase. The Erase Suspend command will be ignored if
written during the Chip Erase operation or Embedded Program Algorithm. Writting the Erase Suspend command
during the Sector Erase time-out results in immediate termination of the time-out period and suspension of the
erase operation.
Writing the Erase Resume command resumes the erase operation. The addresses are DON’T CARES when
writing the Erase Suspend or Erase Resume command.
When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum
of 20 µs to suspend the erase operation. When the devices have entered the erase-suspended mode, the RY/
BY output pin and the DQ7 bit will be at logic “1”, and DQ6 will stop toggling. The user must use the address of
the erasing sector for reading DQ6 and DQ7 to determine if the erase operation has been suspended. Further
writes of the Erase Suspend command are ignored.
When the erase operation has been suspended, the devices default to the erase-suspend-read mode. Reading
data in this mode is the same as reading from the standard read mode except that the data must be read from
sectors that have not been erase-suspended. Successively reading from the erase-suspended sector while the
device is in the erase-suspend-read mode will cause DQ2 to toggle. (See”DQ2 Toggle Bit II”.)
After entering the erase-suspend-read mode, the user can program the device by writing the appropriate
command sequence for Program. This program mode is known as the erase-suspend-program mode. Again,
programming in this mode is the same as programming in the regular Program mode except that the data must
be programmed to sectors that are not erase-suspended. Successively reading from the erase-suspended sector
while the devices are in the erase-suspend-program mode will cause DQ2 to toggle. The end of the erasesuspended Program operation is detected by the RY/BY output pin, Data polling of DQ7, or by the Toggle Bit I
(DQ6) which is the same as the regular Program operation. Note that DQ7 must be read from the Program address
while DQ6 can be read from any address.
To resume the operation of Sector Erase, the Resume command (30h) should be written. Any further writes of
the Resume command at this point will be ignored. Another Erase Suspend command can be written after the
chip has resumed erasing.
17
MBM29LV008TA/BA-70/90
Extended Command
(1) Fast Mode
MBM29LV008TA/BA has Fast Mode function. This mode dispenses with the initial two unclock cycles required
in the standard program command sequence by writing Fast Mode command into the command register. In
this mode, the required bus cycle for programming is two cycles instead of four bus cycles in standard
program command. (Do not write erase command in this mode.) The read operation is also executed after
exiting this mode. To exit this mode, it is necessary to write Fast Mode Reset command into the command
register. (Refer to “ (8) Embedded ProgramTM Algorithm for Fast Mode” in ■ FLOW CHART.) The VCC active
current is required even CE = VIH during Fast Mode.
(2) Fast Programming
During Fast Mode, the programming can be executed with two bus cycles operation. The Embedded Program
Algorithm is executed by writing program set-up command (A0h) and data write cycles (PA/PD). (Refer to
to “ (8) Embedded ProgramTM Algorithm for Fast Mode” in ■ FLOW CHART.)
(3) Extended Sector Protection
In addition to normal sector protection, the MBM29LV008TA/BA has Extended Sector Protection as extended
function. This function enable to protect sector by forcing VID on RESET pin and write a commnad sequence.
Unlike conventional procedure, it is not necessary to force VID and control timing for control pins. The only
RESET pin requires VID for sector protection in this mode. The extended sector protect requires VID on RESET
pin. With this condition, the operation is initiated by writing the set-up command (60h) into the command
register. Then, the sector addresses pins (A19, A18, A17, A16, A15, A14, and A13) and (A10, A6, A1, A0) = (0, 0, 1,
0) should be set to the sector to be protected (recommend to set VIL for the other addresses pins), and write
extended sector protect command (60h). A sector is typically protected in 150 µs. To verify programming of
the protection circuitry, the sector addresses pins (A19, A18, A17, A16, A15, A14, and A13) and (A10, A6, A1, A0) =
(0, 0, 1, 0) should be set and write a command (40h). Following the command write, a logical “1” at device
output DQ0 will produce for protected sector in the read operation. If the output data is logical “0”, please
repeat to write extended sector protect command (60h) again. To terminate the operation, it is necessary to
set RESET pin to VIH.
Write Operation Status
Hardware Sequence Flags
Status
Embedded Program Algorithm
Embedded Erase Algorithm
In Progress
Erase Suspend Read
(Erase Suspended Sector)
Erase
Erase Suspend Read
Suspended
(Non-Erase Suspended Sector)
Mode
Erase Suspend Program
(Non-Erase Suspended Sector)
DQ7
DQ6
DQ5
DQ3
DQ2
DQ7
Toggle
0
0
1
0
Toggle
0
1
Toggle
1
1
0
0
Toggle
Data
Data
Data Data
Data
DQ7 Toggle* 1
0
0
1*2
Embedded Program Algorithm
DQ7
Toggle
1
0
1
Embedded Erase Algorithm
Exceeded
Time Limits Erase
Erase Suspend Program
Suspended
(Non-Erase Suspended Sector)
Mode
0
Toggle
1
1
N/A
DQ7
Toggle
1
0
N/A
*1 : Performing successive read operations from any address will cause DQ6 to toggle.
*2 : Reading the byte address being programmed while in the erase-suspend program mode will indicate logic “1”
at the DQ2 bit. However, successive reads from the erase-suspended sector will cause DQ2 to toggle.
Notes : • DQ0 and DQ1 are reserve pins for future use.
• DQ4 is Fujitsu internal use only.
18
MBM29LV008TA/BA-70/90
DQ7
Data Polling
The MBM29LV008TA/BA devices feature Data Polling as a method to indicate to the host that the Embedded
Algorithms are in progress or completed. During the Embedded Program Algorithm an attempt to read the
devices will produce the complement of the data last written to DQ7. Upon completion of the Embedded Program
Algorithm, an attempt to read the device will produce the true data last written to DQ7. During the Embedded
Erase Algorithm, an attempt to read the device will produce a “0” at the DQ7 output. Upon completion of the
Embedded Erase Algorithm an attempt to read the device will produce a “1” at the DQ7 output. The flowchart
for Data Polling (DQ7) is shown in “ (3) Data Polling Algorithm” in ■ FLOW CHART.
For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth write pulse in the six
write pulse sequence. Data Polling must be performed at sector address within any of the sectors being erased
and not a protected sector. Otherwise, the status may not be valid. Once the Embedded Algorithm operation is
close to being completed, the MBM29LV008TA/BA data pins (DQ7) may change asynchronously while the output
enable (OE) is asserted low. This means that the devices are driving status information on DQ7 at one instant
of time and then that byte’s valid data at the next instant of time. Depending on when the system samples the
DQ7 output, it may read the status or valid data. Even if the device has completed the Embedded Algorithm
operation and DQ7 has a valid data, the data outputs on DQ6 to DQ0 may be still invalid. The valid data on DQ7
to DQ0 will be read on the successive read attempts.
The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase Algorithm
or sector erase time-out. (See “Hardware Sequence Flags”.)
See “ (6) AC Waveforms for Data Polling during Embedded Algorithm Operations” in ■ TIMING DIAGRAM for
the Data Polling timing specifications and diagrams.
DQ6
Toggle Bit I
The MBM29LV008TA/BA also feature the “Toggle Bit I” as a method to indicate to the host system that the
Embedded Algorithms are in progress or completed.
During an Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from
the devices will result in DQ6 toggling between one and zero. Once the Embedded Program or Erase Algorithm
cycle is completed, DQ6 will stop toggling and valid data will be read on the next successive attempts. During
programming, the Toggle Bit I is valid after the rising edge of the fourth write pulse in the four write pulse sequence.
For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth write pulse in the six
write pulse sequence. The Toggle Bit I is active during the sector time out.
In programming, if the sector being written to is protected, the toggle bit will toggle for about 2 µs and then stop
toggling without the data having changed. In erase, the devices will erase all the selected sectors except for the
ones that are protected. If all selected sectors are protected, the chip will toggle the toggle bit for about 100 µs
and then drop back into read mode, having changed none of the data.
Either CE or OE toggling will cause the DQ6 to toggle. In addition, an Erase Suspend/Resume command will
cause the DQ6 to toggle.
See “ (7) AC Waveforms for Toggle Bit I during Embedded Algorithm Operations” in ■ TIMING DIAGRAM for
the Toggle Bit I timing specifications and diagrams.
19
MBM29LV008TA/BA-70/90
DQ5
Exceeded Timing Limits
DQ5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under
these conditions DQ5 will produce a “1”. This is a failure condition which indicates that the program or erase
cycle was not successfully completed. Data Polling DQ7, DQ6 is the only operating function of the devices under
this condition. The CE circuit will partially power down the device under these conditions (to approximately
2 mA). The OE and WE pins will control the output disable functions as described in “MBM29LV008TA/008BA
User Bus Operations” in ■ DEVICE BUS OPERATION.
The DQ5 failure condition may also appear if a user tries to program a non blank location without erasing. In this
case the devices lock out and never complete the Embedded Algorithm operation. Hence, the system never
reads a valid data on DQ7 bit and DQ6 never stops toggling. Once the devices have exceeded timing limits, the
DQ5 bit will indicate a “1.” Please note that this is not a device failure condition since the devices were incorrectly
used. If this occurs, reset the device with command sequence.
DQ3
Sector Erase Timer
After the completion of the initial sector erase command sequence the sector erase time-out will begin. DQ3 will
remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector erase
command sequence.
If Data Polling or the Toggle Bit I indicates the device has been written with a valid erase command, DQ3 may
be used to determine if the sector erase timer window is still open. If DQ3 is high (“1”) the internally controlled
erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase
operation is completed as indicated by Data Polling or Toggle Bit I. If DQ3 is low (“0”), the device will accept
additional sector erase commands. To insure the command has been accepted, the system software should
check the status of DQ3 prior to and following each subsequent Sector Erase command. If DQ3 were high on
the second status check, the command may not have been accepted.
Refer to “Hardware Sequence Flags”.
DQ2
Toggle Bit II
This Toggle bit II, along with DQ6, can be used to determine whether the devices are in the Embedded Erase
Algorithm or in Erase Suspend.
Successive reads from the erasing sector will cause DQ2 to toggle during the Embedded Erase Algorithm. If the
devices are in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause
DQ2 to toggle. When the devices are in the erase-suspended-program mode, successive reads from the byte
address of the non-erase suspended sector will indicate a logic “1” at the DQ2 bit.
DQ6 is different from DQ2 in that DQ6 toggles only when the standard program or Erase, or Erase Suspend
Program operation is in progress. The behavior of these two status bits, along with that of DQ7, is summarized
as follows:
For example, DQ2 and DQ6 can be used together to determine if the erase-suspend-read mode is in progress.
(DQ2 toggles while DQ6 does not.) See also “Hardware Sequence Flags” and “ (12) DQ2 vs.DQ6” in ■ TIMING
DIAGRAM.
20
MBM29LV008TA/BA-70/90
Furthermore, DQ2 can also be used to determine which sector is being erased. When the device is in the erase
mode, DQ2 toggles if this bit is read from an erasing sector.
DQ7
DQ6
DQ2
DQ7
Toggle
1
Erase
0
Toggle
Toggle
Erase-Suspend Read
(Erase-Suspended Sector)
(Note 1)
1
1
Toggle
DQ7
Toggle*1
1*2
Mode
Program
Erase-Suspend Program
*1 : Performing successive read operations from any address will cause DQ6 to toggle.
*2 : Reading the byte address being programmed while in the erase-suspend program mode will indicate logic “1”
at the DQ2 bit. However, successive reads from the erase-suspended sector will cause DQ2 to toggle.
RY/BY
Ready/Busy
The MBM29LV008TA/BA provide a RY/BY open-drain output pin as a way to indicate to the host system that the
Embedded Algorithms are either in progress or has been completed. If the output is low, the devices are busy
with either a program or erase operation. If the output is high, the devices are ready to accept any read/write or
erase operation. When the RY/BY pin is low, the devices will not accept any additional program or erase
commands with the exception of the Erase Suspend command. If the MBM29LV008TA/BA are placed in an
Erase Suspend mode, the RY/BY output will be high, by means of connecting with a pull-up resister to VCC.
During programming, the RY/BY pin is driven low after the rising edge of the fourth write pulse. During an erase
operation, the RY/BY pin is driven low after the rising edge of the sixth write pulse. The RY/BY pin will indicate
a busy condition during the RESET pulse. Refer to “ (8) RY/BY Timing Diagram during Program/Erase
Operations” and “ (9) RESET, RY/BY Timing Diagram” in ■ TIMING DIAGRAM for a detailed timing diagram.
The RY/BY pin is pulled high in standby mode.
Since this is an open-drain output, RY/BY pins can be tied together in parallel with a pull-up resistor to VCC.
RESET
Hardware Reset
The MBM29LV008TA/BA devices may be reset by driving the RESET pin to VIL. The RESET pin has a pulse
requirement and has to be kept low (VIL) for at least 500 ns in order to properly reset the internal state machine.
Any operation in the process of being executed will be terminated and the internal state machine will be reset
to the read mode 20 µs after the RESET pin is driven low. Furthermore, once the RESET pin goes high, the
devices require an additional tRH before it will allow read access. When the RESET pin is low, the devices will
be in the standby mode for the duration of the pulse and all the data output pins will be tri-stated. If a hardware
reset occurs during a program or erase operation, the data at that particular location will be corrupted. Please
note that the RY/BY output signal should be ignored during the RESET pulse. See “ (9) RESET, RY/BY Timing
Diagram” in ■ TIMING DIAGRAM for the timing diagram. Refer to Temporary Sector Unprotection for additional
functionality.
If hardware reset occurs during Embedded Erase Algorithm, there is a possibility that the erasing sector(s)
cannot be used.
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MBM29LV008TA/BA-70/90
Data Protection
The MBM29LV008TA/BA are designed to offer protection against accidental erasure or programming caused by
spurious system level signals that may exist during power transitions. During power up the devices automatically
reset the internal state machine in the Read mode. Also, with its control register architecture, alteration of the
memory contents only occurs after successful completion of specific multi-bus cycle command sequences.
The devices also incorporate several features to prevent inadvertent write cycles resulting form VCC power-up
and power-down transitions or system noise.
Low VCC Write Inhibit
To avoid initiation of a write cycle during VCC power-up and power-down, a write cycle is locked out for VCC less
than 2.3 V (typically 2.4 V). If VCC < VLKO, the command register is disabled and all internal program/erase circuits
are disabled. Under this condition the device will reset to the read mode. Subsequent writes will be ignored until
the VCC level is greater than VLKO. It is the users responsibility to ensure that the control pins are logically correct
to prevent unintentional writes when VCC is above 2.3 V.
If Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector(s) cannot be used.
Write Pulse “Glitch” Protection
Noise pulses of less than 3 ns (typical) on OE, CE, or WE will not initiate a write cycle.
Logical Inhibit
Writing is inhibited by holding any one of OE = VIL, CE = VIH, or WE = VIH. To initiate a write cycle CE and WE
must be a logical zero while OE is a logical one.
Power-Up Write Inhibit
Power-up of the devices with WE = CE = VIL and OE = VIH will not accept commands on the rising edge of write
pulse. The internal state machine is automatically reset to the read mode on power-up.
22
MBM29LV008TA/BA-70/90
■ ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Unit
Min
Max
Tstg
−55
+125
°C
TA
−40
+85
°C
VIN, VOUT
−0.5
VCC + 0.5
V
VCC
−0.5
+5.5
V
VIN
−0.5
+13.0
V
Storage Temperature
Ambient Temperature with Power Applied
Voltage with Respect to Ground All pins except A9,
OE, and RESET *1,*2
Rating
Power Supply Voltage *1,*3
2
A9, OE, and RESET *
*1 : Voltage is defind on the basis of VSS = GND = 0 V.
*2 : Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, input or I/O pins may undershoot
VSS to –2.0 V for periods of up to 20 ns. Maximum DC voltage on output and I/O pins is VCC +0.5 V.
During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods of up to 20 ns.
*3 : Minimum DC input voltage on A9, OE and RESET pins is –0.5 V. During voltage transitions, A9, OE
and RESET pins may undershoot VSS to –2.0 V for periods of up to 20 ns. Voltage difference between input
and supply voltage (VIN – VCC) does not exceed +9.0 V. Maximum DC input voltage on A9, OE and RESET pins
is +13.0 V which may overshoot to +14.0 V for periods of up to 20 ns.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
Parameter
Ambient Temperature
Power Supply Voltage*
Conditions
Symbol

TA
MBM29LV008TA/BA-70
MBM29LV008TA/BA-90
VCC
Value
Unit
Min
Max
−40
+85
°C
+3.0
+3.6
V
+2.7
+3.6
V
* : Voltage is defind on the basis of VSS = GND = 0 V.
Note : Operating ranges define those limits between which the functionality of the devices are guaranteed.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
23
MBM29LV008TA/BA-70/90
■ MAXIMUM OVERSHOOT/MAXIMUM UNDETRSHOOT
+0.6 V
20 ns
20 ns
–0.5 V
–2.0 V
20 ns
Maximum Undershoot Waveform
20 ns
V CC +2.0 V
V CC +0.5 V
+2.0 V
20 ns
20 ns
Maximum Overshoot Waveform 1
20 ns
+14.0 V
+13.0 V
V CC +0.5 V
20 ns
20 ns
Note : This waveform is applied for A9, OE, and RESET.
Maximum Overshoot Waveform 2
24
MBM29LV008TA/BA-70/90
■ DC CHARACTERISTICS
Value
Parameter
Symbol
Test Conditions
Unit
Min
Max
Input Leakage Current
ILI
VIN = VSS to VCC, VCC = VCC Max
–1.0
+1.0
µA
Output Leakage Current
ILO
VOUT = VSS to VCC, VCC = VCC Max
–1.0
+1.0
µA
A9, OE, RESET Inputs Leakage
Current
ILIT
VCC = VCC Max,
A9, OE, RESET = 12.5 V
—
35
µA
CE = VIL, OE = VIH, f=10 MHz
—
22
mA
VCC Active Current *1
ICC1
CE = VIL, OE = VIH, f=5 MHz
—
12
mA
VCC Active Current *2
ICC2
CE = VIL, OE = VIH
—
35
mA
VCC Current (Standby)
ICC3
VCC = VCC Max, CE = VCC ± 0.3 V,
RESET = VCC ± 0.3 V
—
5
µA
VCC Current (Standby, Reset)
ICC4
VCC = VCC Max,
RESET = VSS ± 0.3 V
—
5
µA
VCC Current
(Automatic Sleep Mode) *3
ICC5
VCC = VCC Max, CE = VSS ± 0.3 V,
RESET = VCC ± 0.3 V
VIN = VCC ± 0.3 V or VSS ± 0.3 V
—
5
µA
Input Low Level
VIL
—
–0.5
0.6
V
Input High Level
VIH
—
2.0
VCC + 0.3
V
Voltage for Autoselect, Sector
Protection,and Temporary Sector
Unprotection
(A9, OE, RESET)*4
VID
—
11.5
12.5
V
Output Low Voltage Level
VOL
IOL = 4.0 mA, VCC = VCC Min
—
0.45
V
VOH1
IOH = –2.0 mA, VCC = VCC Min
2.4
—
V
VOH2
IOH = –100 µA
VCC – 0.4
—
V
2.3
2.5
V
Output High Voltage Level
Low VCC Lock-Out Voltage
VLKO
—
*1 : The ICC current listed includes both the DC operating current and the frequency dependent component.
*2 : ICC active while Embedded Algorithm (program or erase) is in progress.
*3 : Automatic sleep mode enables the low power mode when address remain stable for 150 ns.
*4 : (VID – VCC) do not exceed 9 V.
25
MBM29LV008TA/BA-70/90
■ AC CHARACTERISTICS
• Read Only Operations
Value
Symbol
Test
Setup
Parameter
JEDEC
Standard
Read Cycle Time
tAVAV
tRC
Address to Output Delay
tAVQV
Chip Enable to Output Delay
-70*
-90*
Min
Max
Min
Max
—
70

90

ns
tACC
CE = VIL
OE = VIL

70

90
ns
tELQV
tCE
OE = VIL

70

90
ns
Output Enable to Output Delay
tGLQV
tOE
—

30

35
ns
Chip Enable to Output High-Z
tEHQZ
tDF
—

25

30
ns
Output Enable to Output High-Z
tGHQZ
tDF
—

25

30
ns
Output Hold Time From Addresses,
CE or OE, Whichever Occurs First
tAXQX
tOH
—
0

0

ns
—
tREADY
—

20

20
µs
RESET Pin Low to Read Mode
* : Test Conditions:
Output Load: 1 TTL gate and 30 pF (MBM29LV008TA/BA-70)
1 TTL gate and 100 pF (MBM29LV008TA/BA-90)
Input rise and fall times: 5 ns
Input pulse levels: 0.0 V or 3.0 V
Timing measurement reference level
Input: 1.5 V
Output:1.5 V
3.3 V
Diode = 1N3064
or Equivalent
2.7 kΩ
Device
Under
Test
6.2 kΩ
CL
Diode = 1N3064
or Equivalent
Notes: CL = 30 pF including jig capacitance (MBM29LV008TA/BA-70)
CL = 100 pF including jig capacitance (MBM29LV008TA/BA-90)
Test Conditions
26
Unit
MBM29LV008TA/BA-70/90
• Write/Erase/Program Operations
MBM29LV008TA/BA
Symbol
Parameter
JEDEC Standard
-70
-90
Unit
Min
Typ
Max
Min
Typ
Max
Write Cycle Time
tAVAV
tWC
70


90


ns
Address Setup Time
tAVWL
tAS
0


0


ns
Address Hold Time
tWLAX
tAH
45


45


ns
Data Setup Time
tDVWH
tDS
35


45


ns
Data Hold Time
tWHDX
tDH
0


0


ns
Output Enable Setup Time
—
tOES
0


0


ns
Output Enable Read
Hold Time
Toggle and Data Polling
—
tOEH
0


0


ns
10


10


ns
Read Recover Time Before Write
tGHWL
tGHWL
0


0


ns
Read Recover Time Before Write
tGHEL
tGHEL
0


0


ns
CE Setup Time
tELWL
tCS
0


0


ns
WE Setup Time
tWLEL
tWS
0


0


ns
CE Hold Time
tWHEH
tCH
0


0


ns
WE Hold Time
tEHWH
tWH
0


0


ns
Write Pulse Width
tWLWH
tWP
35


45


ns
CE Pulse Width
tELEH
tCP
35


45


ns
Write Pulse Width High
tWHWL
tWPH
25


25


ns
CE Pulse Width High
tEHEL
tCPH
25


25


ns
Byte Programming Operation
tWHWH1
tWHWH1

8


8

µs
Sector Erase Operation*1
tWHWH2
tWHWH2

1


1

s
—
tVCS
50


50


µs
Rise Time to V *
—
tVIDR
500


500


ns
Voltage Transition Time*2
—
tVLHT
4


4


µs
VCC Setup Time
ID 2
—
tWPP
100


100


µs
2
OE Setup Time to WE Active*
—
tOESP
4


4


µs
CE Setup Time to WE Active*2
—
tCSP
4


4


µs
Recover Time From RY/BY
—
tRB
0


0


ns
RESET Pulse Width
—
tRP
500


500


ns
RESET Hold Time Before Read
—
tRH
200


200


ns
Program/Erase Valid to RY/BY Delay
—
tBUSY


90


90
ns
Delay Time from Embedded Output Enable
—
tEOE


30


35
ns
Write Pulse Width*2
*1 : This does not include the preprogramming time.
*2 : This timing is for Sector Protection operation.
27
MBM29LV008TA/BA-70/90
■ ERASE AND PROGRAMMING PERFORMANCE
Limit
Parameter
Unit
Comments
Min
Typ
Max
Sector Erase Time
—
1
10
s
Excludes programming time
prior to erasure
Byte Programming Time
—
8
300
µs
Excludes system-level
overhead
Chip Programming Time
—
8.4
25
s
Excludes system-level
overhead
100,000
—
—
cycle
Erase/Program Cycle
—
■ TSOP(1) PIN CAPACITANCE
Parameter
Symbol
Typ
Max
Unit
Input Capacitance
CIN
VIN = 0
7
10
pF
Output Capacitance
COUT
VOUT = 0
8
10
pF
Control Pin Capacitance
CIN2
VIN = 0
10
12
pF
Note : Test conditions TA = +25°C, f = 1.0 MHz
28
Test Setup
MBM29LV008TA/BA-70/90
■ TIMING DIAGRAM
• Key to Switching Waveforms
WAVEFORM
INPUTS
OUTPUTS
Must Be
Steady
Will Be
Steady
May
Change
from H to L
Will Be
Changing
from H to L
May
Change
from L to H
Will Be
Changing
from L to H
“H” or “L”
Any Change
Permitted
Changing
State
Unknown
Does Not
Apply
Center Line is
HighImpedance
“Off” State
(1) AC Waveforms for Read Operations
tRC
Address
Address Stable
tACC
CE
tOE
tDF
OE
tOEH
WE
tCE
Outputs
High-Z
Output Valid
High-Z
29
MBM29LV008TA/BA-70/90
(2) AC Waveforms for Hardware Reset/Read Operations
tRC
Address
Address Stable
tACC
tRH
RESET
tOH
Outputs
30
High-Z
Output Valid
MBM29LV008TA/BA-70/90
(3) AC Waveforms for Alternate WE Controlled Program Operations
Data Polling
3rd Bus Cycle
Address
555h
tWC
PA
tAS
PA
tRC
tAH
CE
tCH
tCS
tCE
OE
tGHWL
tWP
tWPH
tOE
tWHWH1
WE
tOH
tDS
tDH
Data
A0h
PD
DQ 7
DOUT
DOUT
Notes : • PA is address of the memory location to be programmed.
• PD is data to be programmed at byte address.
• DQ7 is the output of the complement of the data written to the device.
• DOUT is the output of the data written to the device.
• Figure indicates last two bus cycles out of four bus cycle sequence.
31
MBM29LV008TA/BA-70/90
(4) AC Waveforms for Alternate CE Controlled Program Operations
3rd Bus Cycle
Address
Data Polling
PA
555h
tWC
tAS
PA
tAH
WE
tWS
tWH
OE
tGHEL
tCP
tCPH
tWHWH1
CE
tDS
tDH
Data
A0h
PD
DQ 7
DOUT
Notes : • PA is address of the memory location to be programmed.
• PD is data to be programmed at byte address.
• DQ7 is the output of the complement of the data written to the device.
• DOUT is the output of the data written to the device.
• Figure indicates last two bus cycles out of four bus cycle sequence.
32
MBM29LV008TA/BA-70/90
(5) AC Waveforms Chip/Sector Erase Operations
Address
2AAh
555h
tWC
tAS
555h
555h
2AAh
SA*
tAH
CE
tCS
tCH
OE
tGHWL
tWP
tWPH
WE
tDS
AAh
Data
tDH
55h
80h
AAh
55h
10h/
30h
tVCS
VCC
*: SA is the sector address for Sector Erase. Addresses = 555h (Word), AAAh (Byte) for Chip Erase.
33
MBM29LV008TA/BA-70/90
(6) AC Waveforms for Data Polling during Embedded Algorithm Operations
CE
tCH
tOE
tDF
OE
tOEH
WE
tCE
*
DQ7
Data
High-Z
DQ7 =
Valid Data
DQ7
tWHWH1 or 2
DQ6 to DQ0
Data
DQ6 to DQ0 = Output Flag
High-Z
DQ6 to DQ0
Valid Data
tEOE
*: DQ7 = Valid Data (The device has completed the Embedded operation.)
(7) AC Waveforms for Toggle Bit I during Embedded Algorithm Operations
CE
tOEH
WE
tOES
OE
*
DQ 6
Data
DQ 6 = Toggle
DQ 6 =
Stop Toggling
DQ 6 = Toggle
tOE
*: DQ6 stops toggling. (The device has completed the Embedded operation.)
34
Valid
MBM29LV008TA/BA-70/90
(8) RY/BY Timing Diagram during Program/Erase Operations
CE
The rising edge of the last WE signal
WE
Entire programming
or erase operations
RY/BY
tBUSY
(9) RESET, RY/BY Timing Diagram
WE
RESET
tRP
tRB
RY/BY
tREADY
35
MBM29LV008TA/BA-70/90
(10) AC Waveforms for Sector Protection Timing Diagram
A19, A18, A17
A16, A15
A14, A13
SAX
SAY
A0
A1
A6
12 V
3V
A9
tVLHT
12 V
3V
OE
tVLHT
tVLHT
tVLHT
tWPP
WE
tOESP
tCSP
CE
Data
01h
tVCS
VCC
SAX : Sector Address for initial sector
SAY : Sector Address for next sector
36
tOE
MBM29LV008TA/BA-70/90
(11) Temporary Sector Unprotection Timing Diagram
VCC
tVIDR
tVCS
tVLHT
VID
3V
3V
RESET
CE
WE
tVLHT
tVLHT
Program or Erase Command Sequence
RY/BY
Unprotection period
(12) DQ2 vs. DQ6
Enter
Embedded
Erasing
WE
Erase
Suspend
Erase
Enter Erase
Suspend Program
Erase Suspend
Read
Erase
Suspend
Program
Erase
Resume
Erase Suspend
Read
Erase
Erase
Complete
DQ6
DQ2*
Toggle
DQ2 and DQ6
with OE or CE
* : DQ2 is read from the erase-suspended sector.
37
MBM29LV008TA/BA-70/90
(13) Extended Sector Protection Timing Diagram
VCC
tVCS
RESET
tVLHT
tVIDR
Address
SPAX
SPAX
SPAY
A0
A1
A6
CE
OE
TIME-OUT
WE
Data
60h
60h
40h
01h
tOE
SPAX : Sector Address to be protected
SPAY : Next Sector Address to be protected
TIME-OUT : Time-Out window = 150 µs (Min)
38
60h
MBM29LV008TA/BA-70/90
■ FLOW CHART
(1) Embedded ProgramTM Algorithm
EMBEDDED ALGORITHMS
Start
Write Program Command
Sequence
(See below)
Data Polling Device
Increment Address
No
Last Address
?
Yes
Programming Completed
Program Command Sequence (Address/Command):
555h/AAh
2AAh/55h
555h/A0h
Program Address/Program Data
39
MBM29LV008TA/BA-70/90
(2) Embedded EraseTM Algorithm
EMBEDDED ALGORITHMS
Start
Write Erase Command
Sequece
(See below)
Data Polling or Toggle Bit
Successfully Completed
Erasure Completed
Chip Erase Command Sequence
(Address/Command):
Individual Sector/Multiple Sector
Erase Command Sequence
(Address/Command):
555h/AAh
555h/AAh
2AAh/55h
2AAh/55h
555h/80h
555h/80h
555h/AAh
555h/AAh
2AAh/55h
2AAh/55h
555h/10h
Sector Address/30h
Sector Address/30h
Sector Address/30h
40
Additional sector
erase commands
are optional.
MBM29LV008TA/BA-70/90
(3) Data Polling Algorithm
Start
Read
(DQ7 to DQ0)
Addr. = VA
DQ7 = Data?
VA = Address for programming
= Any of the sector addresses within
the sector being erased during
sector erase or multiple
erases operation.
= Any of the sector addresses within
the sector not being protected
during sector erase or multiple
sector erases operation.
Yes
No
No
DQ5 = 1?
Yes
Read
(DQ7 to DQ0)
Addr. = VA
DQ 7 = Data?
Yes
No
Fail
Pass
Note : DQ7 is rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5.
41
MBM29LV008TA/BA-70/90
(4) Toggle Bit Algorithm
Start
Read
(DQ7 to DQ0)
Addr. = “H” or “L”
*1
Read
(DQ7 to DQ0)
Addr. = “H” or “L”
DQ6 = Toggle
?
No
Yes
No
DQ5 = 1?
Yes
*1, *2
Read
(DQ7 to DQ0)
Addr. = “H” or “L”
*1, *2
Read
(DQ7 to DQ0)
Addr. = “H” or “L”
DQ6 = Toggle
?
No
Yes
Program/Erase
Operation Not Complete.
Write Reset Command
Program/Erase
Operation Complete.
*1 : Read toggle bit twice to determine whether it is toggling.
*2 : Recheck toggle bit because it may stop toggling as DQ5 changes to “1”.
42
MBM29LV008TA/BA-70/90
(5) Sector Protection Algorithm
Start
Setup Sector Addr.
(A19, A18, A17, A16, A15, A14, A13)
PLSCNT = 1
OE = VID, A9 = VID,
A6 = CE = VIL, RESET = VIH
A0 = VIL, A1 = VIH
Activate WE Pulse
Time out 100 µs
Increment PLSCNT
WE = VIH, CE = OE = VIL
(A9 should remain VID)
Read from Sector
(Addr. = SA, A0 = VIL, A1 = VIH,
A6 = VIL)*
No
No
PLSCNT = 25?
Yes
Remove VID from A9
Write Reset Command
Data = 01h?
Yes
Yes
Protect Another Sector?
No
Device Failed
Remove VID from A9
Write Reset Command
Sector Protection
Completed
43
MBM29LV008TA/BA-70/90
(6) Temporary Sector Unprotection Algorithm
Start
RESET = VID*1
Perform Erase or
Program Operations
RESET = VIH
Temporary Sector
Unprotection Completed*2
*1 : All protected sectors are unprotected.
*2 : All previously protected sectors are protected once again.
44
MBM29LV008TA/BA-70/90
(7) Extended Sector Protection Algorithm
FAST MODE ALGORITHM
Start
RESET = VID
Wait to 4 µs
Device is Operating in
Temporary Sector
Unprotection Mode
No
Extended Sector
Protection Entry?
Yes
To Setup Sector Protection
Write XXXh/60h
PLSCNT = 1
To Sector Protection
Write SPA/60h
(A0 = VIL, A1 = VIH, A6 = VIL)
Time Out 150 µs
Increment PLSCNT
To Verify Sector Protection
Write SPA/40h
(A0 = VIL, A1 = VIH, A6 = VIL)
Setup Next Sector Address
Read from Sector Address
(A0 = VIL, A1 = VIH, A6 = VIL)
No
No
PLSCNT = 25?
Yes
Remove VID from RESET
Write Reset Command
Device Failed
Data = 01h?
Yes
Protection Other Sector
?
No
Yes
Remove VID from RESET
Write Reset Command
Sector Protection
Completed
45
MBM29LV008TA/BA-70/90
(8) Embedded ProgramTM Algorithm for Fast Mode
FAST MODE ALGORITHM
Start
555h/AAh
Set Fast Mode
2AAh/55h
555h/20h
XXXh/A0h
Program Address/Program Data
Data Polling Device
Verify Byte?
No
In Fast Program
Yes
Increment Address
No
Last Address
?
Yes
Programming Completed
XXXh/90h
Reset Fast Mode
XXXh/F0h
46
MBM29LV008TA/BA-70/90
■ ORDERING INFORMATION
Part number
MBM29LV008TA-70PTN
MBM29LV008TA-90PTN
MBM29LV008TA-70PTR
MBM29LV008TA-90PTR
MBM29LV008BA-70PTN
MBM29LV008BA-90PTN
MBM29LV008BA-70PTR
MBM29LV008BA-90PTR
MBM29LV008
T
A
Package
Access Time
40-pin plastic TSOP (1)
70
(FPT-40P-M06)
90
(Normal bend)
40-pin plastic TSOP (1)
70
(FPT-40P-M07)
90
(Reverse bend)
40-pin plastic TSOP (1)
70
(FPT-40P-M06)
90
(Normal bend)
40-pin plastic TSOP (1)
70
(FPT-40P-M07)
90
(Reverse bend)
-70
Sector Configuration
Remarks
Top sector
Bottom sector
PTN
PACKAGE TYPE
PTN = 40-Pin Thin Small Outline Package
(TSOP) Normal Bend
PTR = 40-Pin Thin Small Outline Package
(TSOP) Reverse Bend
SPEED OPTION
See Product Selector Guide
Device Revision
BOOT CODE SECTOR ARCHITECTURE
T = Top sector
B = Bottom sector
DEVICE NUMBER/DESCRIPTION
MBM29LV008
8Mega-bit (1M × 8-Bit) CMOS Flash Memory
3.0 V-only Read, Program, and Erase
47
MBM29LV008TA/BA-70/90
■ PACKAGE DIMENSIONS
40-pin plastic TSOP (1)
(FPT-40P-M06)
LEAD No.
Note 1) * : Resin protrusion. (Each side : 0.15 (.006) Max) .
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
1
40
Details of "A" part
INDEX
0.25(.010)
0~8˚
0.60±0.15
(.024±.006)
20
21
+0.03
0.17 –0.08
0.10±0.05(.004±.002)
(Stand off)
+.001
.007 –.003
20.00±0.20
(.787±.008)
*18.40±0.20
(.724±.008)
*10.00±0.20
(.394±.008)
+0.10
+.004
1.10 –0.05 .043 –.002
(Mounting height)
0.50(.020)
"A"
0.10(.004)
0.22±0.05
(.009±.002)
C
2003 FUJITSU LIMITED F40007S-c-3-4
0.10(.004)
M
Dimensions in mm (inches) .
Note : The values in parentheses are reference values.
(Continued)
48
MBM29LV008TA/BA-70/90
(Continued)
40-pin plastic TSOP (1)
(FPT-40P-M07)
LEAD No.
Note 1) * : Resin protrusion. (Each side : 0.15 (.006) Max) .
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
1
40
Details of "A" part
INDEX
0.60±0.15
(.024±.006)
0~8˚
0.25(.010)
20
21
0.22±0.05
(.009±.002)
0.10(.004)
0.10±0.05(.004±.002)
(Stand off)
+0.03
0.17 –0.08
0.10(.004)
+.001
.007 –.003
"A"
*18.40±0.20
(.724±.008)
M
0.50(.020)
*10.00±0.20
(.394±.008)
+0.10
+.004
1.10 –0.05 .043 –.002
(Mounting height)
20.00±0.20
(.787±.008)
C
2003 FUJITSU LIMITED F40008S-c-3-4
Dimensions in mm (inches) .
Note : The values in parentheses are reference values.
49
MBM29LV008TA/BA-70/90
FUJITSU LIMITED
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