S72NS-P Based MCPs/PoPs MirrorBit™ Flash Memory and DRAM 128/256/512 Mb (8/16/32 M x 16 bit), 1.8 Volt-only, Multiplexed Simultaneous Read/Write, Burst Mode Flash Memory 128/256 Mb (8/16 M x 16 bit) DDR DRAM on Split Bus S72NS-P Based MCPs/PoPs Cover Sheet Data Sheet (Advance Information) Notice to Readers: This document states the current technical specifications regarding the Spansion product(s) described herein. Each product described herein may be designated as Advance Information, Preliminary, or Full Production. See Notice On Data Sheet Designations for definitions. Publication Number S72NS-P_00 Revision 01 Issue Date September 6, 2006 D a t a S h e e t ( A d va n c e I n fo r m a t i o n ) Notice On Data Sheet Designations Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of product information or intended specifications throughout the product life cycle, including development, qualification, initial production, and full production. In all cases, however, readers are encouraged to verify that they have the latest information before finalizing their design. The following descriptions of Spansion data sheet designations are presented here to highlight their presence and definitions. Advance Information The Advance Information designation indicates that Spansion Inc. is developing one or more specific products, but has not committed any design to production. Information presented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. Spansion Inc. therefore places the following conditions upon Advance Information content: “This document contains information on one or more products under development at Spansion Inc. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed product without notice.” Preliminary The Preliminary designation indicates that the product development has progressed such that a commitment to production has taken place. This designation covers several aspects of the product life cycle, including product qualification, initial production, and the subsequent phases in the manufacturing process that occur before full production is achieved. Changes to the technical specifications presented in a Preliminary document should be expected while keeping these aspects of production under consideration. Spansion places the following conditions upon Preliminary content: “This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications.” Combination Some data sheets contain a combination of products with different designations (Advance Information, Preliminary, or Full Production). This type of document distinguishes these products and their designations wherever necessary, typically on the first page, the ordering information page, and pages with the DC Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first page refers the reader to the notice on this page. Full Production (No Designation on Document) When a product has been in production for a period of time such that no changes or only nominal changes are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include those affecting the number of ordering part numbers available, such as the addition or deletion of a speed option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following conditions to documents in this category: “This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the valid combinations offered may occur.” Questions regarding these document designations may be directed to your local Spansion sales office. ii S72NS-P Based MCPs/PoPs September 6, 2006 S72NS-P_00-01 S72NS-P Based MCPs/PoPs MirrorBit™ Flash Memory and DRAM 128/256/512 Mb (8/16/32 M x 16 bit), 1.8 Volt-only, Multiplexed Simultaneous Read/Write, Burst Mode Flash Memory 128/256 Mb (8/16 M x 16 bit) DDR DRAM on Split Bus Data Sheet (Advance Information) Features Power supply voltage of 1.7 V to 1.95 V Packages Burst Speeds – 11.0 x 10.0 mm, 133-ball MCP – 8.0 x 8.0 mm, 133-ball MCP – 12.0 x 12.0 mm, 128-ball PoP – Flash = 66 MHz, 80 MHz – DRAM = 133 MHz Operating Temperature of –25°C to +85°C General Description This document contains information on the S72NS-P MCP stacked products. Refer to the S29NS-P data sheet (S29NS-P_00) for full electrical specifications of the Flash memory component. The S72NS Series is a product line of stacked products (MCPs and PoPs), and consists of: NS family multiplexed Flash memory die DDR DRAM The products covered by this document are listed in the tables below. DRAM Density Flash Density 128 Mb 128 Mb S72NS128PD0 256 Mb S72NS256PD0 512 Mb S72NS512PD0 256 Mb S72NS512PE0 For detailed specifications, please refer to the individual data sheets. Density Manufacturer Publication Number DRAM1 SDRAM_03 DRAM5 SDRAM_07 Manufacturer Publication Number 128 Density DRAM1 TBD DRAM5 SDRAM_11 256 Publication Number S72NS-P_00 Revision 01 Issue Date September 6, 2006 This document contains information on one or more products under development at Spansion Inc. The information is intended to help you evaluate this product. Do not design in this product without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed product without notice. D a t a 1. S h e e t ( A d va n c e I n fo r m a t i o n ) Product Selector Guide Device OPN Flash Density DDR DRAM Density S72NS128PD0AJBGG Flash Speed (MHz) DDR DRAM Speed (MHz) Supplier Package 66 DRAM1 S72NS128PD0AJBGC 80 128 Mb 128 Mb S72NS128PD0AJBLG 133 8.0 x 8.0mm133-ball MCP 66 DRAM5 S72NS128PD0AJBLC 80 S72NS128PD0KJFGG 66 DRAM1 S72NS128PD0KJFGC 80 128 Mb 128 Mb S72NS128PD0KJFLG 133 12.0 x 12.0mm 128-ball PoP 66 DRAM5 S72NS128PD0KJFLC 80 S72NS256PD0AJBGG 66 S72NS256PD0AJBGC 80 DRAM1 256 Mb 128 Mb S72NS256PD0AJBLG 133 8.0 x 8.0mm133-ball MCP 66 DRAM5 S72NS256PD0AJBLC 80 S72NS256PD0KJFGG 66 DRAM1 S72NS256PD0KJFGC 80 256 Mb 128 Mb S72NS256PD0KJFLG 133 12.0 x 12.0mm 128-ball PoP 66 DRAM5 S72NS256PD0KJFLC 80 S72NS512PD0AJGGG 66 DRAM1 S72NS512PD0AJGGC 80 512 Mb 128 Mb S72NS512PD0AJGLG 133 11.0 x 10.0mm 133-ball MCP 66 DRAM5 S72NS512PD0AJGLC 80 S72NS512PD0KJFGG 66 S72NS512PD0KJFGC 80 DRAM1 512 Mb 128 Mb 133 S72NS512PD0KJFLG 66 S72NS512PD0KJFLC 80 S72NS512PE0AJGGG 66 12.0 x 12.0mm 128-ball PoP DRAM5 DRAM1 S72NS512PE0AJGGC 80 512 Mb 256 Mb S72NS512PE0AJGLG 133 11.0 x 10.0mm 133-ball MCP 66 DRAM5 S72NS512PE0AJGLC 80 S72NS512PE0KJFGG 66 S72NS512PE0KJFGC 80 DRAM1 512 Mb S72NS512PE0KJFLG 256 Mb 133 12.0 x 12.0mm 128-ball PoP 66 DRAM5 S72NS512PE0KJFLC 2 80 S72NS-P Based MCPs/PoPs S72NS-P_00_01 September 6, 2006 D a t a S h e e t ( A d va n c e In fo r m a t i o n ) 2. Product Block Diagram F-RST# F-ACC F-WP# RST# A15-A0 ACC WP# F-CE# CE# F-OE# OE# F-WE# WE# AVD# AVD# F-VSS VSS ADQ15-ADQ0 DQ15-DQ0 MUX Flash Memory NS-P CLK F-CLK RDY F-RDY Amax - A16 Amax - A16 VCC VCCQ F-VCC F-VCCQ D-CLK F2-CE# D-RAS# RAS# CLK D-CAS# CAS# CLK# D-CLK# DQS0 D-LDQS DQS1 D-UDQS LDQM D-LDQM UDQM D-UDQM D-BA0 BA0 D-BA1 BA1 D-CKE CKE D-WE# WE# D-CE# CE# DDR DRAM Memory D-VCCQ DQ15-DQ0 VSS D-Amax - D-A0 D-VCC TEST VSSQ D-TEST D-DQ15 - D-DQ0 D-VSS D-VSSQ VCC VCCQ Notes: 1. Amax indicates highest address bit for memory component: a. Amax = A24 for NS512P, A23 for NS256P, A22 for NS128P b. Amax = A11 for 128 Mb DDR DRAM c. Amax = A12 for 256Mb DDR DRAM 2. For Flash, A15 - A0 is tied to DQ15 - DQ0. S72NS-P_00_01 September 6, 2006 S72NS-P Based MCPs/PoPs 3 D a t a S h e e t ( A d va n c e I n fo r m a t i o n ) 3. Connection Diagrams Figure 3.1 133-ball Fine-Pitch Ball Grid Array MCP 1 2 DNU DNU 3 4 5 6 7 8 9 10 11 12 13 14 Legend DNU DNU Index Location DNU Do Not Use A D-VSSQ D-VCCQ D-DQ9 D-DQ8 D-VSS D-VCC D-VCC D-DQ5 D-DQ3 D-VSSQ B DNU D-VSS D-DQ13 D-UDQS D-DQ10 D-VSSQ D-VCCQ D-VCCQ D-LDQM D-DQ6 D-DQ4 D-DQ1 D-VCCQ C D-VCC D-DQ15 D-DQ14 D-DQ12 D-DQ11 D-UDQM D-VSS D-VCC D-VSSQ D-DQ7 D-LDQS D-DQ2 D-DQ0 D-VSS No Connect D NC RFU NC INDEX F-OE# ADQ8 D-VCC DRAM Only E A24 A22 A17 ADQ9 ADQ1 ADQ0 A23 A19 A18 F-VSS ADQ3 ADQ2 Code Flash Only F Reserved for Future Use G F-CE# F-WP# F-WE# F-VCCQ ADQ11 ADQ10 F-ACC F-VCC F-CLK ADQ13 ADQ12 ADQ4 A16 F-VSS NC F-VSS F-VSS ADQ5 A21 F-AVD# NC NC ADQ7 ADQ6 A20 F-RST# D-CE# H J K L F-VCCQ ADQ15 ADQ14 M NC NC D-A3 D-A6 D-A9 D-CKE D-VSS D-WE# D-A10 D-A1 NC NC F-RDY F-VSS D-A5 D-A8 D-CAS# D-CLK# D-BA1 D-A11 D-A2 D-A12 NC F-VCC DNU D-A4 D-A7 D-RAS# D-CLK D-VCC D-BA0 D-A0 D-VCC D-VSS DNU DNU N DNU D-VSS D-VCC P DNU DNU NC Note: Additional NC locations are in reference to the superset connection diagram shown here 4 Device OPN Flash Address Amax DDR DRAM Address Amax Additional NC Locations S72NS128PD0 A22 A11 Ball F1, Ball E1, Ball N11 S72NS256PD0 A23 A11 Ball E1, Ball N11 S72NS512PD0 A24 A11 Ball N11 S72NS512PE0 A24 A12 N/A S72NS-P Based MCPs/PoPs S72NS-P_00_01 September 6, 2006 D a t a S h e e t ( A d va n c e In fo r m a t i o n ) Figure 3.2 128-ball Fine-Pitch Ball Grid Array, PoP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 NC NC ADQ8 ADQ9 ADQ10 ADQ11 ADQ12 ADQ13 ADQ14 ADQ15 D-VSS D-VSS D-VCCQ D-VCCQ D-VCC D-VCC D-VSSQ NC NC ADQ0 ADQ1 ADQ2 D-VSS D-VCCQ D-VCCQ D-VCCQ D-VCC 18 Legend NC NO Connect A B ADQ3 ADQ4 ADQ5 ADQ6 ADQ7 F-CLK NC D-VSSQ NOR Flash Only C F-AVD# F-OE# D-VSSQ D-VSSQ DDR DRAM Only D F-RST# F-RDY D-UDQS D-DQ15 F-VCCQ F-WE# D-DQ13 D-DQ14 F-VCCQ F-VSS D-DQ11 D-DQ12 E F G F-VSS F-VSS D-DQ9 D-DQ10 F-VSS F-VSS D-DQ8 D-UDQM F-VSS F-VSS D-CLK D-CLK# A23 F1-CE# LDQM D-DQ07 A20 A18 D-DQ6 D-DQ5 A21 A16 D-DQ4 D-DQ3 F-ACC A19 D-DQ2 D-DQ1 F-VCC F-VCC D-DQ0 D-LDQS A17 A22 D-VCCQ D-VSSQ NC A24 D-VCC D-VSSQ F-WP# NC NC NC D-CE# NC NC NC NC D-VCC D-VCC H J K L M N P R T U D-A3 D-A1 D-A10 D-CKE D-A12 D-A11 D-WE# D-A9 D-A7 D-CAS# D-A5 NC D-VSS D-A2 D-A0 D-BA1 D-BA0 D-VSS D-VSS NC D-A8 D-RAS# D-A6 D-A4 NC V Note: Additional NC locations are in reference to the superset connection diagram shown here. Device OPN Flash Address Amax DDR DRAM Address Amax Additional NC Locations S72NS128PD0 A22 A11 Ball K1, Ball T2, Ball U10 S72NS256PD0 A23 A11 Ball K1, Ball U10 S72NS512PD0 A24 A11 Ball U10 S72NS512PE0 A24 A12 N/A S72NS-P_00_01 September 6, 2006 S72NS-P Based MCPs/PoPs 5 D a t a 4. S h e e t ( A d va n c e Input/Output Descriptions Signal Description Amax – A16 = Flash Address inputs ADQ15 – ADQ0 = Flash multiplexed Address and Data Flash F-CE# = Flash Chip-enable input. Asynchronous relative to CLK for Burst Mode F-OE# = Flash Output Enable input. Asynchronous relative to CLK for Burst mode. X F-WE# = Flash Write Enable input X F-VCC = Flash device power supply (1.7 V to 1.95 V) X F-VCCQ = Flash Input/Output Buffer power supply X F-VSS F-RDY = Flash Ground X Flash ready output. Indicates the status of the Burst read. VOL = data invalid. VOH = data valid. X = Flash Clock. The first rising edge of CLK in conjunction with AVD# low latches the address input and activates burst mode operation. After the initial word is output, subsequent rising edges of CLK increment the internal address counter. CLK should remain low during asynchronous access. X Flash Address Valid input. Indicates to device that the valid address is present on the address inputs. VIL = for asynchronous mode, indicates valid address; for burst mode, causes starting address to be latched on rising edge of CLK. VIH= device ignores address inputs X = F-AVD# F-RST# F-WP# = Flash hardware reset input. VIL= device resets and returns to reading array data X = Flash hardware write protect input. VIL = disables program and erase functions in the four outermost sectors X = Flash accelerated input. At VHH, accelerates programming; automatically places device in unlock bypass mode. At VIL, disables all program and erase functions. Should be at VIH for all other conditions. X F-ACC DRAM X = F-CLK 6 I n fo r m a t i o n ) D-A12 – D-A0 = DRAM Address inputs. X D-DQ15 – D-DQ0 = DRAM Data input/output X D-CLK = DRAM System Clock X D-CE# = DRAM Chip Select X D-CKE = DRAM Clock Enable X D-BA1 – BA0 = DRAM Bank Select X D-RAS# = DRAM Row Address Strobe X D-CAS# = DRAM Column Address Strobe X D-UDQM – D-LDQM = DRAM Data Input Mask X D-WE# = DRAM Write Enable input X D-VSS = DRAM Ground X D-VSSQ = DRAM Input/Output Buffer ground X D-VCCQ = DRAM Input/Output Buffer power supply X D-VCC = DRAM device power supply X D-UDQS = DRAM Upper Data Strobe, output with read data and input with write data X D-LDQS = DRAM Lower Data Strobe, output with read data and input with write data X D-CLK# = DDR Clock for negative edge of CLK X RFU = Reserved for Future Use NC = No Connect. Can be connected to ground or left floating. DNU = Do Not Use. This signal must be left floating S72NS-P Based MCPs/PoPs S72NS-P_00_01 September 6, 2006 D a t a 5. S h e e t ( A d va n c e In fo r m a t i o n ) Ordering Information The order number (Valid Combination) is formed by the following: S72NS 256 P D0 AJ B L G 3 PACKING TYPE 0 = Tray 2 = 7-inch Tape and Reel 3 = 13-inch Tape and Reel FLASH and DDR SPEED G = 66 MHz Flash, 133 MHz DDR DRAM C = 80 MHz Flash, 133 MHz DDR DRAM DDR SUPPLIER G = DRAM Type 1 x16 DDR DRAM L = DRAM Type 5 x16 DDR DRAM PACKAGE MODIFIER G = 133-ball, 11x10mm, FBGA MCP B = 133-ball, 8x8mm, FBGA MCP F = 128-ball, 12x12mm, FBGA PoP PACKAGE AND MATERIAL TYPE AJ = Thin profile Fine-pitch BGA Pb-free LF35 MCP (0.5 mm pitch) KJ = Thin profile Fine-pitch BGA Pb-free PoP (0.65 mm pitch) DDR DRAM AND DATA FLASH DENSITY D0 = 128 Mb DRAM, No Data Flash E0 = 256 Mb DRAM, No Data Flash PROCESS TECHNOLOGY P = 90 nm, MirrorBitTM Technology CODE FLASH DENSITY 512 = 512 Mb 256 = 256 Mb 128 = 128 Mb PRODUCT FAMILY S72NS Multi-Chip Product (MCP) 1.8 V Multiplexed, SRW, Burst Mode Flash and DDR DRAM on Split Bus Valid Combinations Product Family Code Flash Density (Mb) Process Technology DRAM Density (Mb) Package Type/ Material D0 AJB, KJF DDR Vendor 128 S72NS 256 Flash & DDR Speed Packing Type G, C P G, L G, C 512 D0, E0 0, 2, 3 (Note 1) AJG, KJF Notes: 1. Packing Type 0 is standard. Specify other options as required. 2. BGA package marking omits leading “S” and packing type designator from ordering part number. 3. Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. S72NS-P_00_01 September 6, 2006 S72NS-P Based MCPs/PoPs 7 D a t a 6. 6.1 S h e e t ( A d va n c e I n fo r m a t i o n ) Physical Dimensions NLC133—133-ball Fine-Pitch Ball Grid Array (FBGA) 11.0 x 10.0 mm NOTES: PACKAGE NLC 133 JEDEC N/A DxE 11.0 mm x 10.00 mm PACKAGE SYMBOL MIN NOM MAX NOTE A 0.90 1.00 1.10 PROFILE A1 0.20 0.25 0.30 BALL HEIGHT A2 0.70 0.76 0.82 BODY THICKNESS D 10.9 11.0 11.1 BODY SIZE E 9.9 10.0 10.1 BODY SIZE D1 6.50 BSC. MATRIX FOOTPRINT E1 6.50 BSC. MATRIX FOOTPRINT MD 14 MATRIX SIZE D DIRECTION ME 14 MATRIX SIZE E DIRECTION n Øb 133 0.25 0.30 DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. 3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010. 4. e REPRESENTS THE SOLDER BALL GRID PITCH. 5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. 6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. 7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. BALL COUNT 0.35 eE 0.50 BSC. BALL PITCH 0.50 BSC BALL PITCH 0.25 BSC. D5-D11, E4-E11, F4-F11 G4-G11, H4-H11, J4-J11 K4-K11, L4-L11 WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. BALL DIAMETER eD SD / SE 1. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. 9. N/A SOLDER BALL PLACEMENT DEPOPULATED SOLDER BALLS 10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. 3436 \ 16-039.22 \ 12.09.04 8 S72NS-P Based MCPs/PoPs S72NS-P_00_01 September 6, 2006 D a t a 6.2 S h e e t ( A d va n c e In fo r m a t i o n ) NSC133—133-ball Fine-Pitch Ball Grid Array (FBGA) 8.0 x 8.0 mm NOTES: PACKAGE NSC 133 JEDEC N/A DxE 8.00 mm x 8.00 mm PACKAGE SYMBOL MIN NOM MAX NOTE 1. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. 3. BALL POSITION DESIGNATION PER JESD 95-1 SPP-010. A 0.90 1.00 1.10 PROFILE 4. e REPRESENTS THE SOLDER BALL GRID PITCH. A1 0.20 0.25 0.30 BALL HEIGHT 5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. A2 0.70 0.76 0.82 BODY THICKNESS D 8.00 BSC BODY SIZE E 8.00 BSC BODY SIZE D1 6.50 BSC. MATRIX FOOTPRINT E1 6.50 BSC. MD 14 MATRIX SIZE D DIRECTION ME 14 MATRIX SIZE E DIRECTION n Øb MATRIX FOOTPRINT 133 0.25 eE 0.30 SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. 6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. 7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. BALL COUNT 0.35 WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. BALL DIAMETER 0.50 BSC. BALL PITCH eD 0.50 BSC BALL PITCH SD / SE 0.25 BSC. SOLDER BALL PLACEMENT D5-D11,E4-E11,F4-F11,G4-G11 DEPOPULATED SOLDER BALLS H4-H11,J4-J11,K4-K11,L4-L11 WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. 9 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. 3583 \ 16-039.22 \ 8.15.06 S72NS-P_00_01 September 6, 2006 S72NS-P Based MCPs/PoPs 9 D a t a 6.3 S h e e t ( A d va n c e I n fo r m a t i o n ) ALJ128—128-ball Fine-Pitch Ball Grid Array (FBGA) 12.0 x 12.0 mm A D PIN A1 CORNER D1 9 INDEX MARK eD SD PIN A1 CORNER 7 A B C D E F G SE 7 H J E E1 K L M eE N P R T U 0.10 C V 18 17 16 15 14 13 12 11 10 (2X) 9 8 7 6 5 4 3 2 1 B TOP VIEW BOTTOM VIEW 0.10 C (2X) 0.10 C A A2 A1 C b 128X 0.15 0.08 M C A B M C NOTES: PACKAGE ALJ 128 JEDEC N/A DxE 12.00 mm x 12.00 mm PACKAGE SYMBOL 1. MIN NOM MAX A --- --- 1.15 A1 0.35 --- --- A2 0.60 --- 0.72 NOTE PROFILE BALL HEIGHT BODY THICKNESS D 12.00 BSC. BODY SIZE E 12.00 BSC. BODY SIZE D1 11.05 BSC. MATRIX FOOTPRINT E1 11.05 BSC. MATRIX FOOTPRINT MD 18 MATRIX SIZE D DIRECTION ME 18 MATRIX SIZE E DIRECTION n 128 BALL COUNT N 128 MAXIMUM NUMBER OF BALLS R Øb 2 0.40 0.45 NUMBER OF LAND PERIMETERS 0.50 eE 0.65 BSC. BALL PITCH 0.65 BSC BALL PITCH 0.325 BSC. C3~C16, D3~D16, E3~E16, F3~F16 G3~G16, H3~H16, J3~J16, K3~K16 L3~L16, M3~M16, N3~N16, P3~P16 R3~R16, T3~T16 ALL DIMENSIONS ARE IN MILLIMETERS. 3. BALL POSITION DESIGNATION PER JEP95, SECTION 3.0, SPP-010. 4. e REPRESENTS THE SOLDER BALL GRID PITCH. 5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. N IS THE MAXIMUM NUMBER OF BALLS ON THE FBGA PACKAGE. 6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. DATUM C IS THE SEATING PLANE AND IS DEFINED BY THE CROWNS OF THE SOLDER BALLS. 7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 SOLDER BALL PLACEMENT DEPOPULATED SOLDER BALLS DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. 2. BALL DIAMETER eD SE / SD 0.10 C SIDE VIEW 6 8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. 9 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. 10 OUTLINE AND DIMENSIONS PER CUSTOMER REQUIREMENT. 3561 16 038 24 \ 5 15 6 10 S72NS-P Based MCPs/PoPs S72NS-P_00_01 September 6, 2006 D a t a 6.4 S h e e t ( A d va n c e In fo r m a t i o n ) ASF128—128-ball Fine-Pitch Ball Grid Array (FBGA) 12.0 x 12.0 mm NOTES: PACKAGE ASF128 JEDEC N/A DxE 12.00 mm x 12.00 mm PACKAGE SYMBOL MIN NOM MAX NOTE A 0.95 1.05 1.15 A1 0.35 0.40 0.45 BALL HEIGHT A2 0.59 --- 0.72 BODY THICKNESS PROFILE D 12.00 BSC. BODY SIZE E 12.00 BSC. BODY SIZE D1 11.05 BSC. MATRIX FOOTPRINT E1 11.05 BSC. MATRIX FOOTPRINT MD 18 MATRIX SIZE D DIRECTION ME 18 MATRIX SIZE E DIRECTION n 128 BALL COUNT N 128 MAXIMUM NUMBER OF BALLS R Øb 2 0.40 0.45 NUMBER OF LAND PERIMETERS 0.50 eE 0.65 BSC. BALL PITCH 0.65 BSC BALL PITCH 0.325 BSC. C3-C16,D3-D16,E3-E16, F3-F16,G3-G16,H3-H16, J3-J16,K3-K16,L3-L16, M3-M16,N3-N16,P3-P16, R3-R16,T3-T16 DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. 3. BALL POSITION DESIGNATION PER JEP95, SECTION 3.0, SPP-010. 4. e REPRESENTS THE SOLDER BALL GRID PITCH. 5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME. N IS THE MAXIMUM NUMBER OF BALLS ON THE FBGA PACKAGE. 6 7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 SOLDER BALL PLACEMENT DEPOPULATED SOLDER BALLS DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A PLANE PARALLEL TO DATUM C. DATUM C IS THE SEATING PLANE AND IS DEFINED BY THE CROWNS OF THE SOLDER BALLS. BALL DIAMETER eD SE / SD 1. 8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. 9 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. 10 OUTLINE AND DIMENSIONS PER CUSTOMER REQUIREMENT. 3581\16-039.24\8.3.6 S72NS-P_00_01 September 6, 2006 S72NS-P Based MCPs/PoPs 11 D a t a 7. S h e e t ( A d va n c e I n fo r m a t i o n ) Revision History 7.1 Revision 01 (September 6, 2006) Initial release. Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. Trademarks and Notice The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright © 2006 Spansion Inc. All Rights Reserved. Spansion, the Spansion logo, MirrorBit, ORNAND, and combinations thereof are trademarks of Spansion Inc. Other names are for informational purposes only and may be trademarks of their respective owners. 12 S72NS-P Based MCPs/PoPs S72NS-P_00_01 September 6, 2006