74GTL1655A 16 BIT LVTTL TO GTL/GTL + UNIVERSAL BUS TRANSCEIVERS WITH LIVE INSERTION ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED GTL/GTL+ UNIVERSAL TRANSCEIVER: tPD = 4.6 ns (MAX.) A to B at VCC = 3V COMBINES D-TYPE LATCHES AND D-TYPE FLIP-FLOPS FOR OPERATION IN TRANSPARENT, LATCHED, OR CLOCKED MODE OPERATING VOLTAGE RANGE: VCC(OPR) = 3.0V to 3.6V SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL=24mA (MIN) at VCC = 3V (A PORT) OUTPUT IMPEDANCE: IOL = 100mA (MIN) at VCC = 3V (B PORT) HIGH-IMPEDANCE STATE DURING POWER UP AND POWER DOWN up to VCC=BIASVCC=1.5V PERMITT LIVE INSERTION B-PORT PRECHARGED BY BIASVCC REDUCE NOISE ON THE LINE DURING LIVE INSERTION EDGE RATE-CONTROL INPUT CONFIGURES THE B-PORT OUTPUT RISE AND FALL TIMES BUS HOLD ON DATA INPUTS ELIMINATES THE NEED FOR EXTERNAL PULL-UP/ PULL-DOWN RESISTORS (A PORT) DISTRIBUTED VCC AND GND PIN CONFIGURATION MINIMIZES HIGH-SPEED SWITCHING NOISE IN PARALLEL COMUNICATIONS PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 1655 ) s ( ct TSSOP Table 1: Order Codes ) s t( PACKAGE T&R TSSOP 74GTL1655ATTR o r P Figure 1: Pin Connection e t le c u d o s b O - u d o r P e t e l o DESCRIPTION The 74GTL1655A devices are 16-bit high-drive (100mA), low-output-impedance universal bus transceivers designed for backplane applications. The 74GTL1655A devices provide live-insertion capability for backplane applications by tolerating active signals on the data ports when the devices are powered off. In addition, a biasing pin preconditions the GTL/GTL+ port to minimize disruption to an active backplane. The edge rate-control (VERC) input is provided so the rise and fall time of the B outputs can be configured to optimize for various backplane loading conditions. Data flow in each direction is s b O October 2004 Rev. 1 1/16 74GTL1655A controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLK) inputs. For A-to-B data flow, the devices operate in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLK is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OEAB is low, the outputs are active. When OEAB is high, the outputs are in the high-impedance state. Data flow for B to A is similar to that of A to B, but uses OEBA, LEBA, and CLK. The output enable (OE) is used to disable both ports simultaneously. Active bus-hold circuitry is provided on the A port to hold unused or floating data inputs at a valid logic level. When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5V, OE should be tied to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. All input and output are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. Figure 2: Input And Output Equivalent Circuit c u d e t le ) s ( ct Table 2: Pin Description u d o PIN N° r P e o r P o s b O - SYMBOL NAME AND FUNCTION 1, 2 4, 6, 7, 9, 11, 13, 14, 16 17, 19, 20, 22, 23, 25, 27, 29 31, 32 33 34, 35 36 1OEAB, 1OEBA 1A1 to 1A8 2A1 to 2A8 2OEAB, 2OEBA OE 2LEBA, 2LEAB BIAS VCC 37, 38, 40, 42, 43, 45, 46, 48 41 2B8 to 2B1 VREF Data Inputs/Outputs GTL/GTL+ GTL Voltage Reference Input 49, 51, 52, 54, 55, 56, 58, 59 61 2A1 to 2A8 VERC Data Inputs/Outputs GTL/GTL+ Edge Rate Control 62, 63 64 5, 8, 10, 12, 18, 21, 24, 26, 30, 39, 44, 47, 53, 57, 60 3, 15, 28, 50 1LEBA, 1LEAB CLK GND t e l o s b O 2/16 VCC Output Enable Input Data Inputs/Outputs LVTTL Data Inputs/Outputs LVTTL Output Enable Input Output Enable Input Latch Enable Pre-Charge Supply Voltage Latch Enable Clock Input (LOW to HIGH edge triggered) Ground (0V) Positive Supply Voltage ) s t( 74GTL1655A Table 3: Function Table (1) INPUTS OUTPUT MODE OEAB LEAB CLK A B H L L X H H X X X X L H Z L H Isolation Transparent Transparent L L L L Registered L L H H L L H X B0 (2) Previous State L L L X B0(3) Previous State Registered 1) A to B data flow is shown. B to A flow is similar, but uses OEBA, LEBA and CLK 2) Output level before the indicated steady-state input conditions were established, provided that CLK was high before LEAB went low 3) Output level before the indicated steady-state input conditions were established Table 4: Output Enable Truth Table INPUTS OUTPUTS OE OEAB OEBA A PORT L L L L H L L H H X L H L H X Active Z Active Z Z o s b O - Table 5: B-Port Edge Rate Control (VERC) Truth Table INPUT VERC LOGIC LEVEL r P e t le uc ) s t( B PORT od Active Active Z Z Z OUTPUT B PORT EDGE RATE NOMINAL VOLTAGE (s) H ct L u d o VCC Slow GND Fast r P e t e l o s b O 3/16 74GTL1655A Figure 3: Logic Diagram c u d e t le ) s ( ct u d o r P e t e l o s b O 4/16 o s b O - o r P ) s t( 74GTL1655A Table 6: Absolute Maximum Ratings Symbol Parameter Value Unit VCC Supply Voltage, Bias VCC -0.5 to +4.6 V VIA DC Input Voltage A Side, Control Input -0.5 to +4.6 V VIB DC Input Voltage B Side, VERC, VREF -0.5 to +4.6 V VOA DC Output Voltage A Side -0.5 to +4.6 V VOB DC Output Voltage B Side -0.5 to +4.6 V IIK DC Input Diode Current - 50 mA IOK DC Output Diode Current - 50 mA IOA DC Output Current A Side ± 48 mA IOB DC Output Current B Side in the Low State 200 mA Tstg Storage Temperature TL Lead Temperature (10 sec) -65 to +150 °C 300 °C ) s t( Absolute Maximum Rating are those value beyond which damage to the device may occur. Functional operation under these condition is not implied c u d Table 7: Recommended Operating Conditions 3.0 o r P 3.3 3.6 1.14 1.35 0.74 0.87 1.2 1.5 0.8 1 Value Symbol Parameter Min. VCC Supply Voltage VTT Termination Voltage VREF VI GTL GTL+ GTL GTL+ B port Supply Voltage Input Voltage VIH High Level Input Voltage VIL c u d Low Level Input Voltage o r P e IIK Input Clamp Current IOH High Level Output Current t e l o IOL dt/dVCC s b O Top Low Level Output Current (t s) e t le Typ. 0 1.26 1.65 0.87 1.1 VTT other 0 VCC B port VREF+0.05 other B port 2 o s b O - V V V V V VREF-0.05 other Unit Max. 0.8 V -18 mA A port -24 mA A port B port 24 100 mA Power -up ramp rate 200 Operating Temperature -40 µs/V 85 °C 1) VTT and RTT can be adjusted to adapt backplane impedance if DC recommended IOL ratings are not exceeded 2) VREF can be adjusted to optimize noise margin (typ two-thirds VTT) 5/16 74GTL1655A Table 8: DC Specifications Test Condition Symbol VIK VOLA VOLB Ioff II(HOLD) IOZHB IOZLB IOZ (*) IOZPU** IOZPD** ∆ICC Low Level Output Voltage B Port bs Max. -1.2 3 to 3.6 IO=-100µA VCC-0.2 3 IO=-12mA 2.4 2.2 V V 3 IO=-24mA 3 to 3.6 IO=100µA 3 IO=12mA 0.4 3 IO=24mA 0.55 3 IO=40mA 0.2 3 IO=80mA 0.4 0.5 0.2 V V ) s t( 3 Control 3.6 VI = VCC or GND ±10 µA B Port 3.6 VI = VTT or GND ±10 VI or VO = 0 to 3.6V uc µA 0 ±100 µA 3 VI = 0.8V 3 VI = 2V 3.6 VI = 0 to VCC 3.6 VO = 1.5V 3-State Output Current B Port 3-State Output Current B Port 3-State Output Current A Port 3-State Output Current A Port 3-State Output Current A Port 3.6 t c u od r P e (s) 0 to 1.5 ∆ Supply Current except B port Control Input Capacitance Input Capacitance A Port Input Capacitance B Port 1.5 to 0 3.6 3.6 d o r P e let -75 20 µA ± 500 µA -10 µA VO = VCC or GND ±10 µA VO = 0.5 to 3V OE = LOW VO = 0.5 to 3V OE = LOW VI = VCC or GND IO=0 ±50 µA ±50 µA 40 mA 1 mA o s b O VO = 0.4V 3.6 75 10 10 VIN = VCC or GND One input VCC =0.6V VIN = VCC or GND 3 5 pF VO = VCC or GND 5 6 6 8 pF (*) For I/O ports, the parameter IOZ includes the input leakage current (**) Is also guaranteed when connecting BiasVCC with VCC. 6/16 Typ. IO=100mA Power Off Leakage Current Bus Hold A Port Input Current t e l o CI O Low Level Output Voltage A Port Quiescent Supply Current ICC Min. Unit 3 High Level Output Voltage A Port Input Current II -40 to 85 °C VCC (V) High Level Input Voltage VOHA CO Parameter Value 74GTL1655A Table 9: Live Insertion Specifications Test Condition Symbol Parameter Value ICC (Bias Quiescent Bias Current VCC) Unit -40 to 85 °C VCC (V) Min. 0 to 3.0 VO(Bport) = 0 to 1.2V 3 to 3.6 VI(Bias Vcc) = 3 to 3.6V VO Output Voltage B Port 0 VI(Bias Vcc) = 3.3V 1 IO Output Current B Port 0 VO(Bport) = 0.4V VI(Bias Vcc) = 3 to 3.6V -1 0 to 3.6 0 to 1.5 OE = 3.3V OE = 0 to 3.3V Typ. Max. 5 mA 10 µA 1.2 V µA 100 100 µA µA Table 10: AC Electrical Characteristics for GTL (VCC=3.3 ± 0.3V, VTT=1.2V, VREF=0.8V, VERC=VCC or GND) Value Symbol Parameter Test Condition -40 to 85 °C Min. fMAX Maximum Frequency tPLH A to B or B to A Propagation Delay Time A to B VERC=VCC R1=12.5Ω CL=30pF Propagation Delay Time CK to B VERC=VCC RL=12.5Ω CL=30pF Propagation Delay Time LEAB to B VERC=VCC RL=12.5Ω CL=30pF Enable Delay Time OEAB or OE to B Disable Delay Time OEAB or OE to B Propagation Delay Time A to B VERC=VCC RL=12.5Ω CL=30pF tPHL tPLH tPHL tPLH tPHL tEN tDIS tPLH tPHL tPHL tPLH tEN s b O tDIS tPLH tPHL tPLH tPHL tPLH tPHL e t le (s) o s b O - t c u VERC=GND RL=12.5Ω CL=30pF VERC=GND RL=12.5Ω CL=30pF Propagation Delay Time LEAB to B VERC=GND RL=12.5Ω CL=30pF Enable Delay Time OEAB or OE to B Disable Delay Time OEAB or OE to B Propagation Delay Time B to A VERC=GND RL=12.5Ω CL=30pF t e l o tPHL 1.5 1.5 d o r P e Propagation Delay Time CK to B tPLH 160 RL=500Ω Propagation Delay Time CK to A RL=500Ω Propagation Delay Time LEBA to A RL=500Ω CL=50pF CL=50pF CL=50pF Unit c u d Typ. o r P ) s t( Max. 5.2 6.2 1.5 5.5 1.5 5.8 1.5 5.8 1.5 6.4 1.5 5.4 1.5 6.2 1.5 4.3 1.5 4.6 1.5 4.3 1.5 4.9 1.5 4.9 1.5 4.8 1.5 4.8 1.5 4.2 1.5 4.7 1.5 4.8 1.5 4 1.5 4 1.5 4 1.5 3.7 MHz ns ns ns ns ns ns ns ns ns ns ns 7/16 74GTL1655A Value Symbol Parameter Test Condition -40 to 85 °C Min. tEN Enable Delay Time OEBA or OE to A Disable Delay Time OEBA or OE to A Set-up Time tDIS tSU tH Hold Time tW Pulse duration Slew rate Slew rate B output both transition (0.6 to 1.3V) RL=500Ω R1=500ΩCL=50pF Data before clock Data before LE Ck High Ck Low Data after clock Data after LE Ck High or LOW LE High CK High or Low VERC=VCC 4.6 1 6.1 2.7 2.8 2.6 0.4 0.9 3 3 Symbol Parameter 1 1 c u d Test Condition so b O - Maximum Frequency tPLH B to A or A to B Propagation Delay Time A to B VERC=VCC RL=12.5Ω CL=30pF Propagation Delay Time CK to B VERC=VCC RL=12.5Ω CL=30pF Propagation Delay Time LEAB to B VERC=VCC RL=12.5Ω CL=30pF Enable Delay Time OEAB or OE to B Disable Delay Time OEAB or OE to B Propagation Delay Time A to B VERC=VCC RL=12.5Ω CL=30pF tPLH tPHL tPHL tEN t e l o tDIS bs tPHL tPLH tPHL tEN tDIS r P e (s) ct u d o tPLH tPLH ns 1 fMAX tPHL O ns VERC=GND e t le VERC=GND RL=12.5Ω CL=30pF Propagation Delay Time CK to B VERC=GND RL=12.5Ω CL=30pF Propagation Delay Time LEAB to B VERC=GND RL=12.5Ω CL=30pF Enable Delay Time OEAB or OE to B Disable Delay Time OEAB or OE to B VERC=GND RL=12.5Ω CL=30pF Min. ns ns 1 Table 11: AC Electrical Characteristics for GTL+ (VCC=3.3 ± 0.3V, VTT=1.5V, VREF=1.0V, VERC=VCC or GND) tPHL Max. 1 Skew between drivers (in Switching in the same direction the same package) Switching in any direction tsk tPLH Typ. Unit ns/V ) s t( ns o r P Value -40 to 85 °C Typ. Unit Max. 160 MHz 1.5 5.1 1.5 6.5 1.5 5.4 1.5 6.2 1.5 5.7 1.5 6.7 1.5 5.5 1.5 5.8 1.0 4.3 1.0 4.9 1.0 4.0 1.0 5.5 1.0 4.0 1.0 5.4 1.0 5.1 1.0 4.9 ns ns ns ns ns ns ns ns 8/16 74GTL1655A Value Symbol Parameter Test Condition tPLH Propagation Delay Time B to A RL=500Ω Propagation Delay Time CK to A RL=500Ω Propagation Delay Time LEBA to A RL=500Ω -40 to 85 °C Min. tPHL tPLH tPHL tPLH tPHL tEN Enable Delay Time OEBA or OE to A tDIS Disable Delay Time OEBA or OE to A Slew rate Slew rate B output both transition (0.6 to 1.3V) tW Pulse duration tSU Set-up Time tH CL=50pF CL=50pF CL=50pF RL=500Ω R1=500ΩCL=50pF Max. 1.5 4.8 1.5 4.7 1.5 4.4 1.5 4.1 1.5 4 1.5 3.7 1 4.2 1 6.1 VERC=VCC RL=12.5Ω CL=30pF 1 VERC=GND RL=12.5Ω CL=30pF 1 LE High CK High or Low Data before clock Data before LE Ck High Ck Low Hold Time Data after clock Data after LE Ck High or LOW Skew between drivers (in Switching in the same direction the same package) Switching in any direction tsk Typ. Unit Figure 4: Test Circuit For "A" Outputs ) s ( ct 3 3 2.7 2.8 2.6 0.4 0.9 e t le c u d o r P 1 1 o s b O - r P e t e l o Test tPLH, tPHL Switch Open tPZL, tPLZ 6V tPZH, tPHZ GND CL = 50pF or equivalent (includes jig and probe capacitance) RL = R1 = 500Ω or equivalent RT = ZOUT of pulse generator (typically 50Ω) tr=tf <=2.5ns 9/16 ns ns ns ns/V ) s t( ns ns ns u d o s b O ns ns 74GTL1655A Table 12: Test Circuit For "B" Outputs CL = 30pF or equivalent (includes jig and probe capacitance) RL = R1 = 12.5Ω or equivalent RT = ZOUT of pulse generator (typically 50Ω) c u d tr=tf <=2.5ns Figure 5: Waveform - Pulse Duration (A Port, Control Pin) e t le ) s ( ct u d o o s b O - Figure 6: Waveform - Clock To B Port Propagation Delay Time r P e t e l o s b O 10/16 o r P ) s t( 74GTL1655A Figure 7: Waveform - Clock To A Port Propagation Delay Time Figure 8: Waveform - Setup And Hold Time c u d e t le ) s ( ct ) s t( o r P o s b O - u d o r P e t e l o s b O 11/16 74GTL1655A Figure 9: Waveform - Enable And Disable Time (A Port) c u d e t le ) s ( ct u d o r P e t e l o s b O 12/16 o s b O - o r P ) s t( 74GTL1655A TSSOP64 MECHANICAL DATA mm. inch DIM. MIN. TYP MAX. A MIN. TYP. MAX. 1.1 A1 0.05 0.043 0.15 A2 0.002 0.006 0.9 0.035 b 0.17 0.27 0.0067 0.011 c 0.09 0.20 0.0035 0.0079 D 16.9 17.1 0.665 ) s t( E 0.673 8.1 E1 0.318 6.0 6.2 e 0.5 BSC 0˚ 8˚ L 0.50 0.75 ) s ( ct A2 A1 b o r P e du e o r P 0.244 0.0197 BSC K A c u d 0.236 e t le 0˚ o s b O - 0.020 K 8˚ 0.030 L E c D t e l o s b O E1 PIN 1 IDENTIFICATION 1 7187824A 13/16 74GTL1655A Tape & Reel TSSOP64 MECHANICAL DATA mm. inch DIM. MIN. TYP A MAX. MIN. TYP. 330 13.2 12.992 C 12.8 D 20.2 0.795 N 60 2.362 T 0.504 0.519 30.4 1.197 Ao 8.7 8.9 0.342 0.350 Bo 17.2 17.4 0.677 Ko 1.4 1.6 0.055 Po 3.9 4.1 0.153 ) s t( P 11.9 12.1 0.468 0.685 ) s ( ct u d o r P e t e l o s b O o s b O - c u d ro P e let 14/16 MAX. 0.063 0.161 0.476 74GTL1655A Table 13: Revision History Date Revision 18-Oct-2004 1 Description of Changes First Release. c u d e t le ) s ( ct ) s t( o r P o s b O - u d o r P e t e l o s b O 15/16 74GTL1655A c u d e t le ) s ( ct ) s t( o r P o s b O - u d o r P e t e l o Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. 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