STMICROELECTRONICS 74LCX540TTR

74LCX540
LOW VOLTAGE CMOS OCTAL BUS BUFFER (3-STATE)
WITH 5V TOLERANT INPUTS AND OUTPUTS
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5V TOLERANT INPUTS AND OUTPUTS
HIGH SPEED:
tPD = 8.0 ns (MAX.) at VCC = 3V
POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 24mA (MIN) at VCC = 3V
PCI BUS LEVELS GUARANTEED AT 24 mA
BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
OPERATING VOLTAGE RANGE:
VCC(OPR) = 2.0V to 3.6V (1.5V Data
Retention)
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 540
LATCH-UP PERFORMANCE EXCEEDS
500mA (JESD 17)
ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
DESCRIPTION
The 74LCX540 is a low voltage CMOS OCTAL
BUS BUFFER (INVERTED) fabricated with
sub-micron silicon gate and double-layer metal
wiring C2MOS technology. It is ideal for low power
and high speed 3.3V applications; it can be
interfaced to 5V signal environment for both inputs
and outputs.
Figure 1: Pin Connection And IEC Logic Symbols
September 2004
SOP
TSSOP
Table 1: Order Codes
PACKAGE
T&R
SOP
TSSOP
74LCX540MTR
74LCX540TTR
The 3 STATE control gate operates as two input
AND such that if either G1 and G2 are high, all
eight outputs are in the high impedance state. In
order to enhance PC board layout the 74LCX540
offers a pinout having inputs and outputs on
opposite sides of the package.
It has same speed performance at 3.3V than 5V
AC/ACT family, combined with a lower power
consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
Rev. 3
1/12
74LCX540
Figure 2: Input And Output Equivalent Circuit
Table 2: Pin Description
Table 3: Truth Table
PIN N°
SYMBOL
1, 19
2, 3, 4, 5, 6,
7, 8, 9
18, 17, 16,
15, 14, 13,
12, 11
10
20
G1, G2
A1 to A8
Output Enable Inputs
Data Inputs
Y1 to Y8
Data Outputs
GND
VCC
NAME AND FUNCTION
Ground (0V)
Positive Supply Voltage
INPUT
OUTPUT
G1
G2
An
Yn
H
X
L
L
X
H
L
L
X
X
H
L
Z
Z
L
H
X : Don’t Care
Z : High Impedance
Table 4: Absolute Maximum Ratings
Symbol
VCC
Parameter
Value
Unit
Supply Voltage
-0.5 to +7.0
V
VI
DC Input Voltage
-0.5 to +7.0
V
VO
DC Output Voltage (OFF State)
-0.5 to +7.0
V
VO
DC Output Voltage (High or Low State) (note 1)
-0.5 to VCC + 0.5
V
IIK
DC Input Diode Current
- 50
mA
IOK
DC Output Diode Current (note 2)
- 50
mA
IO
DC Output Current
± 50
mA
ICC
DC Supply Current per Supply Pin
± 100
mA
IGND
DC Ground Current per Supply Pin
Tstg
Storage Temperature
TL
Lead Temperature (10 sec)
± 100
mA
-65 to +150
°C
300
°C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
1) IO absolute maximum rating must be observed
2) VO < GND
2/12
74LCX540
Table 5: Recommended Operating Conditions
Symbol
VCC
Parameter
Supply Voltage (note 1)
Value
Unit
2.0 to 3.6
V
VI
Input Voltage
0 to 5.5
V
VO
Output Voltage (OFF State)
0 to 5.5
V
VO
Output Voltage (High or Low State)
0 to VCC
V
± 24
mA
IOH, IOL
High or Low Level Output Current (VCC = 3.0 to 3.6V)
IOH, IOL
High or Low Level Output Current (VCC = 2.7V)
Top
dt/dv
Operating Temperature
Input Rise and Fall Time (note 2)
± 12
mA
-55 to 125
°C
0 to 10
ns/V
1) Truth Table guaranteed: 1.5V to 3.6V
2) VIN from 0.8V to 2V at VCC = 3.0V
Table 6: DC Specifications
Test Condition
Symbol
VIH
VIL
VOH
Parameter
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
Low Level Output
Voltage
Ioff
IOZ
ICC
∆ICC
Input Leakage
Current
Power Off Leakage
Current
High Impedance
Output Leakage
Current
Quiescent Supply
Current
ICC incr. per Input
Min.
Max.
2.0
-55 to 125 °C
Min.
Unit
Max.
2.0
V
2.7 to 3.6
0.8
0.8
2.7 to 3.6
IO=-100 µA
VCC-0.2
VCC-0.2
2.7
IO=-12 mA
2.2
2.2
IO=-18 mA
2.4
2.4
IO=-24 mA
2.2
2.7 to 3.6
V
V
2.2
IO=100 µA
0.2
0.2
IO=12 mA
0.4
0.4
IO=16 mA
0.4
0.4
IO=24 mA
0.55
0.55
2.7 to 3.6
VI = 0 to 5.5V
±5
±5
µA
0
VI or VO = 5.5V
10
10
µA
2.7 to 3.6
VI = VIH or VIL
VO = 0 to VCC
±5
±5
µA
2.7
3.0
II
-40 to 85 °C
VCC
(V)
3.0
VOL
Value
2.7 to 3.6
VI = VCC or GND
VI or VO= 3.6 to 5.5V
VIH = VCC - 0.6V
2.7 to 3.6
10
10
± 10
± 10
500
500
V
µA
µA
3/12
74LCX540
Table 7: Dynamic Switching Characteristics
Test Condition
Symbol
VOLP
VOLV
Parameter
Value
TA = 25 °C
VCC
(V)
Dynamic Low Level Quiet
Output (note 1)
Min.
Typ.
Max.
0.8
CL = 50pF
VIL = 0V, VIH = 3.3V
3.3
Unit
V
-0.8
1) Number of outputs defined as "n". Measured with "n-1" outputs switching from HIGH to LOW or LOW to HIGH. The remaining output is
measured in the LOW state.
Table 8: AC Electrical Characteristics
Test Condition
Symbol
Parameter
tPLH tPHL
Propagation Delay
Time
tPZL tPZH
Output Enable Time
tPLZ tPHZ
Output Disable Time
tOSLH
tOSHL
Output To Output
Skew Time (note1,
2)
VCC
(V)
2.7
3.0 to 3.6
2.7
3.0 to 3.6
2.7
3.0 to 3.6
3.0 to 3.6
Value
CL
(pF)
RL
(Ω)
ts = tr
(ns)
50
500
2.5
50
500
2.5
50
500
2.5
50
500
2.5
-40 to 85 °C
-55 to 125 °C
Min.
Max.
Min.
Max.
1.5
1.5
1.5
1.5
1.5
1.5
9.0
8.0
9.5
8.5
8.5
7.5
1.0
1.5
1.5
1.5
1.5
1.5
1.5
9.0
8.0
9.5
8.5
8.5
7.5
1.0
Unit
ns
ns
ns
ns
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switching in the same direction, either HIGH or LOW (tOSLH = | tPLHm - tPLHn|, tOSHL = | tPHLm - tPHLn|)
2) Parameter guaranteed by design
Table 9: Capacitive Characteristics
Test Condition
Symbol
CIN
COUT
CPD
Parameter
Value
TA = 25 °C
VCC
(V)
Min.
Typ.
Unit
Max.
Input Capacitance
3.3
VIN = 0 to VCC
6
pF
Output Capacitance
3.3
VIN = 0 to VCC
12
pF
Power Dissipation Capacitance
(note 1)
3.3
fIN = 10MHz
VIN = 0 or VCC
25
pF
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/8 (per buffer)
4/12
74LCX540
Figure 3: Test Circuit
TEST
SWITCH
tPLH, tPHL
Open
tPZL, tPLZ
6V
tPZH, tPHZ
GND
CL = 50 pF or equivalent (includes jig and probe capacitance)
RL = R1 = 500Ω or equivalent
RT = ZOUT of pulse generator (typically 50Ω)
Figure 4: Waveform - Propagation Delays (f=1MHz; 50% duty cycle)
5/12
74LCX540
Figure 5: Waveform - Output Enable And Disable Time (f=1MHz; 50% duty cycle)
6/12
74LCX540
SO-20 MECHANICAL DATA
DIM.
mm.
MIN.
TYP
inch
MAX.
MIN.
TYP.
MAX.
A
2.35
2.65
0.093
0.104
A1
0.1
0.30
0.004
0.012
B
0.33
0.51
0.013
0.020
C
0.23
0.32
0.009
0.013
D
12.60
13.00
0.496
0.512
E
7.4
7.6
0.291
0.299
e
1.27
0.050
H
10.00
10.65
0.394
0.419
h
0.25
0.75
0.010
0.030
L
0.4
1.27
0.016
0.050
k
0°
8°
0°
8°
ddd
0.100
0.004
0016022D
7/12
74LCX540
TSSOP20 MECHANICAL DATA
mm.
inch
DIM.
MIN.
TYP
MAX.
A
MIN.
TYP.
MAX.
1.2
A1
0.05
A2
0.8
b
0.047
0.15
0.002
0.004
0.006
1.05
0.031
0.039
0.041
0.19
0.30
0.007
0.012
c
0.09
0.20
0.004
0.0079
D
6.4
6.5
6.6
0.252
0.256
0.260
E
6.2
6.4
6.6
0.244
0.252
0.260
E1
4.3
4.4
4.48
0.169
0.173
0.176
1
e
0.65 BSC
K
0˚
L
0.45
A
0.0256 BSC
0.60
8˚
0˚
0.75
0.018
8˚
0.024
0.030
A2
A1
b
K
e
L
E
c
D
E1
PIN 1 IDENTIFICATION
1
0087225C
8/12
74LCX540
Tape & Reel SO-20 MECHANICAL DATA
mm.
inch
DIM.
MIN.
A
TYP
MAX.
MIN.
330
MAX.
12.992
C
12.8
D
20.2
0.795
N
60
2.362
T
13.2
TYP.
0.504
30.4
0.519
1.197
Ao
10.8
11
0.425
0.433
Bo
13.2
13.4
0.520
0.528
Ko
3.1
3.3
0.122
0.130
Po
3.9
4.1
0.153
0.161
P
11.9
12.1
0.468
0.476
9/12
74LCX540
Tape & Reel TSSOP20 MECHANICAL DATA
mm.
inch
DIM.
MIN.
A
MAX.
MIN.
330
13.2
TYP.
MAX.
12.992
C
12.8
D
20.2
0.795
N
60
2.362
T
10/12
TYP
0.504
22.4
0.519
0.882
Ao
6.8
7
0.268
0.276
Bo
6.9
7.1
0.272
0.280
Ko
1.7
1.9
0.067
0.075
Po
3.9
4.1
0.153
0.161
P
11.9
12.1
0.468
0.476
74LCX540
Table 10: Revision History
Date
Revision
15-Sep-2004
3
Description of Changes
Ordering Codes Revision - pag. 1.
11/12
74LCX540
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