74LVC573A OCTAL D-TYPE LATCH HIGH PERFORMANCE ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 5V TOLERANT INPUTS HIGH SPEED: tPD = 6.8ns (MAX.) at VCC = 3V POWER DOWN PROTECTION ON INPUTS AND OUTPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24mA (MIN) at VCC = 3V PCI BUS LEVELS GUARANTEED AT 24 mA BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC(OPR) = 1.65V to 3.6V (1.2V Data Retention) PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 573 LATCH-UP PERFORMANCE EXCEEDS 500mA (JESD 17) ESD PERFORMANCE: HBM > 2000V (MIL STD 883 method 3015); MM > 200V DESCRIPTION The 74LVC573A is a low voltage CMOS OCTAL D-TYPE LATCH fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for 1.65 to 3.6 VCC operations and low power and low noise applications. These 8 bit D-Type latch are controlled by a latch enable input (LE) and an output enable input (OE). While the LE inputs is held at a high level, the Q Figure 1: Pin Connection And IEC Logic Symbols July 2004 SOP TSSOP Table 1: Order Codes PACKAGE T&R SOP TSSOP 74LVC573AMTR 74LVC573ATTR outputs will follow the data input precisely or inversely. When the LE is taken low, the Q outputs will be latched precisely or inversely at the logic level of D input data. While the (OE) input is low, the 8 outputs will be in a normal logic state (high or low logic level) and while high level the outputs will be in a high impedance state. This device is designed to interface directly High Speed CMOS systems with TTL and NMOS components. It has more speed performance at 3.3V than 5V AC/ACT family, combined with a lower power consumption. All inputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. Rev. 3 1/13 74LVC573A Figure 2: Input And Output Equivalent Circuit Table 2: Pin Description Table 3: Truth Table PIN N° SYMBOL 1 OE 2, 3, 4, 5, 6, 7, 8, 9 12, 13, 14, 15, 16, 17, 18, 19 11 10 20 D0 to D7 3 State Output Enable Input (Active LOW) Data Inputs NAME AND FUNCTION Q0 to Q7 3-State Latch Outputs LE GND VCC Latch Enable Input Ground (0V) Positive Supply Voltage INPUTS OUTPUT OE LE D Q H X X L L X L L H H L H Z NO CHANGE L H X : Don’t Care Z : High Impedance Table 4: Absolute Maximum Ratings Symbol Value Unit Supply Voltage -0.5 to +7.0 V VI DC Input Voltage -0.5 to +7.0 V VO DC Output Voltage (VCC = 0V) VO DC Output Voltage (High or Low State) (note 1) VCC Parameter IIK DC Input Diode Current IOK DC Output Diode Current (note 2) IO DC Output Current ICC or IGND DC VCC or Ground Current per Supply Pin Storage Temperature Tstg TL Lead Temperature (10 sec) -0.5 to +7.0 V -0.5 to VCC + 0.5 - 50 V mA - 50 mA ± 50 mA ± 100 mA -65 to +150 °C 300 °C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied 1) IO absolute maximum rating must be observed 2) VO < GND 2/13 74LVC573A Table 5: Recommended Operating Conditions Symbol VCC Parameter Supply Voltage (note 1) Value Unit 1.65 to 3.6 V VI Input Voltage 0 to 5.5 V VO Output Voltage (VCC = 0V) 0 to 5.5 V VO Output Voltage (High or Low State) 0 to VCC V IOH, IOL High or Low Level Output Current (VCC = 3.0 to 3.6V) ± 24 mA IOH, IOL High or Low Level Output Current (VCC = 2.7 to 3.0V) ± 12 mA IOH, IOL High or Low Level Output Current (VCC = 2.3 to 2.7V) ±8 mA IOH, IOL High or Low Level Output Current (VCC = 1.65 to 2.3V) Top dt/dv Operating Temperature Input Rise and Fall Time (note 2) ±4 mA -55 to 125 °C 0 to 10 ns/V 1) Truth Table guaranteed: 1.2V to 3.6V 2) VIN from 0.8V to 2V at VCC = 3.0V Table 6: DC Specifications Test Condition Symbol VIH VIL VOH VOL II Ioff IOZ ICC ∆ICC Parameter Value -40 to 85 °C -55 to 125 °C VCC (V) Min. High Level Input Voltage 1.65 to 1.95 0.65VCC 0.65VCC 2.3 to 2.7 2.7 to 3.6 1.7 2 1.7 2 Low Level Input Voltage 1.65 to 1.95 0.35VCC 0.35VCC 2.3 to 2.7 2.7 to 3.6 0.7 0.8 0.7 0.8 High Level Output Voltage 1.65 to 3.6 IO=-100 µA VCC-0.2 VCC-0.2 1.65 IO=-4 mA 1.2 1.2 2.3 IO=-8 mA 1.7 1.7 2.7 IO=-12 mA 2.2 2.2 3.0 IO=-18 mA 2.4 2.4 2.2 Low Level Output Voltage Input Leakage Current Power Off Leakage Current High Impedance Output Leakage Current Quiescent Supply Current ICC incr. per Input Max. Min. Unit Max. V V V 3.0 IO=-24 mA 1.65 to 3.6 IO=100 µA 0.2 0.2 1.65 IO=4 mA 0.45 0.45 2.3 IO=8 mA 0.7 0.7 2.2 V 2.7 IO=12 mA 0.4 0.4 3.0 IO=24 mA 0.55 0.55 3.6 VI = 0 to 5.5V ±5 ±5 µA 0 VI or VO = 5.5V 10 10 µA 3.6 VI = VIH or VIL VO = 0 to 5.5V ±5 ±5 µA VI = VCC or GND 10 10 VI or VO = 3.6 to 5.5V VIH = VCC-0.6V ± 10 ± 10 500 500 3.6 2.7 to 3.6 µA µA 3/13 74LVC573A Table 7: Dynamic Switching Characteristics Test Condition Symbol VOLP VOLV Parameter Value TA = 25 °C VCC (V) Dynamic Low Level Quiet Output (note 1) Min. Typ. Max. 0.8 CL = 50pF VIL = 0V, VIH = 3.3V 3.3 Unit V -0.8 1) Number of output defined as "n". Measured with "n-1" outputs switching from HIGH to LOW or LOW to HIGH. The remaining output is measured in the LOW state. Table 8: AC Electrical Characteristics Test Condition Symbol tPLH tPHL tPLH tPHL tPZL tPZH tPLZ tPHZ tW ts th tOSLH tOSHL Parameter Propagation Delay Time D to Q Propagation Delay Time LE to Q Output Enable Time Output Disable Time LE Pulse Width HIGH Setup Time D to LE, (HIGH to LOW) Hold Time LE (HIGH to LOW) to D Output To Output Skew Time (note1, 2) Value VCC (V) CL (pF) RL (Ω) ts = t r (ns) 1.65 to 1.95 2.3 to 2.7 2.7 3.0 to 3.6 1.65 to 1.95 2.3 to 2.7 2.7 3.0 to 3.6 1.65 to 1.95 2.3 to 2.7 2.7 3.0 to 3.6 1.65 to 1.95 2.3 to 2.7 2.7 3.0 to 3.6 1.65 to 1.95 2.3 to 2.7 2.7 3.0 to 3.6 1.65 to 1.95 2.3 to 2.7 2.7 3.0 to 3.6 1.65 to 1.95 2.3 to 2.7 2.7 3.0 to 3.6 2.7 to 3.6 30 30 50 50 30 30 50 50 30 30 50 50 30 30 50 50 30 30 50 50 30 30 50 50 30 30 50 50 1000 500 500 500 1000 500 500 500 1000 500 500 500 1000 500 500 500 1000 500 500 500 1000 500 500 500 1000 500 500 500 2.0 2.0 2.5 2.5 2.0 2.0 2.5 2.5 2.0 2.0 2.5 2.5 2.0 2.0 2.5 2.5 2.0 2.0 2.5 2.5 2.0 2.0 2.5 2.5 2.0 2.0 2.5 2.5 -40 to 85 °C Min. 1.5 1 1.5 1 1 1 2 2 TBD TBD 3.3 3.3 TBD TBD 2 2 TBD TBD 1.5 1.5 Max. TBD TBD 7.8 6.8 TBD TBD 7.8 6.8 TBD TBD 8.7 7.7 TBD TBD 7.6 7.0 1 -55 to 125 °C Min. 1.5 1 1.5 1 1 1 2 2 TBD TBD 3.3 3.3 TDB TBD 2 2 TBD TBD 1.5 1.5 Unit Max. TBD TBD 9.4 8.2 TBD TBD 9.4 8.2 TBD TBD 10.4 9.2 TBD TBD 9.1 8.4 ns ns ns ns ns ns ns 1 ns 1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switching in the same direction, either HIGH or LOW (tOSLH = | tPLHm - tPLHn|, tOSHL = | tPHLm - tPHLn| 2) Parameter guaranteed by design 4/13 74LVC573A Table 9: Capacitive Characteristics Test Condition Symbol Parameter CIN Input Capacitance CPD Power Dissipation Capacitance (note 1) Value TA = 25 °C VCC (V) Min. 1.8 2.5 3.3 fIN = 10MHz Typ. Unit Max. 4 pF 28 30 34 pF 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/n (per circuit) Figure 3: Test Circuit RT = ZOUT of pulse generator (typically 50Ω) Table 10: Test Circuit And Waveform Symbol Value VCC Symbol CL 1.65 to 1.95V 2.3 to 2.7V 2.7V 3.0 to 3.6V 30pF 30pF 50pF 50pF RL = R1 1000Ω 500Ω 500Ω 500Ω VS 2 x VCC 2 x VCC 6V 7V VIH VCC VCC 2.7V 3.0V VM VCC/2 VCC/2 1.5V 1.5V VOH VCC VCC 3.0V 3.5V VX VOL + 0.15V VOL + 0.15V VOL + 0.3V VOL + 0.3V VY VOH - 0.15V VOH - 0.15V VOH - 0.3V VOH - 0.3V tr = tr <2.0ns <2.0ns <2.5ns <2.5ns 5/13 74LVC573A Figure 4: Waveform - Propagation Delay, Setup And Hold Times (f=1MHz; 50% duty cycle) Figure 5: Waveform - Output Enable And Disable Times (f=1MHz; 50% duty cycle) 6/13 74LVC573A Figure 6: Waveform - Propagation Delay Time (f=1MHz; 50% duty cycle) 7/13 74LVC573A SO-20 MECHANICAL DATA DIM. mm. MIN. TYP inch MAX. MIN. TYP. MAX. A 2.35 2.65 0.093 0.104 A1 0.1 0.30 0.004 0.012 B 0.33 0.51 0.013 0.020 C 0.23 0.32 0.009 0.013 D 12.60 13.00 0.496 0.512 E 7.4 7.6 0.291 0.299 e 1.27 0.050 H 10.00 10.65 0.394 0.419 h 0.25 0.75 0.010 0.030 L 0.4 1.27 0.016 0.050 k 0° 8° 0° 8° ddd 0.100 0.004 0016022D 8/13 74LVC573A TSSOP20 MECHANICAL DATA mm. inch DIM. MIN. TYP MAX. A MIN. TYP. MAX. 1.2 A1 0.05 A2 0.8 b 0.047 0.15 0.002 0.004 0.006 1.05 0.031 0.039 0.041 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.0079 D 6.4 6.5 6.6 0.252 0.256 0.260 E 6.2 6.4 6.6 0.244 0.252 0.260 E1 4.3 4.4 4.48 0.169 0.173 0.176 1 e 0.65 BSC K 0˚ L 0.45 A 0.0256 BSC 0.60 8˚ 0˚ 0.75 0.018 8˚ 0.024 0.030 A2 A1 b K e L E c D E1 PIN 1 IDENTIFICATION 1 0087225C 9/13 74LVC573A Tape & Reel SO-20 MECHANICAL DATA mm. inch DIM. MIN. A MAX. MIN. 330 13.2 TYP. MAX. 12.992 C 12.8 D 20.2 0.795 N 60 2.362 T 10/13 TYP 0.504 30.4 0.519 1.197 Ao 10.8 11 0.425 0.433 Bo 13.2 13.4 0.520 0.528 Ko 3.1 3.3 0.122 0.130 Po 3.9 4.1 0.153 0.161 P 11.9 12.1 0.468 0.476 74LVC573A Tape & Reel TSSOP20 MECHANICAL DATA mm. inch DIM. MIN. A TYP MAX. MIN. 330 MAX. 12.992 C 12.8 D 20.2 0.795 N 60 2.362 T 13.2 TYP. 0.504 22.4 0.519 0.882 Ao 6.8 7 0.268 0.276 Bo 6.9 7.1 0.272 0.280 Ko 1.7 1.9 0.067 0.075 Po 3.9 4.1 0.153 0.161 P 11.9 12.1 0.468 0.476 11/13 74LVC573A Table 11: Revision History Date Revision 26-Jul-2004 3 12/13 Description of Changes Ordering Codes Revision - pag. 1. 74LVC573A Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. 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