EMIF02-USB03F2 2-line IPAD™, EMI filter including ESD protection Features ■ 2-line low-pass-filter + 2-line ESD protection ■ High efficiency in EMI filtering ■ Lead-free package ■ Very low PCB space occupation: < 3.25 mm2 ■ Very thin package: 0.65 mm ■ High efficiency in ESD suppression (IEC61000-4-2 level 4) ■ High reliability offered by monolithic integration ■ High reduction of parasitic elements through ■ integration and wafer level packaging Flip Chip (11 bumps) Figure 1. Pin layout (bump side) 3 2 1 ID Dz Vbus Pup Pd1 B D+ out Pd2 D+ in C Dout GND Din D A Complies with the following standards ■ ■ IEC 61000-4-2 level 4 on external pins: – 15 kV (air discharge) – 8 kV (contact discharge) IEC 61000-4-2 level 1 on internal pins: – 2 kV (air discharge) – 2 kV (contact discharge) Figure 2. Application Schematic Pup Dz ID Vbus EMIF02-USB03F2 R3=1.3kΩ ESD protection and EMI filtering for: ■ USB OTG port D+OUT R2=33Ω D+IN D-OUT R1=33Ω D-IN C C R5=15kΩ Description R4=17kΩ Pd2 Pd1 The EMIF02-USB03F2 is a highly integrated array designed to suppress EMI / RFI noise for USB OTG (on-the-go). Cline = 20 pF max. The EMIF02-USB03F2 Flip Chip packaging means the package size is equal to the die size. Additionally, this filter includes ESD protection circuitry which prevents damage to the protected device when subjected to ESD surges up to 15 kV on external contacts. TM: IPAD is a trademark of STMicroelectronics. April 2008 Rev 4 1/8 www.st.com 8 Characteristics 1 EMIF02-USB03F2 Characteristics Table 1. Absolute ratings (Tamb = 25 °C) Symbol VPP Tj Parameter and test conditions Unit Internal pins (D3, C3, C2, B2, B1): ESD discharge IEC61000-4-2, air discharge ESD discharge IEC61000-4-2, contact discharge External pins (D1, C1, A2, A3, B3): ESD discharge IEC61000-4-2, air discharge ESD discharge IEC61000-4-2, contact discharge 15 8 Maximum junction temperature 125 °C 2 2 kV Top Operating temperature range -40 to +85 °C Tstg Storage temperature range -55 to 150 °C Table 2. Electrical characteristics (Tamb = 25 °C) Symbol Parameters VBR Breakdown voltage IRM Leakage current @ VRM VRM Stand-off voltage VCL Clamping voltage Rd Dynamic impedance IPP Peak pulse current Cline Input capacitance per line Symbol 2/8 Value Test conditions VBR IR = 1 mA IRM VRM = 3 V Cline @0V Min Typ Max 14 Unit V 0.1 0.5 µA 20 pF R1, R2 Tolerance ± 5 % 33 Ω R3 Tolerance ± 5 % 1.30 kΩ R4 Tolerance ± 5 % 17 kΩ R5 Tolerance ± 5 % 15 kΩ EMIF02-USB03F2 Figure 3. Characteristics Filtering measurement Figure 4. EMIF02-USB03F2_EVAL-SAMPLES_PM431 Aplac 7.70 User: ST Microelectronics Jul 22 2004 Analog crosstalk measurement EMIF02-USB03F2_EVAL-SAMPLES_PM431 Aplac 7.70 User: ST Microelectronics Jul 22 2004 0.00 0.00 dB -10.00 dB -20.00 -10.00 -30.00 -40.00 -20.00 -50.00 -30.00 -60.00 -70.00 -40.00 -80.00 -90.00 -50.00 -100.00 100.0k 1.0M 10.0M 100.0M 1.0G 100.0k f/Hz D1/D3 Line C1/C3 Line 1.0M 10.0M Figure 6. 100.0M f/Hz C1/D3 Line 1.0G A2/A3 Line Figure 5. ESD response to IEC 61000-4-2 (+15 kV air discharge) on one input V(in) and on one output V(out) ESD response to IEC 61000-4-2 (-15 kV air discharge) on one input V(in) and on one output V(out) Figure 7. Junction capacitance versus reverse voltage applied (typical values) C(pF) 20 18 16 14 12 10 8 6 4 2 V R (V) 0 0 1 2 3 4 5 6 7 8 9 10 11 12 3/8 Application information Application information Figure 8. Application schematic Vbus 3.3V Vbus ID ID USB OTG Xceiver Pup Dz ID Vbus EMIF02-USB03F2 R3=1.3kΩ D+ D+OUT R2=33Ω D+IN D-OUT R1=33Ω D-IN D+ D- C D- C R5=15kΩ R4=17kΩ GND USB OTG connector 2 EMIF02-USB03F2 GND Pd2 Pd1 R1 = R2 = 33 Ω Cline = 20 pF max. Figure 9. Aplac model C1 C3 Ls Rs Lbump Rbump Rbump Lbump Rs Ls Port2 Port1 50 50 A3 A2 B3 B2 B1 D2 C2 MODEL = D02_usb03_gnd MODEL = D02_usb03 bulk bulk bulk bulk bulk bulk bulk B2 B1 R_17k R_1k3 C3 C2 R_33R C1 D2 R_15k D3 R_33R Lbump D1 Rbump MODEL = D02_usb03 MODEL = D02_usb03 Cgnd Lgnd bulk Cbump Rsubump A2 B1 Cbump Rsubump bulk Cbump Rsubump bulk D3 bulk Cbump Rsubump bulk D1 Cbump Rsubump B3 bulk C1 Cbump Rsubump C3 bulk Cbump Rsubump Cbump Rsubump C2 Rgnd Cbump Rsubump bulk B2 bulk bulk bulk bulk Cbump Rsubump bulk A3 bulk Figure 10. Aplac parameters Ls 950pH Rs 150m R_33R 33 R_1k3 1.3k R_15k 15k R_17k 17k Cz_usb03 11pF Rs_usb03 1 Cz_usb03_gnd 220pF 4/8 Rs_usb03_gnd 0.9 Lgnd 50pH Rgnd 100m Cgnd 0.15pF Lbump 50pH Rbump 20m Cbump 2.4pF Rsubump 100m EMIF02-USB03F2 3 Ordering information scheme Ordering information scheme Figure 11. Ordering information scheme EMIF yy - xxx zz Fx EMI Filter Number of lines Information x = resistance value (Ohms) z = capacitance value / 10(pF) or 3 letters = application 2 digits = version Package F = Flip chip x = 2: lead free, pitch = 500 µm, bump = 315 µm Package information In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at www.st.com. Figure 12. Package dimensions 500 µm ± 50 315 µm ± 50 650 µm ± 65 2.07 mm ± 50 µm 500 µm ± 50 285 µm 1.57 mm ± 50 µm 285 µm 4 5/8 Ordering information EMIF02-USB03F2 Figure 13. Footprint Figure 14. Marking Dot, ST logo xx = marking z = manufacturing location yww = datecode (y = year ww = week) Copper pad Diameter: 250 µm recommended, 300 µm max. E Solder stencil opening: 330 µm recommended x x z y ww Solder mask opening recommendation: 340 µm min. for 300 µm copper pad diameter Figure 15. Flip Chip tape and reel specification Dot identifying Pin A1 location 3.5 ± 0.1 2.17 ST E xxz yww 4 ± 0.1 User direction of unreeling All dimensions in mm Note: 1.67 ST E xxz yww ST E xxz yww 8 ± 0.3 0.73 ± 0.05 1.75 ± 0.1 Ø 1.5 ± 0.1 4 ± 0.1 More information is available in the application notes: AN1235:"Flip Chip: Package description and recommendations for use" AN1751: “EMI filters: Recommendations and measurements” 5 Ordering information Table 3. 6/8 Ordering information Order code Marking Package Weight Base qty Delivery mode EMIF02-USB03F2 FU Flip Chip 4.5 mg 5000 Tape and reel 7” EMIF02-USB03F2 6 Revision history Revision history Table 4. Document revision history Date Revision Changes 14-Oct-2004 1 Initial release. 25-Oct-2004 2 Figure 14.: Flip Chip marking dimensions updated. 27-Oct-2004 3 Minor layout update. No content change. 28-Apr-2008 4 Updated ECOPACK statement. Updated Figure 11, Figure 12, Figure 13, Figure 14 and Figure 15. Reformatted to current standards. 7/8 EMIF02-USB03F2 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. 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