STMICROELECTRONICS EMIF06

EMIF06-10006F2
IPAD™
6 line EMI filter and ESD protection
Main product characteristics
Where EMI filtering in ESD sensitive equipment is
required:
■
Mobile phones and communication systems
■
Computers, printers and MCU Boards
®
Description
Flip-Chip
(15 Bumps)
The EMIF06-10006F2 is a highly integrated
device designed to suppress EMI/RFI noise in all
systems subjected to electromagnetic
interference. The EMIF06 Flip-Chip packaging
means the package size is equal to the die size.
This filter includes an ESD protection circuitry
which prevents damage to the application when
subjected to ESD surges up 15 kV. This device
includes 6 EMIF filters.
Benefits
■
EMI symmetrical (I/O) low-pass filter
■
High efficiency in EMI filtering
■
Lead free package
■
Very low PCB space consumption
2.92 mm x 1.29 mm
■
Very thin package: 0.65 mm
■
High efficiency in ESD suppression
(IEC 61000-4-2 level 4)
■
High reliability offered by monolithic integration
■
High reduction of parasitic elements through
integration and wafer level packaging
Order code
Part Number
Marking
EMIF06-10006F2
FT
Figure 1.
9
Pin configuration (bump side)
8
I6
7
6
I5
I4
Gnd
O6
O5
5
4
3
I3
I2
Gnd
O4
2
1
I1
Gnd
O3
O2
A
B
O1
C
Complies with the following standards:
IEC 61000-4-2 level 4:
15 kV (air discharge)
8 kV (contact discharge)
MIL STD 883E - Method 3015-6 Class 3: 30 kV
TM: IPAD is a trademeark of STMicroelectronics
November 2006
Rev 4
1/9
www.st.com
9
Characteristics
1
EMIF06-10006F2
Characteristics
Figure 2.
Basic cell configuration
100 Ω
Input 1
100 Ω
Output 1
30 pF
Input 4
30 pF
Output 4
30 pF
100 Ω
100 Ω
Input 2
Output 2
30 pF
Input 5
Output 5
30 pF
30 pF
100 Ω
Input 3
Table 1.
Symbol
Input 6
30 pF
Output 6
30 pF
30 pF
Absolute Ratings (limiting values)
Parameter and test conditions
Value
Unit
PR
DC power per resistance
0.1
W
PT
Total DC power per package
0.6
W
Tj
Maximum junction temperature
125
°C
- 40 to + 85
°C
125
°C
Top
Operating temperature range
Tstg
Storage temperature range
Table 2.
Electrical Characteristics (Tamb = 25 °C)
Symbol
Parameter
VBR
Breakdown voltage
IRM
Leakage current @ VRM
VRM
Stand-off voltage
VCL
Clamping voltage
Rd
Dynamic impedance
IPP
Peak pulse current
RI/O
Series resistance between Input and output
Cline
Capacitance per line
Symbol
2/9
30 pF
100 Ω
Output 3
30 pF
30 pF
I
IF
VF
VCL VBR VRM
Test conditions
V
IRM
IR
IPP
Min.
Typ.
Max.
Unit
5.5
7
9
V
500
nA
VBR
IR = 1 mA
IRM
VRM = 3.3 V per line
RI/O
I = 10 mA
80
100
120
Ω
Cline
VR = 2.5 V, F = 1 MHz, 30 mV (on filter cells)
50
60
70
pF
EMIF06-10006F2
Figure 3.
Characteristics
S21 (db) attenuation measurements Figure 4.
and Aplac simulation
Analog crosstalk measurements
Aplac 7.62 User: ST Microelectronics
0.00
00
dB
dB
-12.50
-25
i3_o2.s2p
-25.00
-50
-37.50
-75
Measurement
Simulation
f/Hz
-50.00
100.0k
1.0M
10.0M
100.0M
1.0G
f/Hz
-100
100k
10M
1M
100M
1G
Figure 5.
Digital crosstalk measurements
Figure 6.
ESD response to IEC 61000-4-2
(+15 kV air discharge) on one imput
(Vin) and one output (Vout)
Figure 7.
ESD response to IEC 61000-4-2
(–15 kV air discharge) on one imput
(Vin) and one output (Vout)
Figure 8.
Line capacitance versus applied
voltage for filter
C(pF)
100
90
F=1MHz
Vosc=30mVRMS
Tj=25°C
80
70
60
50
40
30
20
10
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
VR(V)
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Characteristics
EMIF06-10006F2
Figure 9.
Aplac model
Rbump
Lbump
Rs=100
Lbump
Rbump
Ii*
Oi*
sub
[email protected]
Cbump
Rsub
Rsub
Cbump
[email protected]
Rsub
Rbump
sub
Oi * = Output of each filter cell
Ii* = Input of each filter cell
Lbump
Cgnd
Lgnd
Rgnd
EMIF06-10006F2 model
Ground return for each GND bump
Figure 10. Figure 10: Aplac parameters
4/9
aplacvar RS
100Ω
aplacvar Cz
41 pF
aplacvar Lbump
50 pH
aplacvar Rbump
20 m
aplacvar Cbump
1.2 pF
aplacvar Rsub
100 m
aplacvar Rgnd
100 m
aplacvar Lgnd
100 pH
aplacvar Cgnd
0.15 pF
EMIF06-10006F2
2
Ordering Information Scheme
Ordering Information Scheme
EMIF
yy
-
xxx zz
Fx
EMI Filter
Number of lines
Information
x = resistance value (Ohms)
z = capacitance value / 10(pF)
or
3 letters = application
2 digits = version
Package
F = Flip-Chip
x = 2: Lead free Pitch = 500 µm, Bump = 315 µm
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Package information
3
EMIF06-10006F2
Package information
Figure 11. Flip-Chip Package dimensions
650 µm ± 65
50
1µ
m
±5
0
250 µm ± 50
1.29 mm ± 50 µm
500 µm ± 50
435 µm ± 50
315 µm ± 50
2.92 mm ± 50 µm
Figure 12. Foot print recommendations Figure 13. Marking
Copper pad Diameter:
250 µm recommended , 300 µm max
Solder stencil opening: 330 µm
Solder mask opening recommendation:
340 µm min for 300 µm copper pad diameter
6/9
Dot, ST logo
xx = marking
z = manufacturing location
yww = datecode
(y = year
ww = week)
E
x x z
y w w
EMIF06-10006F2
Package information
Figure 14. Flip-Chip Tape and reel specification
Dot identifying Pin A1 location
Ø 1.5 +/- 0.1
3.5 +/- 0.1
STE
xxz
yww
STE
xxz
yww
STE
All dimensions in mm
xxz
yww
8 +/- 0.3
0.73 +/- 0.05
1.75 +/- 0.1
4 +/- 0.1
4 +/- 0.1
User direction of unreeling
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a lead-free second level interconnect. The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
Note:
Note: More packing information is available in the application notes:
AN1235: “Flip-Chip: Package description and recommendations for use”
AN1751: "EMI Filters: Recommendations and measurements"
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Ordering Information
4
5
8/9
EMIF06-10006F2
Ordering Information
Ordering code
Marking
Package
Weight
Base qty
Delivery mode
EMIF06-10006F2
FT
Flip-Chip
5.4 mg
5000
Tape and reel 7”
Revision History
Date
Revision
Description of Changes
Sep-2004
1
First issue
19-Nov-2004
2
Figure 2 on page 2:
Basic cell configuration corrected for I/O5 and I/O6.
11-Apr-2006
3
Reformated to current standard. Marking corrected in
ordering information.
17-Nov-2006
4
Ordering code in ordering information corrected.
EMIF06-10006F2
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