STMICROELECTRONICS ESDA14V2-4BF2

ESDA14V2-4BF2
®
ASD
(Application Specific Devices)
QUAD BIDIRECTIONAL TRANSIL™ ARRAY
FOR ESD PROTECTION
APPLICATION
Where transient overvoltage protection in ESD
sensitive equipment is required, such as :
Computers
Printers
■ Communication systems and cellular phones
■ Video equipment
This device is particularly adapted to the
protection of symmetrical signals.
■
■
DESCRIPTION
The ESDA14V2-4BF2 is a monolithic array
designed to protect up to 4 lines in a bidirectional
way against ESD transients.
The device is ideal for situations where board
space saving is requested.
FEATURES
■ 4 Bidirectional Transil functions
■ ESD Protection: IEC61000-4-2 level 4
■ Stand off voltage: 12 V Min.
■ Low leakage current < 1 µA
■ 50 W Peak pulse power (8/20 µs)
Flip-Chip
(5 Bumps)
Table 1: Order Code
Part Number
ESDA14V2-4BF2
Figure 1: Pin Configuration (Bump side)
A3
A1
BENEFITS
■ High ESD protection level
■ High integration
■ Suitable for high density boards
COMPLIES WITH THE FOLLOWING STANDARDS:
IEC61000-4-2
15 kV
(air discharge)
8 kV
(contact discharge)
Marking
EA
C1
C3
GND
Figure 2: Pin Configuration (Bump Side)
3
MIL STD 883F- Method 3015-7: class3
25 kV
(human body model)
2
1
A
B
C
TM: TRANSIL is a trademark of STMicroelectronics.
January 2006
REV. 3
1/7
ESDA14V2-4BF2
Table 2: Absolute Ratings (limiting values)
Symbol
VPP
PPP
Tj
Tstg
Parameter
Value
Unit
± 25
± 15
±8
kV
Peak pulse power (8/20 µs)
50
W
Junction temperature
125
°C
-55 to +150
°C
260
°C
-40 to +125
°C
ESD discharge
MIL STD 883E - Method 3015-7
IEC61000-4-2 air discharge
IEC61000-4-2 contact discharge
Storage temperature range
TL
Lead solder temperature (10 seconds duration)
Top
Operating temperature range
Table 3: Electrical Characteristics (Tamb = 25 °C)
Symbol
VBR
Breakdown voltage
IRM
Leakage current @ VRM
VRM
Stand-off voltage
VCL
Clamping voltage
Rd
Dynamic impedance
IPP
Peak pulse current
C
I
Parameter
VCL VBR VRM
Slope: 1 / Rd
IPP
Capacitance
@ IR
VBR
min.
max.
IRM
@
VRM
max.
Part Number
ESDA14V2-4BF2
V
V
mA
14.2
18
1
Note 1: Square pulse, IPP = 3A, tp = 2.5 µs.
Note 2: ∆VBR = αT (Tamb -25 °C) x VBR (25 °C)
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V
µA
V
1
12
0.1
3
Rd
αT
C
typ.
max.
max.
note 1
note 2
0V bias
Ω
10-4/°C
pF
3.2
10
15
ESDA14V2-4BF2
Figure 3: Clamping voltage versus peak pulse
current (Tj initial = 25 °C) (Rectangular
waveform, tp = 2.5 µs)
Figure 4: Capacitance versus reverse applied
voltage (typical values)
C(pF)
IPP(A)
14
10.0
tp = 2.5µs
F=1MHz
VOSC=30mVRMS
Tj=25°C
12
10
8
1.0
6
4
2
VR(V)
VCL(V)
0
0.1
0
10
20
30
40
50
60
Figure 5: Relative variation of leakage current
versus junction temperature (typical values)
0
2
4
6
8
10
12
14
Figure 6: ESD response to IEC61000-4-2
(+15 kV air discharge)
IR[Tj] / IR[Tj=25°C]
1000
100
V(i/o)
10
Tj(°C)
1
25
50
75
100
125
Figure 7: ESD response to IEC61000-4-2
(-15 kV air discharge)
Figure 8: Analog crosstalk
Typical crosstalk response of ESDA14V2-4BF1 (A1/A3 line)
0.00
-10.00
-20.00
-30.00
V(i/o)
-40.00
-50.00
-60.00
-70.00
-80.00
-90.00
-100.0
100.0k
1.0M
10.0M
f/Hz
100.0M
1.0G
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ESDA14V2-4BF2
Figure 9: Digital crosstalk
rise time: t10-90% = 3ns
VG1
VIN = A1
V = 0-3V
F = 5MHz
β21VG1
VOUT = C3
Figure 10: Application example
A1
Connector
A3
IC
to be
protected
C1
C3
B2
Figure 11: Aplac model
1.2pF
1.2pF
100m
100m
D02_r
BV = 16
IBV = 1m
CJO = 200p
M = 0.3333
RS = 1
VJ = 0.6
TT = 100n
4/7
1.2pF
100m
D02_r
D02_f
BV = 16
IBV = 1m
CJO = 10.4p
M = 0.3333
RS = 2
VJ = 0.6
TT = 100n
B2
B2
50pH 50m
C3
C1
A3
A1
160pH 1.8
1.2pF
100m
ESDA14V2-4BF2
Figure 12: Ordering Information Scheme
ESDA
14V2 - 4
B
Fx
ESD Array
Breakdown Voltage
14V2 = 14.2 Volts min.
Number of line
4 = 4 lines
Type
B = Bidirectional
Package
F = Flip-Chip
x = 2: Leadfree Pitch = 500µm, Bump = 315µm
Figure 13: FLIP-CHIP Package Mechanical Data
700µm ± 50
650µm ± 65
49
5
µm
±
40
1.12 mm ± 50µm
315µm ± 50
1.12 mm ± 50µm
Figure 14: Foot print recommendations
Copper pad Diameter :
250µm recommended , 300µm max
Figure 15: Marking
Dot, ST logo
xx = marking
z = manufacturing location
yww = datecode
(y = year
ww = week)
E
Solder stencil opening : 330µm
Solder mask opening recommendation :
340µm min for 315µm copper pad diameter
x x z
y ww
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ESDA14V2-4BF2
Figure 16: FLIP-CHIP Tape and Reel Specification
Dot identifying Pin A1 location
1.75 +/- 0.1
Ø 1.5 +/- 0.1
4 +/- 0.1
3.5 +/- 0.1
ST E
xxz
yww
ST E
xxz
yww
ST E
xxz
yww
8 +/- 0.3
0.73 +/- 0.05
4 +/- 0.1
User direction of unreeling
All dimensions in mm
In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These
packages have a Lead-free second level interconnect . The category of second level interconnect is
marked on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
Table 4: Ordering Information
Ordering code
Marking
Package
Weight
Base qty
Delivery mode
ESDA14V2-4BF2
EA
Flip-Chip
2.1 mg
5000
Tape & reel 7”
Note: More informations are available in the application notes:
AN1235: “Flip-Chip: Package description and recommendations for use”
Table 5: Revision History
6/7
Date
Revision
Description of Changes
14-Mar-2005
1
First issue.
18-Oct-2005
2
Dimension from center bump to corner bump changed in
Figure 13 to indicate diagonal instead of perpendicular
measurement. No values changed. ECOPACK statement
added.
17-Jan-2006
3
Die dimensions changed in Figure 13. Cavity depth
changed in Figure 16
ESDA14V2-4BF2
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2006 STMicroelectronics - All rights reserved
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