ESDA6V1-4BC6 ® ASD™ QUAD BIDIRECTIONAL TRANSIL™ SUPPRESSOR FOR ESD PROTECTION MAIN APPLICATIONS Where transient overvoltage protection in ESD sensitive equipment is required, such as: Computers Printers ■ Communication systems ■ Video equipment This device is particularly adapted to the protection of symmetrical signals ■ ■ FEATURES ■ 4 Bidirectional Transil functions ■ ESD Protection for data, Signal and VCC Bus ■ ■ ■ ■ Stand off voltage range: 5 V Low leakage current Peak pulse power (8/20µs); 80W Channel separation: 80dB typ.@20KHz SOT23-6L Table 1: Order Code Part Number ESDA6V1-4BC6 Marking BS77 Figure 1: Functional Diagram DESCRIPTION The ESDA6V1-4BC6 is a monolithic array designed to protect up to 4 lines in a bidirectional way against ESD transients. The device is ideal for situations where board space is at a premium. BENEFITS ■ High ESD protection level ■ High integration ■ Suitable for high density boards 1 6 2 5 3 4 COMPLIES WITH THE FOLLOWING STANDARDS: ■ IEC61000-4-2 level 4: 15kV (air discharge) 8kV (contact discharge) ■ MIL STD 883E-Method 3015-7: class3B (Human Body Model) TM: ASD is a trademark of STMicroelectronics. November 2004 REV. 2 1/6 ESDA6V1-4BC6 Table 2: Absolute Maximum Ratings (Tamb = 25°C) Symbol Parameter MIL STD 883C - Method 3015-6 VPP ESD discharge IEC61000-4-2 air discharge IEC61000-4-2 contact discharge PPP Peak pulse power (8/20µs) Tj Junction temperature Tstg TL Top Storage temperature range Maximum lead temperature for soldering during 10 s at 5mm for case Operating temperature range (note 1) Value 25 15 8 80 Unit kV W 150 °C -55 to +150 °C 260 °C -40 to +125 °C Note 1: Variation of parameters is given by curves. Table 3: Electrical Characteristics (Tamb = 25°C) Symbol Parameter VRM Stand-off voltage VBR Breakdown voltage VCL Clamping voltage IRM Leakage current IPP Peak pulse current Voltage temperature coefficient Forward voltage drop Capacitance Dynamic resistance αT VF C Rd ESDA6V1-4BC6 VBR V RM VCL VBR @ Type I V I RM Rd IR IRM @ VRM max. I PP Rd min. max. typ. note 2 V V mA µA V Ω 6.1 8 1 1 3 0.45 αT max. C typ. 0V bias 10-4/°C 3 pF 45 Note 2: Square pulse, IPP = 3A, tp=2.5µs. Figure 2: Relative variation of peak pulse power versus initial junction temperature Figure 3: Peak pulse power versus exponential pulse duration PPP[Tj initial] / PPP[Tj initial=25°C] PPP(W) 1000 1.1 Tj initial = 25°C 1.0 0.9 0.8 0.7 0.6 100 0.5 0.4 0.3 0.2 0.1 Tj(°C) tp(µs) 10 0.0 0 2/6 25 50 75 100 125 150 1 10 100 ESDA6V1-4BC6 Figure 4: Clamping voltage versus peak pulse current (typical values, rectangular waveform) Figure 5: Junction capacitance versus line voltage applied (typical values IPP(A) C(pF) 100.0 50 F = 1MHz VOSC = 30mV Tj = 25°C 45 40 35 10.0 30 25 20 1.0 15 10 5 tp = 2.5µs Tj initial = 25°C VCL(V) VR(V) 0 0.1 0 5 10 15 20 25 30 35 40 45 50 Figure 6: Relative variation of leakage current versus junction temperature (typical values) 0 1 2 3 4 5 6 Figure 7: Analog crosstalk test configuration IR[Tj] / IR[Tj=25°C] 100 50Ω I/O1 unloaded VG Port 1 GND 10 50Ω I/O6 Port 2 Tj(°C) 1 25 50 75 100 125 1. ESD protection by ESDA6V1-4BC6 With the focus of lowering the operation levels, the problem of malfunction caused by the environment is critical. Electrostatic discharge (ESD) is a major cause of failure in electronic system. Transient Voltage Suppressors are an ideal choice for ESD protection and have proven capable in suppressing ESD events. They are capable of clamping the incoming transient to a low enough level such that damage to the protected semiconductor is prevented. Surface mount TVS arrays offer the best choice for minimal lead inductance. They serve as parallel protection elements, connected between the signal line to ground. As the transient rises above the operating voltage of the device, the TVS array becomes a low impedance path diverting the transient current to ground. ® 3/6 ESDA6V1-4BC6 Figure 8: Bidirectional protection for 0V biased signals CONNECTOR DRIVER 1 6 2 5 3 4 The ESDA6V1-4BC6 array is the ideal product for use as board level protection of ESD sensitive semiconductor components. The tiny SOT23-6L package allows design flexibility in the design of “crowded” boards where the space saving is at a premium. This enables to shorten the routing and can contribute to improve ESD performance. 2. Circuit Board Layout Circuit board layout is a critical design step in the suppression of ESD induced transients. The following guidelines are recommended : ■ ■ ■ ■ ■ The ESDA6V1-4BC6 should be placed as near as possible to the input terminals or connectors. Minimise the path length between the ESD suppressor and the protected device Minimise all conductive loops, including power and ground loops The ESD transient return path to ground should be kept as short as possible. Use ground planes whenever possible. Figure 9: Ordering information scheme ESDA ESD Array Breakdown Voltage (min) 6V1 = 6.1 Volt Number and type of lines protected 4B = 4 Bidirectional lines Package C6 = SOT23-6L 4/6 6V1 - 4B C6 ESDA6V1-4BC6 Figure 10: SOT23-6L Package Mechanical Data DIMENSIONS REF. A2 A D b A1 L H E Millimeters Min. A 0.90 A1 0 c e e Max. Inches Min. Typ. Max. 1.45 0.035 0.057 0.10 0.004 0 A2 0.90 1.30 0.035 0.051 b 0.35 0.50 0.014 0.02 C 0.09 0.20 0.004 0.008 D 2.80 3.05 0.110 0.120 E 1.50 e θ Typ. 1.75 0.059 0.95 0.069 0.037 H 2.60 3.00 0.102 0.118 L 0.10 0.60 0.004 0.024 θ 10° 10° Figure 11: Foot Print Dimensions (in millimeters) 0.60 1.20 3.50 2.30 0.95 1.10 Table 4: Ordering Information Part Number Marking Package Weight Base qty Delivery mode ESDA6V1-4BC6 BS77 SOT23-6L 16.7 mg 3000 Tape & reel Table 5: Revision History ® Date Revision Nov-2002 1A 4-Nov-2004 2 Description of Changes First issue. SOT23-6L package dimensions change for reference “D” from 3.0 millimeters (0.118 inches) to 3.05 millimeters (0.120 inches). 5/6 ESDA6V1-4BC6 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners © 2004 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 6/6