HCF4517B DUAL 64 STAGE STATIC SHIFT REGISTER ■ ■ ■ ■ ■ ■ ■ ■ ■ CLOCK FREQUENCY 12MHz (Typ.) at VDD = 10V SCHMITT TRIGGER CLOCK INPUTS ALLOWS OPERATION WITH VERY SLOW CLOCK RISE AND FALL TIMES THREE STATE OUTPUTS QUIESCENT CURRENT SPECIFIED UP TO 20V STANDARDIZED, SYMMETRICAL OUTPUT CHARACTERISTCS 5V, 10V AND 15V PARAMETRIC RATINGS INPUT LEAKAGE CURRENT II = 100nA (MAX) AT VDD = 18V TA = 25°C 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC JESD13B "STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICES" DESCRIPTION HCF4517B is a monolithic integrated circuit fabricated in Metal Oxide Semiconductor technology available in DIP package. This device is a dual 64-stage static shift register consisting of two independent registers each having a clock, data, and write enable input and outputs accessible by stages following the 16th, DIP ORDER CODES PACKAGE TUBE T&R DIP SOP HCF4517BEY HCF4517BM1 HCF4517M013TR 32nd, 48th, and 64th stages. These stages also serve as input points allowing data to be put in at the 17th , 33rd, and 49th stages when the write enable input is a logic 1 and the clock goes through a low to high transition. The truth table indicates how the clock and write enable inputs control the operation of HCF4517B. Inputs at the intermediate stages allow entry of 64-bits into the register with 16 clock pulses. The 3-state outputs permit connection of this device to an external bus. PIN CONNECTION September 2002 1/8 HCF4517B INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL 1, 2, 5, 6 10, 11,14, 15 3, 13 7, 9 4, 12 8 NAME AND FUNCTION QnA IN/OUT Stage QnB IN/OUT Stage WEA, WEB Write Enable DA, DB Data Input CLA, CLB Clock VSS Negative Supply Voltage VDD 16 Positive Supply Voltage FUNCTIONAL DIAGRAM (One Half) TRUTH TABLES CLOCK WRITE ENABLE DATA L L H H L H L H X X X X Q16 Z Q16 Z Q32 Z Q32 Z Q48 Z Q48 Z Q64 Z Q64 Z L DI In Q16 Q32 Q48 Q64 H DI In D17 In D33 In D49 In Z L X Q16 Q32 Q48 Q64 H X Z Z Z Z X : Don’t Care 2/8 STAGE 16 TAP STAGE 32 TAP STAGE 48 TAP STAGE 64 TAP HCF4517B LOGIC DIAGRAM ABSOLUTE MAXIMUM RATINGS Symbol VDD Parameter Supply Voltage VI DC Input Voltage II DC Input Current PD Value Unit -0.5 to +22 V -0.5 to VDD + 0.5 ± 10 V mA 200 100 mW mW Top Power Dissipation per Package Power Dissipation per Output Transistor Operating Temperature -55 to +125 °C Tstg Storage Temperature -65 to +150 °C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. All voltage values are referred to VSS pin voltage. RECOMMENDED OPERATING CONDITIONS Symbol VDD Parameter Supply Voltage VI Input Voltage Top Operating Temperature Value Unit 3 to 20 V 0 to VDD V -55 to 125 °C 3/8 HCF4517B DC SPECIFICATIONS Test Condition Symbol IL VOH VOL VIH VIL IOH IOL IOL II IOZ CI Parameter Quiescent Current High Level Output Voltage Low Level Output Voltage VI (V) 0/5 0/10 0/15 0/20 0/5 0/10 0/15 5/0 10/0 15/0 High Level Input Voltage Low Level Input Voltage Output Drive Current Output Sink Current Q Output Sink Current Input Leakage Current 3-State Output Leakage Current Input Capacitance VO (V) 0/5 0/5 0/10 0/15 0/5 0/10 0/15 0/5 0/10 0/15 0.5/4.5 1/9 1.5/13.5 4.5/0.5 9/1 13.5/1.5 2.5 4.6 9.5 13.5 0.4 0.5 1.5 0.4 0.5 1.5 Value |IO| VDD (µA) (V) <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 <1 5 10 15 20 5 10 15 5 10 15 5 10 15 5 10 15 5 5 10 15 5 10 15 5 10 15 TA = 25°C Min. Typ. Max. 0.04 0.04 0.04 0.08 5 10 20 100 4.95 9.95 14.95 -40 to 85°C -55 to 125°C Min. Min. 150 300 600 3000 4.95 9.95 14.95 0.05 0.05 0.05 4.95 9.95 14.95 3.5 7 11 1.5 3 4 -3.2 -1 -2.6 -6.8 4 10.4 27.2 1 2.6 6.8 3.5 7 11 1.5 3 4 -1.1 -0.36 -0.9 -2.4 1.43 3.74 9.52 0.36 0.9 2.4 µA V 0.05 0.05 0.05 V V 1.5 3 4 -1.1 -0.36 -0.9 -2.4 1.43 3.74 9.52 0.36 0.9 2.4 V mA mA mA 0/18 Any Input 18 ±10-5 ±0.1 ±1 ±1 µA 0/18 Any Input 18 ±10-4 ±0.4 ±12 ±12 µA 5 7.5 Any Input The Noise Margin for both "1" and "0" level is: 1V min. with VDD =5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V 4/8 Max. 150 300 600 3000 0.05 0.05 0.05 3.5 7 11 -1.36 -0.44 -1.1 -3.0 1.74 4.42 11.56 0.44 1.1 3.0 Max. Unit pF HCF4517B DYNAMIC ELECTRICAL CHARACTERISTICS (Tamb = 25°C, CL = 50pF, RL = 200KΩ, tr = tf = 20 ns) Test Condition Symbol Parameter tPHL tPLH Propagation Delay Time : CL to Bit 16 Tap tPLZ tPHZ 3-State Output WE to Bit tPZL tPZH 16 Tap (see note) tTHL tTLH Output Transition Time tsetup tsetup Setup Time (WRITE ENABLE to CLOCK) Setup Time (DATA to CLOCK) Release Time (WRITE ENABLE to CLOCK) thold tW fCL tr tf Hold Time (DATA to CLOCK) Minimum Clock Pulse Width Maximum Clock Input Frequency Maximum Clock Input Rise or Fall Time VDD (V) 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 Value (*) Min. -100 -50 -30 -100 -60 -30 3 6 8 Unit Typ. Max. 200 110 90 75 40 30 100 50 40 -50 -25 -15 -50 -30 -15 50 25 20 100 50 25 90 40 25 6 12 15 400 220 180 150 80 60 200 100 80 ns ns ns ns ns 100 50 40 200 100 50 180 80 50 Unlimited ns ns ns MHz µs (*) Typical temperature coefficient for all VDD value is 0.3 %/°C. NOTE : Measured at the point of 10% change in output load of 50pF, RL = 1KΩ to VDD for tPZL, tPLZ and RL = 1KΩ to VSS for tPHZ 5/8 HCF4517B TEST CIRCUIT TEST SWITCH tPLH, tPHL Open tPZL, tPLZ VDD tPZH, tPHZ VSS CL = 50pF or equivalent (includes jig and probe capacitance) RL = 200KΩ RT = ZOUT of pulse generator (typically 50Ω) WAVEFORM : PROPAGATION DELAY TIMES (f=1MHz; 50% duty cycle) 6/8 HCF4517B Plastic DIP-16 (0.25) MECHANICAL DATA mm. inch DIM. MIN. a1 0.51 B 0.77 TYP MAX. MIN. TYP. MAX. 0.020 1.65 0.030 0.065 b 0.5 0.020 b1 0.25 0.010 D 20 0.787 E 8.5 0.335 e 2.54 0.100 e3 17.78 0.700 F 7.1 0.280 I 5.1 0.201 L Z 3.3 0.130 1.27 0.050 P001C 7/8 HCF4517B Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. © The ST logo is a registered trademark of STMicroelectronics © 2002 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. © http://www.st.com 8/8