STMICROELECTRONICS L5991AD

L5991
L5991A

PRIMARY CONTROLLER WITH STANDBY
CURRENT-MODE CONTROL PWM
SWITCHING FREQUENCY UP TO 1MHz
LOW START-UP CURRENT (< 120µA)
HIGH-CURRENT OUTPUT DRIVE SUITABLE
FOR POWER MOSFET (1A)
FULLY LATCHED PWM LOGIC WITH DOUBLE PULSE SUPPRESSION
PROGRAMMABLE DUTY CYCLE
100%AND 50% MAXIMUM DUTY CYCLE LIMIT
STANDBY FUNCTION
PROGRAMMABLE SOFT START
PRIMARY OVERCURRENT FAULT DETECTION WITH RE-START DELAY
PWM UVLO WITH HYSTERESIS
IN/OUT SYNCHRONIZATION
LATCHED DISABLE
INTERNAL 100ns LEADING EDGE BLANKING OF CURRENT SENSE
PACKAGE: DIP16 AND SO16
MULTIPOWER BCD TECHNOLOGY
DIP16
SO16
ORDERING NUMBERS: L5991/L5991A (DIP16)
L5991D/L5991AD (SO16)
line or DC-DC power supply applications using a
fixed frequency current mode control.
Based on a standard current mode PWM controller this device includes some features such as
programmable soft start, IN/OUT synchronization,
disable (to be used for over voltage protection and
for power management), precise maximum Duty
Cycle Control, 100ns leading edge blanking on
current sense, pulse by pulse current limit, overcurrent protection with soft start intervention, and
Standby function for oscillator frequency reduction
when the converter is lightly loaded.
DESCRIPTION
This primary controller I.C., developed in BCD60II
technology, has been designed to implement off
BLOCK DIAGRAM
SYNC
1
RCT
2
VCC
DC-LIM
15
VREF
8
4
TIMING
25V
+
3
DC
14
-
DIS
Vref
+
15V/10V
T
PWM UVLO
-
9
DIS
VC
+
2.5V
13V
S
BLANKING
10
OUT
Q
R
PWM
OVER CURRENT
ISEN
13
1.2V
SS
FAULT
SOFT-START
+
VREF
VREF OK
CLK
DIS
STAND-BY
-
7
+
2.5V
5
E/A
-
2R
1V
PGND
ST-BY
VFB
R
12
SGND
August 1999
11
16
6
COMP
D97IN725A
1/23
L5991 - L5991A
ABSOLUTE MAXIMUM RATINGS
Symbol
VCC
IOUT
Ptot
Tj
Tstg
Parameter
Supply Voltage (ICC < 50mA) (*)
Output Peak Pulse Current
Analog Inputs & Outputs (6,7)
Analog Inputs & Outputs (1,2,3,4,5,15,14, 13, 16)
Power Dissipation @ Tamb = 70°C (DIP16)
@ Tamb = 50°C (SO16)
Junction Temperature, Operating Range
Storage Temperature, Operating Range
Value
selflimit
1.5
-0.3 to 8
-0.3 to 6
1
0.83
-40 to 150
-55 to 150
Unit
V
A
V
V
W
W
°C
°C
Value
80
120
°C/W
°C/W
(*) maximum package power dissipation limits must be observed
PIN CONNECTION
SYNC
1
16
ST-BY
RCT
2
15
DC-LIM
DC
3
14
DIS
VREF
4
13
ISEN
VFB
5
12
SGND
COMP
6
11
PGND
SS
7
10
OUT
V CC
8
9
VC
THERMAL DATA
Symbol
Rth j-amb
Parameter
Thermal Resistance Junction -Ambient (DIP16)
Thermal Resistance Junction -Ambient (SO16)
Unit
PIN FUNCTIONS
N.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Name
SYNC
RCT
DC
VREF
VFB
COMP
SS
VCC
VC
OUT
PGND
SGND
ISEN
DIS
DC-LIM
16
ST-BY
2/23
Function
Synchronization. A synchronization pulse terminates the PWM cycle and discharges Ct
Oscillator pin for external CT, RA, RB components
Duty Cycle control
5.0V +/-1.5% reference voltage @ 25°C
Error Amplifier Inverting input
Error Amplifier Output
Soft start pin for external capacitor Css
Supply for internal ”Signal” circuitry
Supply for Power section
High current totem pole output
Power ground
Signal ground
Current sense
Disable. It must never be left floating. TIE to SGND if not used.
Connecting this pin to Vref, DC is limited to 50%. If it is left floating or grounded no limitation is
imposed
Standby. Connect a resistor to RCT. Connect to VREF or floating if not used.
L5991 - L5991A
ELECTRICAL CHARACTERISTICS (VCC = 15V; Tj = 0 to 105°C; RT = 13.3kΩ (*) CT = 1nF;
unless otherwise specified.)
Symbol
Parameter
REFERENCE SECTION
Output Voltage
VREF
Line Regulation
Load Regulation
Temperature Stability
TS
Total Variation
Short Circuit Current
IOS
Power Down/UVLO
OSCILLATOR SECTION
Initial Accuracy
Duty Cycle
Duty Cycle Accuracy
Oscillator Ramp Peak
Oscillator Ramp Valley
ERROR AMPLIFIER SECTION
Input Bias Current
Input Voltage
VI
Open Loop Gain
GOPL
SVR
Supply Voltage Rejection
Output Low Voltage
V OL
Output High Voltage
VOH
Output Source Current
IO
Output Sink Current
Unit Gain Bandwidth
Slew Rate
SR
PWM CURRENT SENSE SECTION
Input Bias Current
Ib
Maximum Input Signal
IS
Delay to Output
Gain
Fault Threshold Voltage
Vt
SOFT START SECTION
SS Charge Current
ISSC
SS Discharge Current
ISSD
SS Saturation Voltage
VSSSAT
SS Clamp Voltage
VSSCLAMP
LEADING EDGE BLANKING
Internal Masking Time
OUTPUT SECTION
Output Low Voltage
V OL
Output High Voltage
VOH
VOUT CLAMP
Output Clamp Voltage
Collector Leakage
Test Condition
Min.
Typ.
Max.
Unit
Tj = 25°C; IO = 1mA
VCC = 12 to 20V; Tj = 25°C
IO = 1 to 10mA; Tj = 25°C
4.925
5.075
10
10
Line, Load, Temperature
Vref = 0V
VCC = 6V; Isink = 0.5mA
4.80
30
5.0
2.0
2.0
0.4
5.0
0.2
5.130
150
0.5
V
mV
mV
mV/°C
V
mA
V
95
100
105
kHz
93
100
107
kHz
46.5
50
53.5
kHz
0
0
%
%
%
%
%
V
V
pin 15 = Vref;
Tj = 25°C
Vcomp = 4.5V
pin 15 = Vref; VCC = 12 to 20V
Vcomp = 4.5V
pin 15 = Vref; VCC = 12 to 20V
Vcomp = 2V
pin 3 = 0,7V, pin 15 = VREF
pin 3 = 0.7V, pin 15 = OPEN
pin 3 = 3.2V, pin 15 = VREF
pin 3 = 3.2V, pin 15 = OPEN
pin 3 = 2.79V, pin 15 = OPEN
VFB to GND
VCOMP = VFB
VCOMP = 2 to 4V
VCC = 12 to 20V
Isink = 2mA
Isou rce = 0.5mA, VFB = 2.3V
VCOMP > 4V, V FB = 2.3V
VCOMP = 1.1V, V FB = 2.7V
Isen = 0
VCOMP = 5V
Tj = 25°C
VSS = 0.6V Tj = 25°C
DC = 0%
IO = 250mA
IO = 20mA; VCC = 12V
IO = 200mA; VCC = 12V
IO = 5mA; VCC = 20V
VCC = 20V VC = 24V
47
93
75
2.8
0.75
2.42
60
80
3.0
0.9
85
3.2
1.05
0.2
2.5
90
85
3.0
2.58
1.1
5
0.5
2
1.7
6
1.3
6
4
8
2.5
µA
V
dB
dB
V
V
mA
mA
MHz
V/µs
2.85
1.1
3
1.0
70
3
1.2
15
1.08
100
3.15
1.3
µA
V
ns
V/V
V
14
5
20
10
26
15
0.6
7
µA
µA
V
V
100
ns
0.92
1.0
10
9
10.5
10
13
2
20
V
V
V
V
µA
(*) RT = RA//RB , RA = RB = 27kΩ, see Fig. 22.
3/23
L5991 - L5991A
ELECTRICAL CHARACTERISTICS (continued.)
Symbol
Parameter
OUTPUT SECTION
Fall Time
Test Condition
C O = 1nF
C O = 2.5nF
C O = 1nF
C O = 2.5nF
VCC = VC = 0 to VCCON
Isink = 10mA
Rise Time
UVLO Saturation
SUPPLY SECTION
Startup voltage
VCCON
Vhys
UVLO Hysteresis
IS
Start Up Current
Iop
Iq
Operating Current
Quiescent Current
14
7.8
9
7
4.5
0.5
40
Before Turn-on at:
VCC = VC = VCCON -0.5V
CT = 1nF, R T = 13.3kΩ, CO =1nF
(After turn on), CT = 1nF,
R T = 13.3kΩ, CO =0nF
I8 = 20mA
Zener Voltage
VZ
STANDBY FUNCTION
VREF-VST-BY
Standby Threshold
VT1
Typ.
Max.
Unit
20
35
50
70
60
ns
ns
ns
ns
V
100
1.0
L5991
L5991A
L5991
L5991A
L5991
L5991A
Minimum Operating Voltage
VCCOFF
Min.
21
IST-BY = 2mA
Vcomp Falling
Vcomp Rising
15
8.4
10
7.6
5
0.8
75
16
9
11
8.2
120
V
V
V
V
V
V
µA
9
7.0
13
10
mA
mA
25
30
V
45
2.5
4.0
mV
V
V
7
V
mA
SYNCHRONIZATION SECTION
V1
I1
Clock Amplitude
Clock Source Current
V1
Sync Pulse
Master Operation
ISOURCE = 0.8mA
Vclock = 3.5V
Slave Operation
Low Level
High Level
VSYNC = 3.5V
Sync Pulse Current
I1
OVER CURRENT PROTECTION
Fault Threshold Voltage
Vt
DISABLE SECTION
Shutdown threshold
Shutdown Current
ISH
4
3
V
V
mA
1.1
1.2
1.3
V
2.4
2.5
330
2.6
V
µA
VCC = 15V
Figure 1. L5991 - Quiescent current vs. input
voltage.
(X = 7.6V and Y= 8.4V for L5991A)
1
3.5
0.5
Figure 2. L5991 - Quiescent current vs. input
voltage (after disable).
(X = 7.6V and Y= 8.4V for L5991A)
Iq [m A ]
30
350
V 1 4 = 0, P in 2 = ope n
T j = 2 5 °C
20
300
8
250
6
200
4
150
0 .2
0 .1 5
V 14 = Vref
T j = 2 5 °C
100
0 .1
X
0 .0 5
0
4
8
12
16
V c c [V ]
X
50
Y
0
0
4/23
Iq [µ A ]
20
24
28
0
4
8
Y
12
16
V cc [V ]
20
24
L5991 - L5991A
Figure 3. Quiescent current vs. input voltage.
Figure 4. Quiescent current vs. input voltage
and switching frequency.
Iq [m A ]
9 .0
Iq [mA]
36
V 1 4 = 0 , V 5 = V re f
C o = 1 n F, T j = 2 5 °C
30
R t = 4 .5 K o h m ,T j = 2 5 °C
8 .5
DC = 0%
1M hz
24
5 00K hz
300K hz
8 .0
1M Hz
18
500KHz
100K hz
12
3 00 K Hz
7 .5
1 0 0K Hz
6
0
7 .0
8
10
12
14
16
18
V c c [V ]
20
22
24
8
10
12
14
16
V cc [ V ]
18
20
22
Figure 5. Quiescent current vs. input voltage
and switching frequency.
Figure 6. Reference voltage vs. load current.
Iq [mA]
36
Vref [V]
5.1
Co= 1nF, Tj = 25°C
30
DC = 100%
24
1MHz
18
500KHz
Vcc=15V
5.05
Tj = 25°C
5
300KHz
12
4.95
100KHz
6
4.9
0
0
8
10
12
14
16
Vcc [V]
18
20
5
10
22
15
20
25
Iref [mA]
Figure 7. Vref vs. junction temperature.
Figure 8. Vref vs. junction temperature.
Vref [V])
Vref [V]
5.1
5.1
Vcc = 15V
Vcc = 15V
5.05
5.05
Iref= 20mA
Iref = 1mA
5
5
4.95
4.95
4.9
-50
-25
0
25
50
Tj (°C)
75
100
125
150
4.9
-50
-25
0
25
50
Tj (°C)
75
100
125
150
5/23
L5991 - L5991A
Figure 9. Vref SVRR vs. switching frequency.
Figure 10. Output saturation.
Vsat = V
SVRR (dB)
[V]
10
16
Vcc = Vc = 15V
Vcc=15V
120
14
Vp-p=1V
Tj = 25°C
12
80
10
40
8
6
0
1
10
100
1000
fsw (Hz)
0
10000
Figure 11. Output saturation.
0.4
0.6
0.8
Isource [A]
1
1.2
Figure 12. UVLO Saturation
V sat = V10 [V]
Ipin10 [mA]
2.5
50
2
30
1
20
0.5
10
0
0.2
0.4
Vcc < Vccon
beforeturn-on
40
Vcc = Vc = 15V
T j = 25°C
1.5
0
0.2
0.6
0.8
1
1.2
0
0
200
400
Isink [A ]
Figure 13. Timingresistor vs.switchingfrequency.
1,000 1,200 1,400
Figure 14. Switching frequency vs. temperature.
fsw (KHz)
fsw (KHz)
5000
320
Vcc
600 800
Vpin10 [mV]
= 15V, V15 =0V
2000
R t= 4.5Kohm, C t = 1nF
Tj = 25°C
1000
310
Vcc = 15V, V15=Vref
500
100pF
200
300
220pF
100
470pF
50
20
290
1 nF
2.2nF
5 .6nF
10
10
20
Rt (kohm)
6/23
30
40
280
-50
-25
0
25
50
Tj (°C)
75
100
125
150
L5991 - L5991A
Figure 15. Switching frequency vs. temperature.
Figure 16. Dead time vs Ct.
fsw (KHz)
320
Dead time [ns]
1,500
Rt= 4.5Kohm, Ct = 1nF
310
Rt =4.5Kohm
V15 = 0V
Vcc = 15V, V15= 0
1,200
900
300
V15 = Vref
600
290
300
280
-50
-25
0
25
50
75
100
125
150
2
4
6
8
Timing capacitor Ct [nF]
Tj (°C)
Figure 17. Maximum Duty Cycle vs Vpin3.
10
Figure18.Delayto outputvs junctiontemperature.
DC Control Voltage Vpin3 [V]
3.5
Delay to output (ns)
42
V15 = 0V
V15 = Vref
40
3
38
2.5
36
34
2
Rt = 4.5Kohm,
32
PIN10 = OPEN
1V pulse
on PIN13
Ct = 1nF
1.5
30
1
0
10
20
30
40 50 60 70
Duty Cycle [%]
80
90 100
28
-50
-25
0
25
50
75
100
125
150
Tj (°C)
Figure 19. E/A frequency response.
G [dB]
Phase
140
150
120
100
100
80
50
60
0
40
20
0.01
0.1
1
10
100
f (KHz)
1000
10000 100000
7/23
L5991 - L5991A
STANDBY FUNCTION
The standby function, optimized for flyback topology, automatically detects a light load condition
for the converter and decreases the oscillator frequency on that occurrence. The normal oscillation
frequency is automatically resumed when the output load builds up and exceeds a defined threshold.
This function allows to minimize power losses related to switching frequency, which represent the
majority of losses in a lightly loaded flyback, without giving up the advantages of a higher switching
frequency at heavy load.
This is accomplished by monitoring the output of
the Error Amplifier (VCOMP) that depends linearly
on the peak primary current, except for an offset.
If the the peak primary current decreases (as a result of a decrease of the power demanded by the
load) and VCOMP falls below a fixed threshold
(VT1), the oscillator frequency will be set to a
lower value (fSB). When the peak primary current
increases and VCOMP exceeds a second threshold
(VT2) the oscillator frequency is set to the normal
value (fosc). An appropriate hysteresis (VT2-VT1)
prevents undesired frequency change when
power is such that VCOMP moves close to the
threshold. This operation is shown in fig. 20.
Both the normal and the standby frequency are
externally programmable. VT1 and VT2 are internally fixed but it is possible to adjust the thresholds in terms of input power level.
Figure 20. Standby dynamic operation.
APPLICATION INFORMATION
Detailed Pin Function Description
Pin 1. SYNC (In/Out Synchronization). This function allows the IC’s oscillator either to synchronize
other controllers (master) or to be synchronized to
an external frequency (slave).
As a master, the pin delivers positive pulses during the falling edge of the oscillator (see pin 2). In
slave operation the circuit is edge triggered. Refer
to fig. 22 to see how it works. When several IC
work in parallel no master-slave designation is
needed because the fastest one becomes auto-
Pin 2. RCT (Oscillator). Two resistors (RA and RB)
and one capacitor (CT), connected as shown in
fig. 22, allow to set separately the operating frequency of the oscillator in normal operation (fosc)
and in standby mode (fSB).
CT is charged from Vref through RA and RB in normal operation (STANDBY = HIGH), through RA
only in standby ( STANDBY = LOW). See pin 16
description to see how the STANDBY signal is generated.
When the voltage on CT reaches 3V, the capacitor is quickly internally discharged. As the voltage
has dropped to 1V it starts being charged again.
Pin
fos c
Normal operation
PNO
fSB
PSB
Stand-by
1
VT1
2
VT2
3
4
VCOMP
matically the master.
During the ramp-up of the oscillator the pin is
pulled low by a 600µA internal sink current generator. During the falling edge, that is when the
pulse is released, the 600µA pull-down is disconnected. The pin becomes a generator whose
source capability is typically 7mA (with a voltage
still higher than 3.5V).
In fig. 21, some practical examples of synchronizing the L5991 are given.
Since the device automatically diminishes its operating frequency under light load conditions, it is
reasonable to suppose that synchronization will
refer to normal operation and not to standby.
Figure 21. Synchronizing the L5991.
RA
RB
SYNC
1
SYNC
ST-BY
16
L5991
4
VREF
2
RA
RCT
L5991
2
17
(a)
16
L5991
(SLAVE)
1
4
SYNC
18
2
VREF
RB
RA
ROSC
COSC
CT
(b)
4
RCT
VREF
RCT
RCT
CT
8/23
ST-BY
L4981A
(MASTER)
16
1
2 L5991 1
(MASTER)
16
RB
L4981A
(SLAVE)
SYNC
SYNC
16 17
18
ST-BY
ROSC
CT
D97IN728A
(c)
COSC
L5991 - L5991A
Figure 22. Oscillator and synchronization internal schematic.
SYNC
VREF
1
4
R1
D
CLAMP
R
R3
RA
RCT
600µA
R2
+
2
Q
CLK
D1
RB
CT
50Ω
ST-BY
16
STANDBY
D97IN729A
The oscillation frequency can be established with
the aid of the diagrams of fig. 13, where RT will be
intended as the parallel of RA and RB in normal
operation and RT = RA in standby, or considering
the following approximate relationships:
fosc ≅
1
CT ⋅ (0.693 ⋅ (RA // RB) + KT
(1),
from fig. 13 or resulting from (1) and (2).
To prevent the oscillator frequency from switching
back and forth from fosc to fSB, the ratio fosc / fSB
must not exceed 5.5.
If during normal operation the IC is to be synchronized to an external oscillator, RA, RB and CT
should be selected for a fosc lower than the master
frequency in any condition (typically, 10-20% ),
depending also on the tolerance of the parts.
which gives the normal operating frequency, and:
fSB ≅
1
CT ⋅ (0.693 ⋅ RA + KT)
(2),
which gives the standby frequency, that is the one
the converter will operate at when lightly loaded.
In the above expressions, RA // RB means:
RA ⋅ RB
RA//RB =
,
RA + RB
while KT is defined as:
90 V15 = VREF
(3),
KT = 
160 V15 = GND/OPEN
and is related to the duration of the falling-edge of
the sawtooth:
Td ≈ 30 ⋅ 10−9 + KT ⋅ CT (4).
Td is also the duration of the sync pulses delivered at pin 1 and defines the upper extreme of the
duty cycle range, Dx (see pin 15 for DX definition
and calculation) since the output is held low during the falling edge.
In case V15 is connected to VREF, however, the
switching frequency will be a half the values taken
Pin 3. DC (Duty Cycle Control). By biasing this
pin with a voltage between 1 and 3 V it is possible
to set the maximum duty cycle between 0 and the
upper extreme Dx (see pin 15).
If Dmax is the desired maximum duty cycle, the
voltage V3 to be applied to pin 3 is:
V3 = 5 - 2(2-Dmax) (5)
Dmax is determined by internal comparison between V3 and the oscillator ramp (see fig. 23),
thus in case the device is synchronized to an external frequency fext (and therefore the oscillator
amplitude is reduced), (5) changes into:
Dmax


V3 = 5 − 4 ⋅ exp  −
 (6)
 RT ⋅ CT ⋅ fext
A voltage below 1V will inhibit the driver output
stage. This could be used for a not-latched device
disable, for example in case of overvoltage protection (see application ideas).
If no limitation on the maximum duty cycle is required (i.e. DMAX = DX), the pin has to be left floating. An internal pull-up (see fig. 23) holds the voltage above 3V. Should the pin pick up noise (e.g.
9/23
L5991 - L5991A
during ESD tests), it can be connected to VREF
through a 4.7kΩ resistor.
Figure 23. Duty cycle control.
VREF
4
DC
3
R1
RA
3µA
23K
R2
28K
ST-BY
RB
RCT
3 ⋅ Rsense ⋅ IQpk
⋅ Css
(7)
ISSC
where Rsense is the current sense resistor (see pin
13) and IQpk is the switch peak current (flowing
through Rsense), which depends on the output
load. Usually, CSS is selected for a TSS in the order of milliseconds.
As mentioned before, the soft-start intervenes
also in case of severe overload or short circuit on
the output. Referring to fig. 24, pulse-by-pulse
current limitation is somehow effective as long as
Tss ≅
16
2
+
TO PWM LOGIC
-
CT
D97IN727A
Pin 4. VREF (Reference Voltage). The device is
provided with an accurate voltage reference
(5V±1.5%) able to deliver some mA to an external
circuit.
A small film capacitor (0.1 µF typ.), connected
between this pin and SGND, is recommended to
ensure the stability of the generator and to prevent
noise from affecting thereference.
Before device turn-on, this pin has a sink current capability of 0.5mA.
Pin 5. VFB (Error Amplifier Inverting Input). The
feedback signal is applied to this pin and is compared to the E/A internal reference (2.5V). The
E/A output generates the control voltage which
fixes the duty cycle.
The E/A features high gain-bandwidth product,
which allows to broaden the bandwidth of the
overall control loop, high slew-rate and current capability, which improves its large signal behavior.
Usually the compensation network, which stabilizes the overall control loop, is connected between this pin and COMP (pin 6).
Pin 6. COMP (Error Amplifier Output). Usually,
this pin is used for frequency compensation and
the relevant network is connected between this
pin and VFB (pin 5). Compensation networks towards ground are not possible since the L5991
E/A is a voltage mode amplifier (low output impedance). See application ideas for some example of compensation techniques.
It is worth mentioning that the calculation of the
part values of the compensation network must
take the standby frequency operation into account. In particular, this means that the open-loop
crossover frequency must not exceed fSB/4 ÷
fSB/5.
The voltage on pin 6 is monitored in order to re10/23
duce the oscillator frequency when the converter
is lightly loaded (standby).
Pin 7. SS (Soft-Start). At device start-up, a capacitor (Css) connected between this pin and
SGND (pin 12) is charged by an internal current
generator, ISSC, up to about 7V. During this
ramp, the E/A output is clamped by the voltage
across Css itself and allowed to rise linearly, starting from zero, up to the steady-state value imposed by the control loop. The maximum time interval during which the E/A is clamped, referred to
as soft-start time, is approximately:
Figure 24. Regulation characteristic and related quantities.
VOUT
IQpk
A
D.C.M.
C.C.M.
1-2 ·IQpk
IQpk(max)
B
C
TON
D
TON(min)
D97IN495
ISHORT IOUT(max)
IOUT
the ON-time of the power switch can be reduced
(from A to B). After the minimum ON-time is
reached (from B onwards) the current is out of
control.
To prevent this risk, a comparator trips an overcurrent handling procedure, named ’hiccup’ mode
operation, when a voltage above 1.2V (point C) is
detected on current sense input (ISEN, pin 13).
Basically, the IC is turned off and then soft-started
as long as the fault condition is detected. As a result, the operating point is moved abruptly to D,
creating a foldback effect. Fig. 25 illustrates the
operation.
The oscillation frequency appearing on the softstart capacitor in case of permanent fault, referred
to as ’hiccup” period, is approximately given by:
 1
Thic ≅ 4.5 ⋅ 
ISSC
+
1 
⋅ Css (8)
ISSD 
L5991 - L5991A
Since the system tries restarting each hiccup cycle, there is not any latchoff risk.
”Hiccup” keeps the system in control in case of
short circuits but does not eliminate power components overstress during pulse-by-pulse limitation (from A to C). Other external protection circuits are needed if a better control of overloads is
required.
MOS. At turn-on the gate resistance is Rg + Rg’, at
turn-off is Rg only.
Figure 26. Turn-on and turn-off speeds adjustment.
Rg’
VCC
Pin 8. VCC (Controller Supply). This pin supplies
the signal part of the IC. The device is enabled as
VCC voltage exceeds the start threshold and
works as long as the voltage is above the UVLO
threshold. Otherwise the device is shut down and
the current consumption is extremely low
(<150µA). This is particularly useful for reducing
the consumption of the start-up circuit (in the simplest case, just one resistor), which is one of the
most significant contributions to power losses in
standby.
An internal Zener limits the voltage on VCC to
25V. The IC current consumption increases considerably if this limit is exceeded.
A small film capacitor between this pin and SGND
(pin 12), placed as close as possible to the IC, is
recommended to filter high frequency noise.
Pin 9. VC (Supply of the Power Stage). It supplies
the driver of the external switch and therefore absorbs a pulsed current. Thus it is recommended to
place a buffer capacitor (towards PGND, pin 11,
as close as possible to the IC) able to sustain
these current pulses and in order to avoid them
inducing disturbances.
This pin can be connected to the buffer capacitor
directly or through a resistor, as shown in fig. 26,
to control separately the turn-on and turn-off
speed of the external switch, typically a Power-
Rg(ON)=Rg+Rg’
Rg(OFF)=Rg
VC
9
8
13V
10
DRIVE &
CONTROL
OUT
L5991
D97IN726
Rg
11
PGND
Pin 10. OUT (Driver Output). This pin is the output of the driver stage of the external power
switch. Usually, this will be a PowerMOS, although the driver is powerful enough to drive
BJT’s (1.6A source, 2A sink, peak).
The driver is made up of a totem pole with a highside NPN Darlington and a low-side VDMOS, thus
there is no need of an external diode clamp to
prevent voltage from going below ground. An internal clamp limits the voltage delivered to the
gate at 13V. Thus it is possible to supply the
driver (Pin 9) with higher voltages without any risk
of damage for the gate oxide of the external MOS.
The clamp does not cause any additional increase of power dissipation inside the chip since
the current peak of the gate charge occurs when
the gate voltage is few volts and the clamp is not
active. Besides, no current flows when the gate
voltage is 13V, steady state.
Under UVLO conditions an internal circuit (shown
Figure 25. Hiccup mode operation.
IOUT
SHORT
ISEN
FAULT
SS
5V
7V
0.5V
Thic
D98IN986
time
11/23
L5991 - L5991A
in fig.27) holds the pin low in order to ensure that
the external MOS cannot be turned on accidentally. The peculiarity of this circuit is its ability to
mantain the same sink capability (typically, 20mA
@ 1V) from VCC = 0V up to the start-up threshold.
When the threshold is exceeded and the L5991
starts operating, V REFOK is pulled high (refer to fig.
27) and the circuit is disabled.
It is then possible to omit the ”bleeder” resistor
(connected between the gate and the source of
the MOS) ordinarily used to prevent undesired
switching-on of the external MOS because of
some leakage current.
Pin 13. ISEN (Current Sense). This pin is to be
connected to the ”hot” lead of the current sense
resistor Rsense (being the other one grounded), to
get a voltage ramp which is an image of the current of the switch (IQ). When this voltage is equal
to:
V13pk = IQpk ⋅ Rsense =
VCOMP − 1.4
(9)
3
the conduction of the switch is terminated.
To increase the noise immunity, a ”Leading Edge
Blanking” of about 100ns is internally realized as
shown in fig. 28. Because of that, the smoothing
RC filter between this pin and Rsense could be removed or, at least, considerably reduced.
Figure 27. Pull-Down of the output in UVLO.
OUT
10
Pin 14. DIS (Device Disable). When the voltage
on pin 14 rises above 2.5V the IC is shut down
and it is necessary to pull VCC (IC supply voltage,
pin 8) below the UVLO threshold to allow the device to restart.
The pin can be driven by an external logic signal
in case of power management, as shown in fig.
29. It is also possible to realize an overvoltage
protection, as shown in the section ” Application
Ideas”.If used, bypass this pin to ground with a filter capacitor to avoid spurious activation due to
noise spikes. If not, it must be connected to
SGND.
VREFOK
12
SGND
D97IN538
Pin 11. PGND (Power Ground). The current loop
during the discharge of the gate of the external
MOS is closed through this pin. This loop should
be as short as possible to reduce EMI and run
separately from signal currents return.
Pin 15. DC-LIM (Maximum Duty Cycle Limit). The
upper extreme, Dx, of the duty cycle range depends on the voltage applied to this pin. Approximately,
Pin 12. SGND (Signal Ground). This ground references the control circuitry of the IC, so all the
ground connections of the external parts related
to control functions must lead to this pin. In laying
out the PCB, care must be taken in preventing
switched high currents from flowing through the
SGND path.
Dx ≅
RT
(10)
RT + 230
if DC-LIM is grounded or left floating. Instead,
Figure 28. Internal LEB.
2V
I
3V
+
0
CLK
ISEN
13
+
FROM E/A
PWM
COMPARATOR
TO PWM
LOGIC
-
TO FAULT
LOGIC
+
1.2V
12/23
-
OVERCURRENT
COMPARATOR
D97IN503
L5991 - L5991A
Figure 29. Disable (Latched).
and the output switching frequency will be halved
with respect to the oscillator one because an internal T flip-flop (see block diagram) is activated.
Fig. 30 shows the operation.
The half duty cycle option speeds up the discharge of the timing capacitor CT (in order to get
duty cycles as close to 50% as possible) so the
oscillator frequency - with the same timing components will be slightly higher.
DISABLE
SIGNAL
DIS
14
+
D
-
R
Q
DISABLE
C
Pin 16. S-BY (Standby Function). The resistor RB,
along with RA, sets the operating frequency of the
oscillator in normal operation (fosc). In fact, as long
as the STANDBY signal is high, the pin is internally connected to the reference voltage VREF by
a N-channel FET (see fig. 31), so the timing capacitor CT is charged through RA and RB. When
the STANDBY signal goes low the N-channel FET
is turned off and the pin becomes floating. RB is
2.5V
UVLO
D97IN502
connecting DC-LIM to VREF (half duty cycle option), Dx will be set approximately at:
RT
(11)
2 ⋅ RT + 260
Figure 30. Half duty cycle option.
Dx ≅
td
V15=GND
V5=V13=GND
V2
DX =
tc
tc + td
V10
tc
td
V15=VREF
V5=V13=GND
V2
DX =
tc
2 ·tc + td
V10
tc
D97IN498
Figure 31. Standby function internal schematic and operation.
ISEN
COMP
13
6
+
2R
R
-
OUT
DRIVER
R
FB
10V
5
2.5
-
+
+
2.5/4
VREF
STANDBY
LEVEL SHIFT
STANDBY BLOCK
STANDBY
4
HIGH
ST-BY
16
LOW
RB
2
RCT
RA
CT
VT1
2.5V
V T2
4V
VCOMP
D97IN752B
13/23
L5991 - L5991A
now disconnected and CT is charged through RA
only. In this way the oscillator frequency (fSB) will
be lower. Refer to pin 2 description to see how to
calculate the timing components.
Typical values for VT1 and VT2 are 2.5 V and 4V
respectively. This 1.5V hysteresis is enough to
prevent undesired frequency change up to a 5.5
to 1 fosc/ fSB ratio.
The value of VT1 is such that in a discontinuous
flyback the standby frequency is activated when
the input power is about 13% of the maximum. If
necessary, it is possible to decrease the power
threshold below 13% by adding a DC offset (Vo)
on the current sense pin (13, ISEN). This will also
allow a frequency change greater than 5.5 to 1.
The following equations,useful for design, apply:
PinSB =
 0.367 − Vo 
1
⋅ LP ⋅ ƒ osc ⋅ 

2
 Rsense 
2
(12),
2
 0.867 − Vo 
1
PinNO = ⋅ LP ⋅ ƒ SB ⋅ 

2
 Rsense 
(13),
2
ƒ osc  0.867 − Vo 
<
ƒ SB  0.367 − Vo
(14),
where PinSB is the input power below which the
L5991 recognizes a light load and switches the
oscillator frequency from ƒ osc to fSB, PinNO is the
input power above which the L5991 switches
back from ƒ SB to ƒ osc and Lp the primary inductance of the flyback transformer.
Connect to Vref or leave open this pin when
stand-by function is not used.
14/23
Layout hints
Generally speaking a proper circuitboard layout is
vital for correct operation but is not an easy task.
Careful component placing, correct traces routing,
appropriate traces widths and, in case of high
voltages, compliance with isolation distances are
the major issues. The L5991 eases this task by
putting two pins at disposal for separate current
returns of bias (SGND) and switch drive currents
(PGND) The matter is complex and only few important points will be here reminded.
1) All current returns (signal ground, power
ground, shielding, etc.) should be routed separately and should be connected only at a single
ground point.
2) Noise coupling can be reduced by minimizing
the area circumscribed by current loops. This
applies particularly to loops where high pulsed
currents flow.
3) For high current paths, the traces should be
doubled on the other side of the PCB whenever
possible: this will reduce both the resistance
and the inductance of the wiring.
4) Magnetic field radiation (and stray inductance)
can be reduced by keeping all traces carrying
switched currents as short as possible.
5) In general, traces carrying signal currents
should run far from traces carrying pulsed currents or with quickly swinging voltages. From
this viewpoint, particular care should be taken
of the high impedance points (current sense input, feedback input, ...). It could be a good idea
to route signal traces on one PCB side and
power traces on the other side.
6) Provide adequate filtering of some crucial
points of the circuit, such as voltage references,
IC’s supply pins, etc.
88 to 270
VAC
C09 8.2nF
6800pF
R9
24K
R5
12K
5
7
16
2
4
Pin(W)
Pout(W)
14
3.10
2.95
2
110
L5991
16
3.90
220
2.2nF
R13 47K
C11
R03 47K
R01 3.3
9
4.40
270
6
11
12
13
10
8
R06 27
R12 330K
R04 47K
C03 220µF
400V
BD01
88
C02
0.1µF
VAC(V)
D06
1N4148
LF01
D05
1N4937
R18
47K
3W
C08
3.3nF
R21 100
C05
100pF
R11 1K
R08 22
C04 47µF
R10
0.22
D04 1N4148
R17
750K
R16
750K
8
3
7
Q51
TL431
4N35
R54
1K
Q01
STP6
NA60FI
R07 47
C10
10nF
100V
C54
220µF 100V
D53 BYT11-600
R58
4.7K
R53
4.7K
R52
47
C55
1000µF
16V
C61
0.056µF
R55
300K
VR51
100K
C58
47µF 25V
10 D56 BYW100-100
11
C56
470µF 25V
C57
470µF 25V
13
12 D55 BYW100-100
15
14 D54 BYW100-100
16
17
R19 4.7M R20 4.7M
18 D52 BYT13-800
1
R56
4.3K
C59
0.01µF
C52
100µF
250V
D97IN730A
C62
100µF 100V
-15V
5W
+15V
5W
6.3V
5W
GND
80V
10W
180V
65W
APPLICATION IDEAS
Here follows a series of ideas/suggestions aimed at
C06
C07 1µF
C01
0.1µF
F01 AC 250V T3.15A
C11 4700pF 4KV C12
L5991 - L5991A
either improving performance or solving common
application problems of L5991 based supplies.
Figure 32. Typical application circuit for computer monitors (90W).
15/23
16/23
47K
Pout(W)
85
0.90
Pin(W)
5.6K
5.6K
VAC(V)
330nF
3.3nF
22K
22V
C02
0.1 µF
0.55
7
1
220
1.14
16
2
3
4
5.6K
0.93
110
1.1M
1.1M
LF01
BC337
100nF
85 TO
C01
265 Vac 0.1µF
F01 AC 250V T1A
14
1.57
5
L5991
265
15
4.7K
BD01
6
11
12
13
10
9 8
22
33K
STK2N50
100µF
400V
2.2
D97IN618
470pF
470
470pF
1K
22
33µF/25V
BAT46
10K
1N4937
BZW06-154
220
TL431
4N35
0.47
1/2 W
STP4NA60
Naux
N1
4.7M
4700pF 4KV
1K
2.7K
N4
N3
N2
4.7M
BYW100-200
0.022 µF
BYW100-50
3.9K
470µF
16V
2 x 470µF
16V
BYW98-100
4700pF 4KV
5.1K
2 x 330µF
35V
270K
5V / 0.5A
GND
12V / 1.5A
28V / 0.7A
L5991 - L5991A
Figure 33. Typical application circuit for inkjet printers (40W).
L5991 - L5991A
Figure 34. Standby thresholds adjustment.
SGND
L5991
12
4
10
13
VREF
ISEN
R
RA
RSENSE
OPTIONAL
D97IN751A
Figure 35. Isolated MOSFET Drive & Current Transformer Sensing in 2-switch Topologies.
VIN
ISOLATION
BOUNDARY
VC
9
OUT
10
L5991
ISEN
13
12
PGND
11
SGND
D97IN761
Figure 36. Low consumption start-up.
VIN
2.2MΩ
33KΩ
STD1NB50-1
T
VCC
VREF
20V
47KΩ
4
SELF-SUPPLY
WINDING
8
L5991
12
11
D97IN762B
Figure 37. Bipolar transistor driver.
VIN
VCC
8
VC
9
10
13
L5991
OUT
ISEN
11
PGND
D97IN763
17/23
L5991 - L5991A
Figure 38. Typical E/A compensation networks.
+
2.5V
From VO
1.3mA
Ri
VFB
5
Rd
2R
+
EA
R
Rf
Cf
COMP
6
12
SGND
Error Amp compensation circuit for stabilizing any current-mode topology except
for boost and flyback converters operating with continuous inductor current.
From VO
+
2.5V
1.3mA
RP
Ri
CP
VFB
5
-
EA
R
Rf
Cf
Rd
2R
+
COMP
6
12
SGND
D97IN507
Error Amp compensation circuit for stabilizing current-mode boost and flyback
topologies operating with continuous inductor current.
Figure 39. Feedback with optocoupler.
VOUT
6
COMP
L5991
5
TL431
VFB
D97IN759
Figure 40. Slope compensation techniques.
ST-BY
VREF
RB
RSLOPE
4
RB
RA
RCT
I
ST-BY
V REF
16
2
ISEN
RSENSE
I
R
2
RSLOPE
CSLOPE
L5991
ISEN
12
SGND
OPTIONAL
RSENSE
13
L5991
12
12
SGND
13
ISEN
OPTIONAL
RSLOPE
RSENSE
SGND
OPTIONAL
D97IN760A
18/23
OUT
CT
L5991
13
10
RA
RCT
CT
16
4
L5991 - L5991A
Figure 41. Protection against overvoltage/feedback disconnection (latched)
RSTART
RSTART
VCC
DIS
VCC
VZ
8
8
DIS
L5991
14
L5991
14
12
11
SGND
12
2.2K
11
SGND
PGND
PGND
D98IN905
D97IN754
Figure 42 Protection against overvoltage/feedback disconnection (not latched)
Figure 43. Device shutdown on overcurrent
RSTART
Ipk max ≅
VREF
4
R1
VREF
DC
•
1-
R2
R1
Ipk
14
L5991
8
R2
L5991
3
I
DIS
VCC
4
2.5
R SENSE
11
12
PGND
11
12
ISEN
13
RSENSE
SGND
OPTIONAL
D97IN756A
D97IN755A
Figure 44. Constant power in pulse-by-pulse current limitation (flyback discontinuous)
VIN
80 ÷ 400VDC
Lp
RFF
6
OUT
RFF = 6·10
10
L5991
11
PGND
12
R·Lp
RSENSE
ISEN
13
R
RSENSE
SGND
D97IN757
Figure 45. Voltage mode operation.
DC
3
10K
COMP
L5991
6
SGND
12
13
ISEN
D97IN758A
19/23