L6180 L6181 OCTAL LINE RECEIVER ADVANCE DATA OCTAL LINE RECEIVER FOR: - EIA STD RS232D RS423A RS422A - CCIT V.10 V.11 V.28 X.26 NO EXTERNAL COMPONENTS INPUT FAIL SAFING CAPABILITY HIGH CROSSTALK REJECTION L6180 DATA RATE < 100KBIT/S L6181 DATA RATE < 1MBIT/S 50V EOS OUTPUT PROTECTION DESCRIPTION L6180/1 is an octal line receiver in a plastic DIP or PLCC designed to meet a wide range of digital communications requirements as outlined in the EIA standards RS232A without additional components, as well as the low speed applications of RS422A. DIP 28 PLCC 28 ORDERING NUMBER: L6180A DIP 28 L6180D PLCC28 L6181A DIP 28 L6181D PLCC28 The receiver meets the CCIT recommendations V.10, V.11, X.26 and V.28 low speed applications (below 100KBS). A low pass filter on the input starts to roll off at a frequency of 100KHz. BLOCK DIAGRAM October 1993 1/10 This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice. L6180 - L6181 ABSOLUTE MAXIMUM RATINGS Symbol Parameter Unit 7 V Supply Voltage VDD Supply Voltage 13.5 V VSS Logic Supply Voltage -13.5 V CRR Common Mode Range ±15 V VID Differential Input Voltage ±25 V Ptot Power Dissipation (PLCC 28) 800 mW Power Dissipation (DIP 28) 1200 mW IOS t Output Sink Current 50 mA Output Short Circuit Time 1 sec 0 to 70 °C -65 to 150 °C Top Operating Free Air Temperature Range Tstg Storage Temperature Range ESD 2KV max ESD 50µJ Input Transient Protection 50V min EOS 100µs PIN CONNECTIONS (Top views) DIP28 2/10 Value VCC PLCC28 L6180 - L6181 ELECTRICAL CHARACTERISTICS (VCC = 5V ±5%; VCM = -7 to 7V; Tamb = 0 to 70°C; VSS = -9 to 13.5V; VDD = 9 to 13.5V; unless otherwise specified.) Symbol VIN RI Parameter Input Current Input Resistance Test Condition Min. Typ. (See Fig.1 and note2) VCC = 0 to 5.25V; VSS, VDD = 0 to 13.5V VIN = - 10 to 10V VIN = - 15 to 15V VIA or VIB = 3 to 15V; (see fig.1) 3 Max. Unit ±3 ±4.25 mA mA 7 KΩ [(VIA or VIN) −VIOC] RI = IIN VFS Failsafe Output Voltage IO = -440µA (See Fig.3) 2.7 V VOH High Level Output Voltage VCC = 4.75V; VID = -1V; IOH = -440µA 2.7 V VOL Low Level Output Voltage VCC = 5.25V; VID = -1V; IOL = 2mA VIT2 VIOH Comparator Threshold Voltage (See Fig.4) 1.8 IIH2 High Operating Threshold Voltage VOL = 0.4V; IOL = 2mA; (See Fig.4) IIH1 Low Operating Threshold Voltage VOH = 2.7V; IO = -440µA (See Fig.4) VH 0.4 V 2.6 V -25 -75 mV -125 -175 mV Input Hysteresis Voltage |VTH2 - VTH1| VIOC1 Open Circuit Input Voltage Measured in accordance with V.28 and RS-232D (see note 4 and 7) VIOCH Open Circuit Input Voltage Measured in presence of AC Input Signal (see note 7) 3.5 IOS Open Short Circuit Current VCC = 5.25V; VO = 0; VID = 1V; (see note 5) 20 VIBV Input for Balance Test (see Figure 7 and note 11) CI 2.2 50 Input Capacitance 150 mV 0.6 2 V 4 4.5 V 100 mA 0.4 V 100 pF VCC Supply Current VCC = 4.75V to 5.25V; (see note 6) 100 mA Vdd Supply Current Vdd = 9 to 3.5V; (see note 6) 30 mA VSS Supplyt Current VSS = -9 to 13.5V; (see note 6) 30 mA IOS Open Short Circuit Current VCC = 5.25V; VO = 0; VID = 1V; (see note 5) 20 100 mA Tplh Propagation Delay Low to High R L = 390Ω; CL = 50pF; |VIN = 1V|; (see fig 5 test Circuit Fig. 6) 0 1500 ns Tphl Propagation Delay Low to High R L = 390Ω; CL = 50pF; |VIN = 1V|; (see fig 5 test Circuit Fig. 6) 0 1500 ns VIOCH Delay VIOCL to VIOCH Switching (see note 7A) 5 ms VIOCL Delay VIOCH to VIOCL Switching (see note 7B) |Tplh - Tphl| R L = 390Ω; CL = 50pF; |VIN| = 1V;(see fig. 5; Test Circuit Fig. 6) 0 500 ns Skew between rec’s in PKg Tp (1) hl/1h - Tp (2) hl/1h R L = 390Ω; CL = 50pF; |VIN| = 1V;(see fig. 5; Test Circuit Fig. 6) 0 300 ns Frequency Accepted (Receiver will Output) VIN = 200mVpp; (see fig. 8 and note 7; Vist TSKEW1 fA 200 100 ms KHz 3/10 L6180 - L6181 ELECTRICAL CHARACTERISTICS (VCC = 5V ±5%; VCM = -7 to 7V; Tamb = 0 to 70°C; VSS = -9 to 13.5V; VDD = 9 to 13.5V; unless otherwise specified.) Symbol fR Parameter Frequency Rejected (No Receiver Output) Test Condition Min. VIN = 2Vpp; (see fig. 8 and note 7) Typ. Max. 5 Unit MHz Note: 1) The algebric convention, where the less positive (more negative) is designed the minimum 2) With the voltage VIA or (VIB) ranging between ±15V, while VIB or (VIA) is open or grounded, the resultant input current IIA or (IIB) shall remain within the shaded region shown in the graph in Fig.1. 3) Either Point B’ or Point A’ is grounded in Figure 1 4) VICC measured from grounded to (+) input with (-) input grounded VICC measured from grounded to (+) input with (-) input grounded 5) Not more than one output should be shorted at a time and for less than 1 seond 6) The sum of the product of the maximum supply currents and voltages cannot exceed themaximum power dissipation 7) A: The conditions for the inpit switching from VIOCL to VIOCH mode is: Vid in start bit ”spacing condition”for less than TpVioch (5ms). B: The conditions for the input switching from VIOCH to VIOCL mode is: Vid > WW2 for greater than TpVIOCL (200ms) 8) An example of a frequency response plot meeting the rejection/acceptance requirements is provided in figure 8. LINE TRANSIENT IMMUNITY (Considering the following cases; powered ON, Powered OFF-LOW impedance power supply and powered OFF-HIGH impedance supply) Symbol Parameter Test Condition Min. Typ. Max. Static tested per MIL-STD-883 (see note 9) 2 KV EOS Stress transient pulse both polarities for 100µs (see note 9 and Fig. 2) 50 V Note: 9) All pins are required to withstand this parameters. 10) Input pins are required to withstand fig.2 without any degradation to the circuit. 11) The balance test requirement can be met by use of a current limit circuit which reduces the input bias current Iib (see figure 7) for input voltages below a threshold voltage given by (Iib x 1K) - 400mV. Figure 1: Input Current Voltage Mesurements 4/10 Unit ESD L6180 - L6181 Figure 2: EOS Requiremets Figure 3: Output Failsafing The output assumes a logic ”1”under the following conditions, (see figure 3) 1 Both inputs open 2 Both inputs shorted 3 Signal Opencircuit 3a Common grounded, signal open circuit 4 Common open, generator powered-on 5 Generatorpowered-down (see note 7) 6 Common open, generator powered-down 6a Signal grounded, common open, generator powered-down 7 Less than 250mVpp differential signal 5/10 L6180 - L6181 Figure 4: Threshold voltage definition Figure 5: PropagationDelay Figure 6: AC Test Circuit 6/10 L6180 - L6181 Figure 7: Receiver input Balance Measurement Figure 8: High Frequency Signal Rejection INPUT BALANCE MEASUREMENT The balance of the receiver input voltage-current characteristics and bias voltages shall be such that the receiver will remain in the intended binary state when a differential voltage Vi of 400mV is applied through 500Ω ±1% to each input terminal, as shown above, and Vcm is varied between -7 and +7V. When the polarity of Vi is reversed, the opposite binary state shall be maintained under the same conditions. Maintain input balance with input B common with another receiver. The voltage input (VIN) rejection is checked at the center point between the High Operating Threshold (Vth2) and the Low OperatingThreshold (Vth1) 7/10 L6180 - L6181 PLCC28 PACKAGE MECHANICAL DATA mm DIM. MIN. TYP. MAX. MIN. TYP. MAX. A 12.32 12.57 0.485 0.495 B 11.43 11.58 0.450 0.456 D 4.2 4.57 0.165 0.180 D1 2.29 3.04 0.090 0.120 D2 0.51 E 9.91 0.020 10.92 0.390 0.430 e 1.27 0.050 e3 7.62 0.300 F 0.46 0.018 F1 0.71 0.028 G 8/10 inch 0.101 0.004 M 1.24 0.049 M1 1.143 0.045 L6180 - L6181 DIP28 PACKAGE MECHANICAL DATA mm DIM. MIN. TYP. inch MAX. MIN. TYP. a1 0.63 0.025 b 0.45 0.018 b1 0.23 b2 0.31 1.27 D E 0.009 0.012 0.050 37.34 15.2 16.68 1.470 0.598 0.657 e 2.54 0.100 e3 33.02 1.300 F MAX. 14.1 0.555 I 4.445 0.175 L 3.3 0.130 9/10 L6180 - L6181 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. 1995 SGS-THOMSON Microelectronics - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands - Singapore - 10/10