L6911E 5-Bit programmable step down controller with synchronous rectification Features ■ Operating supply IC voltage from 5V to 12V buses ■ Up to 1.3A gate current capability ■ TTL-compatible 5 bit programmable output compliant with VRM 8.5 : 1.050V to 1.825V with 0.025V binary steps ■ Voltage mode PWM control ■ Excellent output accuracy: ±1% over line and temperature variations ■ Very fast load transient response: from 0% to 100% Duty Cycle ■ Power good output voltage ■ Overvoltage protection and monitor ■ Overcurrent protection realized using the upper MOSFET's Rds(ON) ■ 200kHz internal oscillator ■ Oscillator externally adjustable from 50kHz to 1MHz ■ Soft start and inhibit functions Applications ■ Power supply for advanced microprocessor core ■ Distributed power supply SO-20 Description The device is a power supply controller specifically designed to provide a high performance DC/DC conversion for high current microprocessors. A precise 5 bit digital to analog converter (DAC) allows to adjust the output voltage from 1.050 to 1.825 with 25mV binary steps. The high precision internal reference assures the selected output voltage to be within ±1%. The high peak current gate drive affords to have fast switching to the external power mos providing low switching losses. The device assures a fast protection against load overcurrent and load over-voltage. An external SCR is triggered to crowbar the input supply in case of hard overvoltage. An internal crowbar is also provided turning on the low side mosfet as long as the over-voltage is detected. In case of over-current detection, the soft start capacitor is discharged an the system works in HICCUP mode. Table 1. Device summary April 2007 Part Number Package Packaging L6911E TSSOP8 Tube L6911ETR TSSOP8 Tape and reel Rev 3 1/34 www.st.com 34 Contents L6911E Contents 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 4 2.1 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.1 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.1 5 6 2/34 VID Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.1 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.2 Digital to analog converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.3 Soft start and inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.4 Driver section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.5 Monitor and protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.6 Inductor design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.7 Output capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.8 Input capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.9 Compensation network design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 VRM demo board description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.1 Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.2 Inductor design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.3 Output capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.4 Input capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.5 Over-current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 L6911E Contents 7 Connector pin orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8 PCB and components layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 9 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3/34 Block diagram 1 L6911E Block diagram Figure 1. Block diagram Vcc 5V to12V Vin 5V to12V VCC PGOOD OCSET BOOT SS MONITOR and PROTECTION UGATE OVP RT PHASE OSC LGATE VD0 VD1 VD2 VD3 VD4 PGND - D/A + + - D98IN957 4/34 E/A COMP GND PWM VSEN VFB Vo 1.050V to 1.825V L6911E Pin settings 2 Pin settings 2.1 Pin connection Figure 2. Pin connection (top view) VSEN 1 20 RT OCSET 2 19 OVP SS/INH 3 18 VCC VID0 4 17 LGATE VID1 5 16 PGND VID2 6 15 BOOT VID3 7 14 UGATE VID4 8 13 PHASE COMP 9 12 PGOOD 10 11 GND FB D98IN958 2.2 Pin description Table 2. Pin description N° Name Description 1 VSEN Connected to the output voltage is able to manage over-voltage conditions and the PGOOD signal. 2 OCSET A resistor connected from this pin and the upper Mos Drain sets the current limit protection. The internal 200µA current generator sinks a current from the drain through the external resistor. The Over-Current threshold is due to the following equation: I OCSET Þ R OCSET I P = ----------------------------------------------R DSon SS/INH The soft start time is programmed connecting an external capacitor from this pin and GND. The internal current generator forces through the capacitor 10µA. This pin can be used to disable the device forcing a voltage lower than 0.4V 4-8 VID0 - 4 Voltage Identification Code pins. These input are internally pulled-up and TTL compatible. They are used to program the output voltage as specified in Table 6 on page 9 and to set the overvoltage and power good thresholds. Connect to GND to program a ‘0’ while leave floating to program a ‘1’. 9 COMP This pin is connected to the error amplifier output and is used to compensate the voltage control feedback loop. 10 FB 3 This pin is connected to the error amplifier inverting input and is used to compensate the voltage control feedback loop. 5/34 Pin settings L6911E Table 2. Pin description (continued) N° Name Description 11 GND All the internal references are referred to this pin. Connect it to the PCB signal ground. 12 PGOOD This pin is an open collector output and is pulled low if the output voltage is not within the above specified threshlds. If not used may be left floating. 13 PHASE This pin is connected to the source of the upper mosfet and provides the return path for the high side driver. This pin monitors the drop across the upper mosfet for the current limit. 14 UGATE High side gate driver output. 15 BOOT Bootstrap capacitor pin. Through this pin is supplied the high side driver and the upper mosfet. Connect through a capacitor to the PHASE pin and through a diode to Vcc (catode vs boot). 16 PGND Power ground pin. This pin has to be connected closely to the low side mosfet source in order to reduce the noise injection into the device 17 LGATE This pin is the lower mosfet gate driver output 18 VCC Device supply voltage. The operative supply voltage range is from 4.5 to 12V. DO NOT CONNECT VIN to 12V if VCC IS 5V. OVP Over voltage protection. If the output voltage reach the 15% above the programmed voltage this pin is driven high and can be used to drive an external SCR that crowbar the supply voltage. If not used, it may be left floating. 19 Oscillator switching frequency pin. Connecting an external resistor from this pin to GND, the external frequency is increased according to the equation: 6 5 ⋅ 10 f S = 200kHz + ------------------R T ( kΩ ) 20 RT Connecting a resistor from this pin to Vcc (12V), the switching frequency is reduced according to the equation: 7 4 ⋅ 10 f S = 200kHz – ------------------R T ( kΩ ) If the pin is not connected, the switching frequency is 200KHz. The voltage at this pin is fixed at 1.23V. Forcing a 50µA current into this pin, the built in oscillator stops to switch. 6/34 L6911E Electrical data 3 Electrical data 3.1 Maximum ratings Table 3. Absolute maximum ratings Parameter (1) Symbol Value Unit 15 V VBOOT-VPHASE Boot Voltage 15 V VHGATE-VPHASE 15 V -0.3 to Vcc+0.3 V 7 V 6.5 V Vcc Vcc to GND, PGND OCSET, PHASE, LGATE ROSC, SS, FB, PGOOD, VSEN COMP, OVP 1. ESD immunity for pins 2 to 9 and 18 to 20 is guaranteed up to 1500V (Human Body Model). 3.2 Thermal data Table 4. Thermal data Symbol Parameter Value Unit RthJA Thermal resistance junction to ambient 110 °C/W Tmax Maximum junction temperature 150 °C TSTG Storage temperature range -40 to 150 °C TJ Junction temperature range 0 to 125 °C 7/34 Electrical characteristics 4 L6911E Electrical characteristics Table 5. Electrical characteristic (VCC = 12V; TA = 25°C unless otherwise specified) Symbol Parameter Test condition Min Typ Max Unit VCC supply current Icc Vcc supply current UGATE and LGATE open Turn-On VCC threshold VOCSET = 4.5V Turn-Off VCC threshold VOCSET = 4.5V 5 mA Power-ON 4.6 3.6 Rising VOCSET threshold ISS Soft start current V V 1.26 V 10 µA Oscillator ∆VOSC Free running frequency RT = OPEN 180 Total Variation 6 KΩ < RT to GND < 200 KΩ -15 Ramp amplitude RT = OPEN 200 220 kHz 15 % 1.9 Vp-p Reference and DAC DACOUT voltage accuracy VID0, VID1,VID2, VID3, VID25mV see Table 6 on page 9; TA = 0 to 70°C -1 VID Pull-Up voltage 1 % 3.1 V DC gain 88 dB Gain-bandwidth product 15 MHz 10 V/µS 1.3 A Error amplifier GBWP SR Slew-rate COMP = 10pF Gate drivers IUGATE High side source current VBOOT - VPHASE = 12V, VUGATE - VPHASE = 6V 1 RUGATE High side sink resistance VBOOT - VPHASE = 12V, IUGATE = 300mA ILGATE Low side source current VCC = 12V, VLGATE = 6V RLGATE Low side sink resistance Vcc=12V, ILGATE = 300mA 1.5 Output driver dead time PHASE connected to GND 120 Over voltage trip (VSEN/DACOUT) VSEN rising 117 120 % OCSET current source VOCSET = 4.5V 200 230 µA 2 0.9 4 1.1 Ω A 3 Ω nS Protections IOCSET 8/34 170 L6911E Electrical characteristics Table 5. Electrical characteristic (VCC = 12V; TA = 25°C unless otherwise specified) (continued) Symbol IOVP Parameter Test condition OVP sourcing current Min Typ Max Unit VSEN > OVP trip, VOVP = 0V 60 mA Upper threshold (VSEN/DACOUT) VSEN rising 108 110 112 % Lower threshold (VSEN/DACOUT) VSEN falling 88 90 92 % Hysteresis (VSEN/DACOUT) Upper and lower threshold PGOOD voltage low IPGOOD = -5mA Power GOOD VPGOOD 4.1 2 % 0.5 V VID Setting Table 6. VID Setting VID4 (25mV) VID3 VID2 VID1 VID0 Output Voltage (V) VID4 (25mV) VID3 VID2 VID1 VID0 Output Voltage (V) 0 0 1 0 0 1.050 0 1 1 0 0 1.450 1 0 1 0 0 1.075 1 1 1 0 0 1.475 0 0 0 1 1 1.100 0 1 0 1 1 1.500 1 0 0 1 1 1.125 1 1 0 1 1 1.525 0 0 0 1 0 1.150 0 1 0 1 0 1.550 1 0 0 1 0 1.175 1 1 0 1 0 1.575 0 0 0 0 1 1.200 0 1 0 0 1 1.600 1 0 0 0 1 1.225 1 1 0 0 1 1.625 0 0 0 0 0 1.250 0 1 0 0 0 1.650 1 0 0 0 0 1.275 1 1 0 0 0 1.675 0 1 1 1 1 1.300 0 0 1 1 1 1.700 1 1 1 1 1 1.325 1 0 1 1 1 1.725 0 1 1 1 0 1.350 0 0 1 1 0 1.750 1 1 1 1 0 1.375 1 0 1 1 0 1.775 0 1 1 0 1 1.400 0 0 1 0 1 1.800 1 1 1 0 1 1.425 1 0 1 0 1 1.825 9/34 Device description 5 L6911E Device description The device is an integrated circuit realized in BCD technology. It provides complete control logic and protections for a high performance step-down DC-DC converter optimized for microprocessor power supply. It is designed to drive N Channel Mosfets in a synchronousrectified buck topology. The device works properly with Vcc ranging from 5V to 12V and regulates the output voltage starting from a 1.26V power stage supply voltage (Vin). The output voltage of the converter can be precisely regulated, programming the VID pins, from 1.050V to 1.825V with 25mV binary steps, with a maximum tolerance of ±1% over temperature and line voltage variations. The device provides voltage-mode control with fast transient response. It includes a 200kHz free-running oscillator that is adjustable from 50kHz to 1MHz. The error amplifier features a 15MHz gain-bandwidth product and 10V/ms slew rate which permits high converter bandwidth for fast transient performance. The resulting PWM duty cycle ranges from 0% to 100%. The device protects against overcurrent conditions entering in HICCUP mode. The device monitors the current by using the rds(ON) of the upper MOSFET which eliminates the need for a current sensing resistor. The device is available in SO20 package. 5.1 Oscillator The switching frequency is internally fixed to 200kHz. The internal oscillator generates the triangular waveform for the PWM charging and discharging with a constant current an internal capacitor. The current delivered to the oscillator is tipically 50µA (FSW = 200KHz) and may be varied using an external resistor (RT) connected between RT pin and GND or VCC. Since the RT pin is maintained at fixed voltage (typ. 1.235V), the frequency is varied proportionally to the current sinked (forced) from (into) the pin. In particular connecting it to GND the frequency is increased (current is sinked from the pin), according to the following relationship: Equation 1 6 4.94 ⋅ 10 f S = 200kHz + -----------------------R T ( kΩ ) 10/34 L6911E Device description Connecting RT to VCC = 12V or to VCC = 5V the frequency is reduced (current is forced into the pin), according to the following relationships: Equation 2 7 4.306 ⋅ 10 f S = 200kHz + ---------------------------R T ( kΩ ) VCC = 12V Equation 3 7 15 ⋅ 10 f S = 200kHz + ------------------R T ( kΩ ) VCC = 5V Switching frequency variations vs. RT are reported in Figure 3 on page 11. That forcing a 50µA current into this pin, the device stops switching because no current is delivered to the oscillator. Figure 3. Switching frequency variations vs. RT 10000 1000 Resistance [kOhm] Note: 100 10 RT to GND RT to VCC=12V RT to VCC=5V 10 100 1000 Frequency [kHz] 11/34 Device description 5.2 L6911E Digital to analog converter The built-in digital to analog converter allows the adjustment of the output voltage from 1.050V to 1.825V with 25mV binary steps as shown in the previous Table 6: VID Setting on page 9. The internal reference is trimmed to ensure the precision of 1%. The internal reference voltage for the regulation is programmed by the voltage identification (VID) pins. These are TTL compatible inputs of an internal DAC that is realised by means of a series of resistors rpoviding a partition of the internal voltage reference. The VID code drives a multiplexer that selects a voltage on a precise point of the divider. The DAC output is delivered to an amplifier obtaining the VPROG voltage reference (i.e. the set-point of the error amplifier). Internal pull-ups are provided (realized with a 5µA current generator); in this way, to program a logic "1" it is enough to leave the pin floating, while to program a logic "0" it is enough to short the pin to GND. The voltage identification (VID) pin configuration also sets the power-good thresholds (PGOOD) and the over- voltage protection (OVP) thresholds. 5.3 Soft start and inhibit At start-up a ramp is generated charging the external capacitor CSS by means of a 10µA constant current, as shown in Figure 4 on page 13 When the voltage across the soft start capacitor (VSS) reaches 0.5V the lower power MOS is turned on to discharge the output capacitor. As VSS reaches 1V (i.e. the oscillator triangular wave inferior limit) also the upper MOS begins to switch and the output voltage starts to increase. The VSS growing voltage initially clamps the output of the error amplifier, and consequently VOUT linearly increases, as shown in Figure 4 on page 13. In this phase the system works in open loop. When VSS is equal to VCOMP the clamp on the output of the error amplifier is released. In any case another clamp on the non-inverting input of the error amplifier remains active, allowing to VOUT to grow with a lower slope (i.e. the slope of the VSS voltage, see Figure 4 on page 13). In this second phase the system works in closed loop with a growing reference. As the output voltage reaches the desired value VPROG, also the clamp on the error amplifier input is removed, and the soft start finishes. Vss increases until a maximum value of about 4V. The Soft-Start will not take place, and the relative pin is internally shorted to GND, if both VCC and OCSET pins are not above their own Turn-On thresholds; in this way the device starts switching only if both the power supplies are present. During normal operation, if any under-voltage is detected on one of the two supplies, the SS pin is internally shorted to GND and so the SS capacitor is rapidly discharged. The device goes in INHIBIT state forcing SS pin below 0.4V. In this condition both external MOSFETS are kept OFF. 12/34 L6911E Device description Figure 4. Soft start Vcc Turn-on threshold Vcc Vin Vin Turn-on threshold 1V Vss to GND 0.5V LGATE Vout Timing diagram 5.4 Aquisition: CH1 = PHASE; CH2 = VOUT; CH3 = PGOOD; CH4 = VSS CH3 = PGOOD; CH4 = VSS Driver section The driver capability on the high and low side drivers allows to use different types of power MOS (also multiple MOS to reduce the Rds(ON)), maintaining fast switching transition. The low-side mos driver is supplied directly by Vcc while the high-side driver is supplied by the BOOT pin. Adaptative dead time control is implemented to prevent cross-conduction and allow to use many kinds of mosfets. The upper mos turn-on is avoided if the lower gate is over about 200mV while the lower mos turn-on is avoided if the PHASE pin is over about 500mV. The upper mos is in any case turned-on after 200nS from the low side turn-off. The peak current is shown for both the upper (Figure 5 on page 14) and the lowr (Figure 6 on page 14) driver at 5V and 12V. a 4nF capacitive load has been used in these measurements. For the lower driver, the source peak current is 1.1A @ VCC = 12V and 500mA @ VCC = 5V, and the sink peak current is 1.3A @ VCC = 12V and 500mA @ VCC = 5V. Similary, for the upper driver, the source peak current is 1.3A @ Vboot-Vphase = 12V and 600mA @ Vboot-Vphase = 5V, and the sink peak current is 1.3A @ Vboot-Vphase = 12V and 550mA @ Vboot-Vphase = 5V. 13/34 Device description 14/34 L6911E Figure 5. High side driver peak current, Vboot-Vphase=12V (left) Vboot-Vphase=5V (right) CH1 = High Side Gate CH4 = inductor current Figure 6. Low side driver peak current, VCC=12V (left) VCC=5V (right)CH1 = Low side gate CH4 = inductor current L6911E 5.5 Device description Monitor and protection The output voltage is monitored by means of pin 1 (VSEN). If it is not within ±10% (typ.) of the programmed value, the powergood output is forced low. The device provides overvoltage protection, when the output voltage reaches a value 17% (typ.) greater than the nominal one. If the output voltage exceed this threshold, the OVP pin is forced high (5V) and the lower driver is turned on as long as the over-voltage is detected. The OVP pin is capable to deliver up to 60mA (min) in order to trigger an external SCR connected to burn the input fuse. The low-side mosfet turn-on implement this function when the SCR is not used and helps in keeping the ouput low. To perform the overcurrent protection the device compares the drop across the high side MOS, due to its RDSON, with the voltage across the external resistor (ROCS) connected between the OCSET pin and drain of the upper MOS. Thus the overcurrent threshold (IP) can be calculated with the following relationship: Equation 4 I OCS ⋅ R OCS I P = ------------------------------R DSON where the typical value of IOCS is 200µA. To calculate the ROCS value it must be considered the maximum RDSON (also the variation with temperature) and the minimum value of IOCS. To avoid undesirable trigger of overcurrent protection this relationship must be satisfied: Equation 5 ∆l I P ≥ I OUTMAX + ----- = I PEAK 2 where ∆I is the inductance ripple current and IOUTMAX is the maximum output current. In case of output short circuit the soft start capacitor is discharged with constant current (10µA typ.) and when the SS pin reaches 0.5V the soft start phase is restarted. During the soft start the over-current protection is always active and if such kind of event occours, the device turns off both mosfets, and the SS capacitor is dicharged again after reaching the upper threshold of about 4V. The system is now working in HICCUP mode, as shown in Figure 7 on page 16 a. After removing the cause of the over-current, the device restart working normally without power supplies turn off and on. 15/34 Device description Figure 7. L6911E Hiccup mode and Inductor ripple current vs. VOUT 9 L=1.5µH, Vin=12V Inductor Ripple [A] 8 7 L=2µH, Vin=12V 6 L=3µH, Vin=12V 5 4 L=1.5µH, Vin=5V 3 L=2µH, Vin=5V 2 L=3µH, Vin=5V 1 0 0.5 1.5 2.5 3.5 Output V oltage [V ] a) 5.6 b) Inductor design The inductance value is defined by a compromise between the transient response time, the efficiency, the cost and the size. The inductor has to be calculated to sustain the output and the input voltage variation to maintain the ripple current ∆IL between 20% and 30% of the maximum output current. The inductance value can be calculated with this relationship: Equation 6 V IN – V OUT V OUT L = ------------------------------ ⋅ -------------f s ⋅ ∆I L V IN Where fSW is the switching frequency, VIN is the input voltage and VOUT is the output voltage. Figure 7 b shows the ripple current vs. the output voltage for different values of the inductor, with vin = 5V and Vin = 12V. Increasing the value of the inductance reduces the ripple current but, at the same time, reduces the converter response time to a load transient. If the compensation network is well designed, the device is able to open or close the duty cycle up to 100% or down to 0%. The response time is now the time required by the inductor to change its current from initial to final value. Since the inductor has not finished its charging time, the output current is supplied by the output capacitors. Minimizing the response time can minimize the output capacitance required. The response time to a load transient is different for the application or the removal of the load: if during the application of the load the inductor is charged by a voltage equal to the difference between the input and the output voltage, during the removal it is discharged only by the output voltage. The following expressions give approximate response time for ∆I load transient in case of enough fast compensation network response: 16/34 L6911E Device description Equation 7 L ⋅ ∆I t application = ----------------------------V IN – V OUT Equation 8 L ⋅ ∆I t removal = -------------V OUT The worst condition depends on the input voltage available and the output voltage selected. Anyway the worst case is the response time after removal of the load with the minimum output voltage programmed and the maximum input voltage available. 5.7 Output capacitor Since the microprocessors require a current variation beyond 10A doing load transients, with a slope in the range of tenth A/µsec, the output capacitor is a basic component for the fast response of the power supply. In fact for first few microseconds they supply the current to the load. The controller recognizes immediately the load transient and sets the duty cycle at 100%, but the current slope is limited by the inductor value. The output voltage has a first drop due to the current variation inside the capacitor (neglecting the effect of the ESL): Equation 9 ∆VOUT = ∆IOUT · ESR A minimum capacitor value is required to sustain the current during the load transient without discharge it. The voltage drop due to the output capacitor discharge is given by the following equation: Equation 10 2 ∆I OUT L ∆V OUT = ------------------------------------------------------------------------------------------2 ⋅ C OUT ⋅ ( V INMIN ⋅ D MAX – V OUT ) Where DMAX is the maximum duty cycle value that is 100%. The lower is the ESR, the lower is the output drop during load transient and the lower is the output voltage static ripple. 17/34 Device description 5.8 L6911E Input capacitor The input capacitor has to sustain the ripple current produced during the on time of the upper MOS, so it must have a low ESR to minimize the losses. The rms value of this ripple is: Equation 11 I rms = I OUT D ⋅ ( 1 – D ) Where D is the duty cycle. The equation reaches its maximum value with D = 0.5. The losses in worst case are: Equation 12 2 P = ESR ⋅ I rms 5.9 Compensation network design The control loop is a voltage mode (Figure 9 on page 19) that uses a droop function to satisfy the requirements for a VRM module, reducing the size and the cost of the output capacitor. This method "recovers" part of the drop due to the output capacitor ESR in the load transient, introducing a dependence of the output voltage on the load current: at light load the output voltage will be higher than the nominal level, while at high load the output voltage will be lower than the nominal value. Figure 8. 18/34 Output transient response without (a) and with (b) the droop function L6911E Device description As shown in Figure 8 on page 18, the ESR drop is present in any case, but using the droop function the total deviation of the output voltage is minimized. In practice the droop function introduces a static error (Vdroop in Figure 8 on page 18) proportional to the output current. Since a sense resistor is not present, the output DC current is measured by using the intrinsic resistance of the inductance (a few mΩ). So the low-pass filtered inductor voltage (that is the inductor current) is added to the feedback signal, implementing the droop function in a simple way. Referring to the schematic in Figure 9, the static characteristic of the closed loop system is: Equation 13 R3 + R8 // R9 R L ⋅ R8 // R9 V OUT = V PROG + V PROG ⋅ ------------------------------------- – ---------------------------------- ⋅ I OUT R8 R2 Where VPROG is the output voltage of the digital to analog converter (i.e. the set point) and RL is the inductance resistance. The second term of the equation allows a positive offset at zero load (∆V+); the third term introduces the droop effect (∆VDROOP). Note that the droop effect is equal the ESR drop if: Equation 14 R L ⋅ R8 // R9 --------------------------------- = ESR R8 Figure 9. Compensation network V V IN V COMP L2 PHASE R L V OUT PW M ESR R8 C18 ZF C 6 -1 5 C 20 R4 R9 C 25 R3 V ZI PROG R2 19/34 Device description L6911E Considering the previous relationships R2, R3, R8 and R9 may be determined in order to obtain the desired droop effect as follow: ● Choose a value for R2 in the range of hundreds of KΩ to obtain realistic values for the other components. ● From the above equations, it results: Equation 15 + ∆V ⋅ R2 R L ⋅ I MAX R8 = ----------------------- ⋅ -------------------------V PROG ∆V DROOP Equation 16 ∆V DROOP 1 R9 = R8 ⋅ -------------------------- ⋅ -----------------------------------R L ⋅ I MAX ∆V DROOP 1 + -------------------------R L ⋅ I MAX Where IMAX is the maximum output current. ● The component R3 must be chosen in order to obtain R3 << R8//R9 to permit these and successive simplifications. Therefore, with the droop function the output voltage decreases as the load current increases, so the DC output impedance is equal to a resistance ROUT. It is easy to verify that the output voltage deviation under load transient is minimum when the output impedance is constant with frequency. 20/34 L6911E Device description To choose the other components of the compensation network, the transfer function of the voltage loop is considered. To simplify the analysis is supposed that R3 << Rd, where Rd = (R8//R9). Figure 10. Compensation network definition |A v | 2 fLC fC E f2 f1 fEC fC C f |R | R0 fD f3 f |G lo o p | G0 fc f ConverterS ingularity fCE = 1 / 2π ⋅ ESR ⋅ C OUT ESRzero f1 = 1 / 2π ⋅ R 4 ⋅ C 20 f 2 = 1 / 2π ⋅ ( R 3 + R 4 ) ⋅ C 20 = 1 / 2π ⋅ ESR ⋅ Cceramic f EC Introduced by f3 = 1 / 2π ⋅ R 3 ⋅ C 25 = 1 / 2π ⋅ Rceramic ⋅ Cceramic f CC CeramicCap acitor fd = 1 / 2π ⋅ Rd ⋅ C 25 fLC = 1 / 2π ⋅ LC Compensati onNetworkS ingularity doublepole The transfer function may be evaluated neglecting the connection of R8 to PHASE because, as will see later, this connection is important only at low frequencies. So R4 is considered connected to VOUT. Under this assumption, the voltage loop has the following transfer function: Equation 17 Zf ( s ) Gloop ( s ) = Av ( s ) ⋅ R ( s ) = Av ( s ) ⋅ ------------Zi ( s ) where ZC ( s ) Vin Av ( s ) = --------------- ⋅ -----------------------------------∆V osc Z C ( s ) + Z L ( s ) Where ZC(s) and ZL(s) are the output capacitor and inductor impedance respectively. The expression of ZI(s) may be simplified as follow: 21/34 Device description L6911E Equation 18 2 R3 1 ⎛ 1 + s R3 1 ⎛ ⎞ -------- ⋅ τ d⎞ ⋅ ( 1 Rd ⎛ 1 + s ⋅ ( τ 1 + τ d ) + s ⋅ -------- ⋅ τ 1 ⋅ τ d⎞ Rd ⋅ --- ⋅ C25 ⎝ R4 + --s- ⋅ C20⎠ ⋅ R3 ⎝ ⎠ ⎝ ⎠ R Rd d s --------------------------------+ ----------------------------------------------------- = -------------------------------------------------------------------------------------------------- = Rd ---------------------------------------------( 1 + s ⋅ τ2 ) ⋅ ( 1 + s ⋅ τd ) ( 1 + s ⋅ τ2 ) ⋅ ( 1 + Rd + 1 --- ⋅ C25 ⎛ R4 + 1 --- ⋅ C20⎞ + R3 s ⎝ ⎠ s Where: τ1 = R4 × C20, τ2 = (R4+R3) × C20 and τd = Rd × C25. The regulator transfer function became now: Equation 19 ( 1 + s ⋅ τ2 ) ⋅ ( 1 + s ⋅ τd ) R ( s ) ≈ ------------------------------------------------------------------------------------------------------R3 s ⋅ C18 ⋅ R d ⋅ ⎛ 1 + s -------- ⋅ τ d⎞ ⋅ ( 1 + s ⋅ τ 1 ) ⎝ ⎠ Rd Figure 10 on page 21 shows a method to select the regulator components (please note that the frequencies fEC and fCC corresponds to the singularities introduced by additional ceramic capacitors in parallel to the output main electrolytic capacitor). ● To obtain a flat frequency response of the output impedance, the droop time constant τd has to be equal to the inductor time constant (see the note at the end of the section): Equation 20 L τ d = R d ⋅ C25 = ------- = τ L RL ● L ⇒ C25 = ---------------------( RL ⋅ Rd ) To obtain a constant -20dB/dec Gloop(s) shape the singularity f1 and f2 are placed in proximity of fCE and fLC respectively. This implies that: Equation 21 f LC f ---2- = -------f CE f1 f1 = f CE ● ⇒ f LC - – 1⎞ R4 = R3 ⋅ ⎛ ------⎝f ⎠ CE ⇒ 1 C20 = --- ⋅ π ⋅ R4 ⋅ f CE 2 To obtain a Gloop bandwidth of fC, results: Equation 22 f LC = 1 ⋅ f C 22/34 ⇒ fC VIN C20 // C25 G 0 = A 0 ⋅ R 0 = ------------------ ⋅ ----------------------------- = -------f LC ∆Vosc C18 VIN C20 ⋅ C25 ⇒ C18 = ------------------ ⋅ ----------------------------∆Vosc C20 + C25 L6911E Note: Device description To understand the reason of the previous assumption, the scheme in Figure 11 on page 23 must be considered. In this scheme, the inductor current has been substituted by the load current, because in the frequencies range of interest for the Droop function these current are substantially the same and it was supposed that the droop network don't represent a charge for the inductor. Figure 11. Voltage regulation with droop function block scheme V com p A v(s) R (s) V ou t R OUT ⋅ 1+ s ⋅τL Io ut 1+ s ⋅τd It results: Equation 23 G LOOP 1 + sτ L 1 + sτ L Vo Z OUT = -------------- = R d ⋅ ------------------ ⋅ ---------------------------- = R OUT ⋅ -----------------1 + sτ d 1 + G LOOP 1 + sτ d I LOAD Because in the interested range |Gloop|>>1. To obtain a flat shape, the relationship considered will naturally follow. 23/34 VRM demo board description 6 L6911E VRM demo board description Figure 12 shows the schematic circuit of the VRM evaluation board. The design has been developed for a VRM 8.5 Flexible Motherboard applicaton delivering up to 28.5A. An additional circuit sense a Vtt bus (1.2V typ.) and generate a 2.5mS (typ.) delayed Vtt_PWRGD signal when this rail is over 1.1V. The assertion of the Vtt_PWRGD signal enables the device together with the ENOUT input. Figure 12. Schematic circuit L1 F1 +5 VIN R14 VCC GND C12 VID0 VID0 VID1 VID1 VID2 VID2 VID3 VID3 VID25mV VID4 R1 OSC SS OVP BOOT D1 +12Vcc 18 2 11 14 4 13 5 U1 17 L6911E 6 7 16 8 12 20 3 1 9 C13 OCSET PHASE C19 R5 C1-3 R7 L2 Q1,Q2 VOUTCORE LGATE PGND Q3,Q4,Q5 D2 C4-9 R15 R6 PGOOD PWRGD VSEN 10 C18 C10 UGATE R8 VFB COMP Q7 C11 19 15 R3 C20 R9 R4 C17 C14 RESET Vdd NOT RESIN GND Vtt_sense SENSE C16 OUTEN 8 R2 NOT RESET 5 UZ 4TLC7701 D3 2 7 R13 R10 Vtt_PGOOD CT 3 C15 1 CONTROL Q6 R11 24/34 6 R12 L6911E CONNECTOR EVALUATION KIT REV. 1.1 Vss L6911E 6.1 VRM demo board description Efficiency The measured efficiency versus load current at different output voltages is shown in Figure 13. In the application two Mosfets STS12NF30L (30V, 8.5mΩ typ with VGS = 12V) connected in parallel are used for the High Side, while three of them are used for the Low Side. Efficiency [%] Figure 13. Efficiency vs. load current 90 80 70 Vout = 1.825V 60 Vout = 1.225V Vout = 1.500V 50 40 0 6.2 5 10 15 20 Output Current [A] 25 Inductor design Since the maximum output current is 28.5A, to have a 20% ripple (5A) the inductor chosen is 1.5µH. 6.3 Output capacitor In the demo six OSCON capacitors, model 6SP680M, are used, with a maximum ESR equal to 12mΩ each. Therefore the resultant ESR is of 2mΩ. For load transient of 28.5A in the worst case the voltage drop is of: Equation 24 ∆Vout = 28.5 * 0.002 = 57mV The voltage drop due to the capacitor discharge during load transient, considering that the maximum duty cicle is equal to 100% results in 46.5mV with 1.85V of programmed output. 25/34 VRM demo board description 6.4 L6911E Input capacitor For IOUT = 28.5A and with D = 0.5(worst case for input current ripple), Irms is equal to 17.8A. Three OSCON electrolityc capacitors 6SP680M, with a maximum ESR equal to 12mΩ, are chosen to substain the ripple. So the losses in worst case are: Equation 25 2 P = ESR ⋅ I rms = ( 1.25 ( 670 )m )W 6.5 Over-current protection Substituting the demo board parameters in the relationship reported in the relative section, (IOCSMIN = 170µA; IP =33A; RDSONMAX = 3mΩ) it results that ROCS = 1kΩ. 26/34 L6911E 7 Connector pin orientation Connector pin orientation Table 7. Connector pin orientation Pin # Row A Pin # Row B 1 5Vin 50 5Vin 2 5Vin 49 5Vin 3 5Vin 48 5Vin 4 5Vin 47 5Vin 5 12Vin 46 12Vin 6 12Vin 45 12Vin 7 Reserved 44 No Contact 8 VID0 43 VID1 9 VID2 42 VID3 10 VID4 (25mV) 41 PWRGD 11 OUTEN 40 Ishare 12 VTT_PWRGD 39 VTT 13 Vss 38 Vss 14 VccCORE 37 Vss 15 VccCORE 36 VccCORE 16 Vss 35 Vss 17 VccCORE 34 VccCORE 18 Vss 33 Vss 19 VccCORE 32 VccCORE 20 Vss 31 Vss 21 VccCORE 30 VccCORE 22 Vss 29 Vss 23 VccCORE 28 VccCORE 24 Vss 27 Vss 25 VccCORE 26 VccCORE Mechanical Key 27/34 PCB and components layout 8 L6911E PCB and components layout Figure 14. PCB and components layouts Component side silkscreen Component side Figure 15. PCB and components layouts Internal Layer Internal Ground Plane Figure 16. PCB and components layouts Solder Side 28/34 Solder Side Silkscreen L6911E PCB and components layout Table 8. Part list Resistors R1 Not Mounted SMD 0805 R2 470K R3 1K SMD 0805 R4 82 SMD 0805 R5 Not Mounted SMD 0805 R6 20K SMD 0805 R7 680 SMD 0805 R8 13K SMD 0805 R9 100K SMD 0805 R10 6.8K 1% SMD 0805 R11 10K 1% SMD 0805 R12 1K SMD 0805 R13 10K SMD 0805 R14 8.2Ω SMD 0805 R15 1K SMD 0805 1% SMD 0805 Capacitors C1-C3 680µF- 6.3V OSCON 6SP680M Radial 10x10.5 C4-C9 820 µF – 4V or 680µF – 6.3V OSCON 4SP820M OSCON 6SP680M Radial 10x10.5 Radial 10x10.5 C10 1nF SMD 0805 C11,C13-C16 100nF SMD 0805 C12 1µF SMD 0805 C17 47nF SMD 0805 C18 3.3nF SMD 0805 C19 Not Mounted SMD 0805 C20 100nF SMD 0805 Magnetics L1 1.5µH T44-52 Core, 7T - 18AWG L2 1.8µH T50-52B Core, 8T – 16AWG Transistors Q1-Q5 STS12NF30L or FDS6670 STMicroelectronics Fairchild SO8 SO8 Q6 Signal NPN BJT SOT23 Q7 Signal MOSFET SOT23 29/34 PCB and components layout L6911E Table 8. Part list (continued) Diodes D1 1N4148 D2 STPS3L25U SOT23 STMicroelectronics SMB D3 Ics U1 L6911E STMicroelectronics SO20 U2 TLC7701QD Texas Instruments SO8 Littlefuse AXIAL Fuse F1 30/34 251015A-15A L6911E 9 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com 31/34 Package mechanical data L6911E Figure 17. SO20 Mechanical data & package dimensions mm inch DIM. MIN. TYP. MAX. MIN. TYP. MAX. A 2.35 2.65 0.093 0.104 A1 0.10 0.30 0.004 0.012 B 0.33 0.51 0.013 0.200 C 0.23 0.32 0.009 0.013 D (1) 12.60 13.00 0.496 0.512 E 7.40 7.60 0.291 0.299 e 1.27 0.050 H 10.0 10.65 0.394 0.419 h 0.25 0.75 0.010 0.030 L 0.40 1.27 0.016 0.050 k ddd OUTLINE AND MECHANICAL DATA 0˚ (min.), 8˚ (max.) 0.10 0.004 (1) “D” dimension does not include mold flash, protusions or gate burrs. Mold flash, protusions or gate burrs shall not exceed 0.15mm per side. SO20 0016022 D 32/34 L6911E 10 Revision history Revision history Table 9. Revision history Date Revision Changes 15-Nov-2001 2 Preliminary version 10-Apr-2007 3 Document has been reformatted, updated Table 3. 33/34 L6911E Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK. Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2007 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 34/34