L9380 Triple high-side MOSFET driver Features ■ Overvoltage charge pump shut off ■ For VS > 25 V ■ Reverse battery protection (referring to the application circuit diagram) ■ Programmable overload protection function for channel 1 and 2 ■ Open ground protection function for channel 1 and 2 ■ Constant gate charge/discharge current SO20 Description The L9380 device is a controller for three external N-channel power MOS transistors in "High-Side Switch" configuration. Table 1. March 2008 It is intended for relays replacement in automotive electric control units. Device summary Order code Package Packing L9380 SO20 Tube L9380-TR SO20 Tape and reel Rev 2 1/18 www.st.com 1 Contents L9380 Contents 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.1 Typical characteristics curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.1.1 Electromagnetic emission classification (EME) . . . . . . . . . . . . . . . . . . . 15 5 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2/18 L9380 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pins function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electromagnetic emission classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3/18 List of figures L9380 List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. 4/18 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pins connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Timing characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Drain, source input current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Comparator hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Charge loading time as function of VS (Vcp = 8 V +VS) . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Charge pump current as function of the charge voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Ground loss protection gate discarge current for source voltage . . . . . . . . . . . . . . . . . . . . 13 Input current as function of the input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Overvoltage shutdown of the charge pump with hysteresis . . . . . . . . . . . . . . . . . . . . . . . . 13 Measured circuit (The EMS of the device was verified in the below described setup) . . . . 14 Printed circuit board (PCB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 SO20 mechanical data and package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 L9380 1 Block diagram Block diagram Figure 1. Block diagram VS CHARGE PUMP CP OVERVOLTAGE GND VSI T1 ≥1 VSI D1 IPR + S1 CP IN1 ENN ≥1 G1 DRIVER 1 VSI T2 ≥1 VSI D2 IPR + S2 CP IN2 ENN ≥1 G2 DRIVER 2 VSI CP ENN IN3 ≥1 G3 DRIVER 3 EN ENN VS REG. REFERENCE VSI 2V PR IPR D98AT390 5/18 Pins description L9380 2 Pins description Figure 2. Pins connection (top view) T1 1 20 CP VS 2 19 D1 N.C. 3 18 N.C. T2 4 17 D2 PR 5 16 G1 IN3 6 15 S1 IN2 7 14 S2 IN1 8 13 N.C. EN 9 12 G2 10 11 G3 GND D98AT391 Table 2. Pins function N° Pin name Function 1 T1 Timer capacitor; the capacitor defines the time for the channel 1 shut down, after overload of the external MOS transistor has been detected. 2 VS Supply voltage. 4 T2 Timer capacitor; the capacitor defines the time for the channel 2 shut down, after overload of the external MOS transistor has been detected. 5 PR Programming resistor for overload detetcion threshold; the resistor from this pin to ground defines the drain pin current and the charging of the timer capacitor. 6 IN3 Input 3; equal to IN1. 7 IN2 Input 2; equal to IN1. 8 IN1 Input 1; logic signal applied to this pin controls the driver 1; this pin features a current source to assure defined high status when the pin is open. 9 EN Enable logic signal high on this pin enables all channels 10 GND 11 G3 Gate 3 driver output; current source from CP or ground 12 G2 Gate 2 driver output; current source from CP or ground 14 S2 Source 2 sense input; monitors the source voltage. 15 S1 Source 1 sense input; monitors the source voltage. 16 G1 Gate 1 driver output; current source from CP or ground 17 D2 Drain 2 sense input; a programmable input bias current defines the drop across the external resistor RD1; this drop fixes the overload threshold of the external MOS. 19 D1 Drain 1 sense input; a programmable input bias current defines the drop across the external resistor RD1; this drop fixes the overload threshold of the external MOS. 20 CP Charge pump capacitor; a alternating current source at this pin charges the connected capacitor CCP to a voltage 10V higher than VS; the charge stored in this capacitor is than used to charge all the three gates of the power MOS transistors. 3, 13, 18 NC Not connected 6/18 Ground L9380 Electrical specifications 3 Electrical specifications 3.1 Absolute maximum ratings Table 3. Absolute maximum ratings Symbol Parameter VS DC supply voltage VS Supply voltage pulse (t ≤ 400 ms) Value Unit -0.3 to +27 V 45 V ΔVS/dt Supply voltage slope -10 to +10 V/µs VIN,EN Input / enable voltage -0.3 to +7 V Timer voltage -0.3 to 27 V VD, G, S Drain, gate, source voltage -15 to +27 V VD, G, S Drain, gate, source voltage pulse (t ≤ 400 ms) 45 V ID, G, S Drain, gate, source current (t ≤ 2 ms) 0 to +4 mA Operating junction temperature -40 to 150 °C Storage temperature -65 to 150 °C VT Tj Tstg Note: ESD for all pins, except the timer pins, are according to MIL 883C, tested at 2 kV, corresponds to a maximum energy dissipation of 0.2 mJ. The timer pins are tested with 800 V. 3.2 Thermal data Table 4. Thermal data Symbol Rth j-amb Parameter Thermal resistance junction to ambient 3.3 Electrical characteristics Table 5. Electrical characteristics (7 V ≤ VS ≤ 18.5 V; -40° C ≤ TJ ≤ 150 °C, unless otherwise specified.) Symbol Parameter Test condition Min. Value Unit 100 °C/W Typ. Max. Unit 2.5 mA 8 17 V VS = 7 V, VCP = 15 V, Tj ≥ 25 °C -23 -12 µA VS = 7 V, VCP = 15 V, Tj < 25 °C -23 -10 µA Supply IVS Static operating supply current VS = 14 V Charge pump VCP Charge pump voltage above VS ICP Charge pump current 7/18 Electrical specifications Table 5. Electrical characteristics (continued) (7 V ≤ VS ≤ 18.5 V; -40° C ≤ TJ ≤ 150 °C, unless otherwise specified.) Symbol Parameter ICP Charge pump current tCP Charging time VSCP off L9380 Min. VS = 12 V, VCP = 20 V, Tj ≥ 25 °C VS = 12 V, VCP = 20 V, Tj < 25 °C Typ. Max. Unit -70 -45 µA -70 -38 µA 200 µs 30 V VCP = VS + 8 V CCP = 100 pF Overvoltage shut down 20 VSCP hys Overvoltage shut down hysteresis fCP Test condition (1) Charge pump frequency (1) 50 200 1000 mV 100 250 400 KHz Gate drivers IGSo Gate source current VG = VS -5 -3 -1 mA IGSi Gate sink current VG ≥ 0.8 V 1 3 5 mA IGCP Charge pump current on the gate VS = 12 V, VG = 20 V, Tj ≥ 25 °C -60 -35 µA VS = 12V, VG = 20 V, Tj < 25 °C -60 -28 µA Bias current programming voltage 10 µA ≤ IPR ≤ 100 µA; VD ≥ 4 V 1.8 2.2 V 0 5 A Drain - source sensing VPR 2 Drain pin leakage current VS = 0 V; VD =14 V Drain pin bias current VS ≥ VD + 1 V; VD ≥ 5 V 0.9 IPR 1.1 IPR ISmax Source pin input current VS ≥ VD + 1 V; VD ≥ 7 V 10 60 VHYST Comparator hysteresis ID Leak ID 20 A mV Timer VTHi Timer threshold high 4 4.4 4.8 V VTLo Timer threshold low 0.3 0.4 0.5 V IT IN = 5 V; VT = 2 V IN = 0 V; VS < VD; VD ≥ 5 V; VT = 2 V Timer current 0.4 IPR -0.6 IPR 0.6 IPR -0.4 IPR Inputs VLOW Input enable low voltage -0.3 1 V VHIGH Input enable high voltage 3 7 V VINhys (1) 500 mV Input enable hysteresis 50 200 IIN Input source current VIN ≤ 3 V -30 -5 μA IEN Enable sink current VEN ≥ 1 V 5 30 μA Transfer time IN/ENABLE VS = 14 V VG = VS; Open Gate 2.5 µs td 1. Not measured guaranteed by design. Function is given for supply voltage down to 5.5V. Function means: the channels are controlled from the inputs, some other parameters may exceed the limit. In this case the programming voltage and timer threshold will be lower. This leads to a lower protection threshold and time. 8/18 L9380 4 Functional description Functional description The triple high-side Power-MOS Driver features all necessary control and protection functions to switch on three Power-MOS transistors operating as High-Side switches in automotive electronic control units. The key application field is relays replacement in systems where high current loads, usually motors with nominal currents of about 40 A connected to ground, has to be switched. A high signal at the EN pin enables all three channels. With enable low gates are clamped to ground. In this condition the gate sink current is higher than the specified 3 mA. An enable low signal makes also a reset of the timer. A low signal at the inputs switch on the gates of the external MOS. A short circuit at the input leads to permanent activation of the concerned channel. In this case the device can be disabled with the enable pin. The charge pump loading is not influenced due to the enable input. An external N-channel MOS driver in high side configuration needs a gate driving voltage higher than VS. It is generated by means of a charge pump with integrated charge transfer capacitors and one external charge storage capacitor CCP. The charge pump is dimensioned to load a capacitor CCP of 33 nF in less than 20 ms up to 8V above VS. The value of CCP depends on the input capacitance of the external MOS and the decay of the charge pump voltage down to that value where no significant influence on the application occurs. The necessary charging time for CCP has to be respected in the sequence of the input control signals. As a consequence the lower gate to source voltage can cause a higher drop across the Power-MOS and get into overload condition. In this case the overload protection timer will start. After the protection time the concerned channel will be switched off. Channel 3 is not equipped with an overload protection. The same situation can occur due to a discharge of the storage capacitor caused by the gate short to ground. The gate driver that is supplied from the pin CP, which is the charge pump output, has a sink and source current capability of 3 mA. For a short-circuit of the load (source to ground) the L9380 has no gate to source limitation. The gate source protection must be done externally. Channel 1 and 2 provide drain to source voltage sensing possibility with programmable shut-off delay when the activation threshold was exceeded. This threshold VDSmin is set by the external resistor RD. The bias current flowing through this resistor is determined by the programming resistor RPR. This external resistor RPR defines also the charge and discharge current of the timer capacitor CCT. The drain to source threshold VDSmin and the timer shut off delay time Toff can be calculated: ⎛ RD ⎞ V DSmin = V PR ⎜ ------------⎟ ⎝ R PR⎠ Toff = 4.4 CT RPR 9/18 Functional description L9380 In application which don’t use the overload protection or if one channel is not used, the Timer pin of this channel must be connected to ground and the drain pin with a resistor to Vbat. The timing characteristic illustrates the function and the meaning of VDSmin and Toff (see Figure 6). The input current of the overload sense comparator is specified as ISmax. The sum IPR + IDmax generates a drop across the external resistor RD if the drain pin voltage is higher than the source pin (see Figure 4). In the switching point the comparator input source pin currents are equal and the half of the specified current ISmax. For an offset compensation equal external resistors (RD = RS) at drain and source pin are imperative. The drain sense comparator, which detects the overload, has a symmetrical hysteresis of 20 mV (see Figure 5). Exceeding the source pin voltage by 10 mV with respect to the drain voltage forces the timer capacitor to discharge. Decreasing the source pin voltage 10 mV lower than the drain pin voltage an overload of the external MOS is detected and the timer capacitor will be loaded. After reaching a voltage at pin CT higher than the timer threshold VThi the influenced channel is switched off. In this case the overload is stored in the timer capacitor. The timer capacitor will be discharged with a ’High’ signal at the input (see Figure 3). After reaching the lower timer threshold VTLo the overload protection is reset and the channel is able to switch on again. Figure 3. Timing characteristic VIN VG td td VDSmin VS VT 4.4V 0.4V D98AT392 Toff Figure 4. Drain, source input current. ID IPR + IDmax VD > VS = VD VS VS > VD IPR 0 10/18 D98AT393 ISmax IS L9380 Functional description Figure 5. Comparator hysteresis VT D98AT394 -10mV VDr +10mV VSo The application diagram is shown in Figure 6. Because of the transients present at the power lines during operation and possible disturbances in the system the external resistors are necessary. Positive ISO-Pulses at Drain, Gate Source are clamped with an active clamping structure. The clamping voltage is less than 60V. Negative Pulses are only clamped with the ESDStructure less than -15 V. This transients lower than -15 V can influence the other channels. In order to protect the transistor against overload and gate breakdown protection diodes between gate and source and gate and drain has to be connected. In case of overvoltage into VS (VS > 20 V) the charge pump oscillation is stopped. Then the charge pump capacitor will be loaded by a diode and a resistor in series up to VS (see Figure 1). In this case the channels are not influenced. In reverse battery condition the pins D1, D2, S1, S2 follow the battery potential down to -13 V (high impedance) and the gate driver pins G1, G2 is referred to S1, S2. In this way it is assured that M1 and M2 will not be driven into the linear conductive mode. This protection function is operating for VS1, VS2 down to -15 V. The gate driver output G3 is referred to the D1 in this case. This function guarantees that the source to source connected N-Channel MOS transistors M3 and M4 remains OFF. All the supplies and the in- and output of the PC Board are supplied with a 40 wires flat cable (not used wires are left open). This cable is submitted to the RF in the strip-line like described in DIN 40839-4 or ISO 11456-5. The measured circuit was build up on a PCB board with ground plane. In the frequency range from 1 MHz to 400 MHz and 80 % AM-modulation of 1 kHz with field strength of 200 V/m no influence to the basic function was detected on a typical device. The failure criteria is an envelope of the output signal with 20 % in the amplitude and 2 % in the time. 11/18 Functional description L9380 Figure 6. Application circuit D1 VBAT VS D2 CHARGE PUMP OVERVOLTAGE C1 VSI T1 C4 D1 ≥1 VSI C2 CP GND IPR + R1 D3 G1 CP M1 R2 D4 IN1 ENN S1 ≥1 R3 DRIVER 1 VSI ≥1 VSI C3 D2 - T2 IPR + R4 D5 M2 G2 CP R5 D6 MICROCONTROLLER IN2 ENN S2 ≥1 M M1 R6 DRIVER 2 VSI CP ENN IN3 D7 ≥1 G3 M3 R7 DRIVER 3 D8 EN ENN VS REG. REFERENCE VSI IPR M4 R8 2V M M2 PR L1 L2 L3 L4 LOAD CONTROL VALUE DRIVER U405 D98AT395A Recommendations to the application circuit: The timer and the charge capacitors are loaded with an alternating current source. A short ground connection of the charge capacitor is indispensable to avoid electromagnetic emigrations. The dimension of the resistors RD, RG and RS have to respect the maximum current during transients at each pin. 12/18 L9380 Functional description 4.1 Typical characteristics curve Depending on production spread, certain deviations may occure. For limits see Table 5. Figure 7. Charge loading time as function of Figure 8. VS (Vcp = 8 V +VS) tCH (ms) Charge pump current as function of the charge voltage D98AT396 D98AT397 ICP (μA) 20 100 12V 16V 10V 68nF 10 50 7V 33nF 10nF 0 6 Figure 9. 8 10 12 14 16 VS(V) 0 7 17 27 VC(V) Ground loss protection gate Figure 10. Input current as function of the discarge current for source voltage input voltage D98AT398 IG (μA) D98AT399 IC (μA) -200 -5 -400 -10 -600 -15 -800 -1000 -20 -15 -10 -5 VS(V) 0 1 2 3 4 VI(V) Figure 11. Overvoltage shutdown of the charge pump with hysteresis VCH (V) D98AT400 30 20 24 24.5 25 25.5 VS(V) 13/18 Functional description L9380 Figure 12. Measured circuit (The EMS of the device was verified in the below described setup) 3.125Hz 9 3 4 5 10 1 2 f 2 8 6.25Hz f U(t) 2 7 12.5Hz + f CAR-BATTERY 2 6 25Hz ANECHOIC CHAMBER 2m STRIPLINE 2 BNC SMB7W01-200 SMT_39A VS 100nF CHARGE PUMP OVERVOLTAGE 33μF VSI T1 10nF 33nF GND D1 ≥1 VSI CP 2KΩ IPR + STD17N06 33V G1 CP 10KΩ 18V IN1 1KΩ 6 2.2nF IN1 ENN 5.6V S1 ≥1 3 1KΩ VSI D2 - T2 10nF 10KΩ 2KΩ DRIVER 1 4.7nF ≥1 VSI STD17N06 G2 33V 10KΩ 18V 1KΩ 7 2.2nF IN2 ENN 5.6V 4.7nF 4 2KΩ DRIVER 2 2.2nF 5Ω 10KΩ S2 ≥1 OUT1 2KΩ IPR + CP IN2 5Ω B60N06 VS 1 BNC B60N06 VBAT 1KΩ OUT2 2.2nF VSI CP IN3 1KΩ 8 2.2nF EN 5.6V 2.2nF ENN 5.6V 4.7nF 33V G3 B60N06 10KΩ 10KΩ 18V EN 10 STD17N06 ≥1 DRIVER 3 4.7nF 1KΩ 9 ENN IN3 VS REG. REFERENCE VSI OUT3 2.2nF 20KΩ 2V IPR 5 1KΩ PR PC-BOARD IN RF BOX D98AT401 14/18 L9380 Functional description Figure 13. Printed circuit board (PCB) 4.1.1 Electromagnetic emission classification (EME) Electromagnetic emission classes presented below are typical data found on bench test. For detailes test description please refer to "Electromagnetic Emission (EME) Measurement of Integrated Circuits, DC to 1 GHz" of VDE/ZVEI work group 767.13 and VDE/ZVEI work group 767.14 or IEC project number 47A 1967Ed. This data is targeted to board designers to allow an estimation of emission filtering effort required in application. All measurements are done with the EMS-board (See Figure 12 and 13). Table 6. Electromagnetic emission classification Pin VCP Note: EME class G - Remark w Electromagnetic Emission and Susceptivity is not tested in production. 15/18 Package information 5 L9380 Package information In order to meet environmental requirements, ST (also) offers these devices in ECOPACK® packages. ECOPACK® packages are lead-free. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 14. SO20 mechanical data and package dimensions mm inch DIM. MIN. A TYP. 2.35 MAX. MIN. 2.65 0.093 TYP. MAX. 0.104 A1 0.10 0.30 0.004 0.012 B 0.33 0.51 0.013 0.200 C 0.23 0.32 0.009 0.013 D (1) 12.60 13.00 0.496 0.512 E 7.40 7.60 0.291 0.299 e 1.27 0.050 H 10.0 10.65 0.394 0.419 h 0.25 0.75 0.010 0.030 L 0.40 1.27 0.016 0.050 k ddd OUTLINE AND MECHANICAL DATA 0˚ (min.), 8˚ (max.) 0.10 0.004 (1) “D” dimension does not include mold flash, protusions or gate burrs. Mold flash, protusions or gate burrs shall not exceed 0.15mm per side. SO20 0016022 D 16/18 L9380 6 Revision history Revision history Table 7. Document revision history Date Revision Changes 20-May-2003 1 Initial release. 05-Mar-2008 2 Document reformatted. Modified Figure 6: Application circuit. 17/18 L9380 Please Read Carefully: Information in this document is provided solely in connection with ST products. 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