STMICROELECTRONICS LFTVS18-1F3

LFTVS18-1F3
Low forward voltage Transil™, transient voltage suppressor
Features
■
Low forward voltage: 1.1 V @ 850 mA
■
Peak pulse power (8/20 µs): 350 W
■
Very low clamping factor VCL/VBR
■
Unidirectional device
■
Fast response time
■
Very thin package: 0.605 mm
■
RoHS compliant
Flip chip
(4 bumps)
Figure 1.
Pin configuration (bump side)
Complies with the following standards:
■
A
IEC 61000-4-2 level 4
– ± 15 kV (air discharge)
– ± 8 kV (contact discharge)
B
1
2
Description
The LFTVS18-1F3 is a single line diode designed
specifically for the protection of integrated circuits
in portable equipment and miniaturized
electronics devices subject to ESD and EOS
transient overvoltages.
Figure 2.
Device configuration
A1 and A2
B1 and B2
TM: Transil is a trademark of STMicroelectronics
March 2008
Rev 1
1/7
www.st.com
Characteristics
1
LFTVS18-1F3
Characteristics
Table 1.
Absolute maximum ratings (Tamb = 25 °C)
Symbol
Parameter
Test condition
Value
Peak pulse power dissipation
(10/1000 µs pulse)
PPP
IFSM
Tj
Tstg
Table 2.
Peak pulse power dissipation
(8/20 µs pulse)
Non repetitive surge peak forward
current
44
Tj initial = Tamb
tp = 10 ms
Tj initial = Tamb
Storage temperature range
7
A
125
°C
-55 to +150
°C
Electrical characteristics (Tamb = 25 °C)
Parameter
VBR
Breakdown voltage
IRM
Leakage current @ VRM
VRM
Stand-off voltage
VCL
Clamping voltage
Rd
Dynamic impedance
IPP
Peak pulse current
αT
Voltage temperature coefficient
VF
Forward voltage drop
I
IF
Symbol
Test conditions
VBR
IR = 1 mA
IRM
VRM = 10 V
VF
VCL VBR VRM
V
IRM
Slope = 1/Rd
Min.
Typ.
16
(1)
IPP
Max.
Unit
18
V
500
nA
V
VCL
IPP = 1 A
19
VF
IF = 850 mA
1.1
αT
9
VR = 0 V, VOSC = 30 mV, F = 1 MHz
1. 8 / 20 µs pulse waveform
2/7
W
350
Maximum operating junction temperature
Symbol
Cline
Unit
130
V
10-4
/ °C
pF
LFTVS18-1F3
Figure 3.
Characteristics
Relative variation of peak pulse
power versus initial junction
temperature
Figure 4.
PPP[Tj initial] / PPP[Tj initial=25°C]
PPP(W)
10000
1.1
Peak pulse power versus
exponential pulse duration (typical
value)
Tj initial = 25 °C
1.0
0.9
0.8
1000
0.7
0.6
0.5
0.4
100
0.3
0.2
0.1
tp(µs)
Tj(°C)
10
0.0
0
25
Figure 5.
10.0
50
75
100
125
1
150
Clamping voltage versus peak
pulse current (typical values)
10
Figure 6.
IPP(A)
1000
100
1000
Relative variation of leakage
current versus junction
temperature (typical values)
IR[Tj] / IR[Tj=25°C]
VR =10V
tp = 10/1000 µs
Tj initial = -30° C
Tj initial = 25° C
100
Tj initial = 85° C
1.0
10
Tj(°C)
VCL(V)
1
0.1
15
16
Figure 7.
17
18
19
20
21
22
23
24
25
Forward voltage drop versus peak
forward current (typical values)
25
50
Figure 8.
75
100
125
Junction capacitance versus
reverse voltage applied (typical
values)
Capacitance(pF)
IFM(A)
1.E+02
140
120
Tj initial = 25° C
1.E+01
80
Tj initial = 85° C
40
Tj initial = -30° C
VFM(V)
0.6
0.8
1.0
1.2
1.4
1.6
1.8
Voltage(V)
0
1.E+00
2.0
2.2
2.4
2.6
0
-2
-4
-6
-8
-10
3/7
Ordering information scheme
Figure 9.
19.0
LFTVS18-1F3
Breakdown voltage versus initial
Figure 10. Frequency response
junction temperature (typical value)
VBR(V)
0.00
-15.00
18.0
-30.00
17.0
-45.00
F/Hz
Tj(° C)
16.0
-40
-60.00
-15
10
35
60
85
110
100.0k
135
Figure 11. ESD response to IEC 61000-4-2
(+8 kV contact discharge)
1.0M
10.0M
100.0M
1.0G
Figure 12. ESD response to IEC 61000-4-2
(-8 kV contact discharge)
X: 20ns/div
Y: 10V/div
X: 20ns/div
Y: 10V/div
2
Ordering information scheme
Figure 13. Ordering information scheme
LF
Low forward voltage
Transient voltage suppressor
Breakdown voltage
18 = 18 VMAX
Number of lines
1 = single line
Package
F = Flip chip
3: lead free, pitch = 400 µm
4/7
TVS 18 - 1 F3
LFTVS18-1F3
Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a lead-free second level interconnect. The category of
second level interconnect is marked on the inner box label, in compliance with JEDEC
Standard JESD97. The maximum ratings related to soldering conditions are also marked on
the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at
www.st.com.
Figure 14. Flip chip dimensions
605 µm ± 55
0.77 mm ± 30 µm
400 µm ± 40
185 µm ± 10
400 µm ± 40
3
Package information
205 µm ± 40
185 µm ± 10
0.77 mm ± 30 µm
255 µm ± 40
Figure 15. Footprint recommendations
Copper pad Diameter:
220 µm recommended
260 µm maximum
Solder mask opening:
300 µm minimum
Solder stencil opening:
220 µm recommended
Figure 16. Marking
Dot
xx = marking
z = manufacturing location
yww = datecode
(y = year
ww = week)
x x z
y ww
5/7
Ordering information
LFTVS18-1F3
Figure 17. Flip chip tape and reel specifications
Dot identifying Pin A1 location
3.5 ± 0.1
xxz
yww
4 ± 0.1
User direction of unreeling
All dimensions in mm
Note:
0.87
xxz
yww
xxz
yww
8 ± 0.3
0.87
0.71 ± 0.05
1.75 ± 0.1
Ø 1.5 ± 0.1
4 ± 0.1
More information is available in the application notes:
AN2348: “400 µm flip chip: Package description and recommendations for use”
AN1751: "EMI Filters: Recommendations and measurements"
4
Ordering information
Table 3.
5
Order code
Marking
Package
Weight
Base qty
Delivery mode
LFTVS18-1F3
EM
Flip chip
0.86 mg
5000
Tape and reel (7”)
Revision history
Table 4.
6/7
Ordering information
Document revision history
Date
Revision
06-Mar-2008
1
Changes
Initial release.
LFTVS18-1F3
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