M36W0R6050T1 M36W0R6050B1 64 Mbit (4 Mb ×16, Multiple Bank, Burst) Flash memory and 32 Mbit (2 Mb ×16) PSRAM, multi-chip package Features ■ Multi-Chip Package – 1 die of 64 Mbit (4 Mb × 16) Flash memory – 1 die of 32 Mbit (2 Mb × 16) Pseudo SRAM ■ Supply voltage – VDDF = VDDP = VDDQF = 1.7 V to 1.95 V ■ Low power consumption ■ Electronic signature – Manufacturer Code: 20h – Device code (top flash configuration), M36W0R6050T1: 8810h – Device code (bottom flash configuration), M36W0R6050B1: 8811h ■ FBGA Stacked TFBGA88 (ZA) Package – ECOPACK® ■ Block locking – All blocks locked at Power-up – Any combination of blocks can be locked – WPF for Block Lock-Down ■ Security – 128-bit user programmable OTP cells – 64-bit unique device number ■ Common Flash Interface (CFI) ■ 100 000 program/erase cycles per block Flash memory ■ ■ ■ ■ Programming time – 8 µs by Word typical for Fast Factory Program – Double/Quadruple Word Program option – Enhanced Factory Program options PSRAM Memory blocks – Multiple Bank memory array: 4 Mbit Banks – Parameter Blocks (Top or Bottom location) Synchronous / Asynchronous Read – Synchronous Burst Read mode: 66 MHz – Asynchronous/ Synchronous Page Read mode – Random Access: 70 ns Dual operations – Program Erase in one Bank while Read in others – No delay between Read and Write operations January 2007 1 ■ Access time: 70 ns ■ Asynchronous Page Read – Page size: 8 words – First access within page: 70 ns – Subsequent read within page: 20 ns ■ Three Power-down modes – Deep Power-Down – Partial Array Refresh of 4 Mbits – Partial Array Refresh of 8 Mbits 1/22 www.st.com 1 Contents M36W0R6050T1, M36W0R6050B1 Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 Address inputs (A0-A21) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 Data inputs/outputs (DQ0-DQ15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.3 Flash Chip Enable (EF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4 Flash Output Enable (GF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.5 Flash Write Enable (WF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6 Flash Write Protect (WPF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.7 Flash Reset (RPF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.8 Flash Latch Enable (LF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.9 Flash Clock (KF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.10 Flash Wait (WAITF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.11 PSRAM Chip Enable (E1P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.12 PSRAM Chip Enable (E2P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.13 PSRAM Output Enable (GP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.14 PSRAM Write Enable (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.15 PSRAM Upper Byte Enable (UBP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.16 PSRAM Lower Byte Enable (LBP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.17 VDDF supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.18 VDDP supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.19 VDDQF supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.20 VPPF program supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.21 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5 DC and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2/22 M36W0R6050T1, M36W0R6050B1 Contents 7 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3/22 List of tables M36W0R6050T1, M36W0R6050B1 List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. 4/22 Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Main operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Device capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Stacked TFBGA88 8 × 10 mm - 8 × 10 ball array, 0.8 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 M36W0R6050T1, M36W0R6050B1 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 TFBGA connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Stacked TFBGA88 8 × 10 mm - 8 × 10 active ball array, 0.8 mm pitch, package outline. . 18 5/22 Description 1 M36W0R6050T1, M36W0R6050B1 Description The M36W0R6050T1 and M36W0R6050B1 combine two memories in a Multi-Chip Package: ● a 64-Mbit, Multiple Bank Flash memory, the M58WR064HT/B, and ● a 32-Mbit Pseudo SRAM, the M69KB048BD. The purpose of this document is to describe how the two memory components operate with respect to each other. It must be read in conjunction with the M58WR064HT/B and M69KB048BD datasheets, where all specifications required to operate the Flash memory and PSRAM components are fully detailed. These datasheets are available from the ST web site: www.st.com. Recommended operating conditions do not allow more than one memory to be active at the same time. The memory is offered in a Stacked TFBGA88 (8 ×10 mm, 8 × 10 ball array, 0.8 mm pitch) package. It is supplied with all the bits erased (set to ‘1’). Figure 1. Logic diagram VDDQF VPPF VDDF VDDP 22 16 A0-A21 DQ0-DQ15 EF GF WAITF WF RPF WPF LF KF M36W0R6050T1 M36W0R6050B1 E1P GP WP E2P UBP LBP VSS Ai12035 6/22 M36W0R6050T1, M36W0R6050B1 Table 1. Description Signal names (1) A0-A21 Address Inputs DQ0-DQ15 Common Data Inputs/Outputs VDDF Flash Memory Power Supply VDDQF Flash memory Power Supply for I/O Buffers VPPF Common Flash Optional Supply Voltage for Fast Program & Erase VSS Ground VDDP PSRAM Power Supply NC Not Connected Internally DU Do Not Use as Internally Connected Flash memory control functions LF Latch Enable input EF Chip Enable input GF Output Enable input WF Write Enable input RPF Reset input WPF Write Protect input KF Burst Clock WAITF Wait Data in Burst Mode PSRAM control functions E1P Chip Enable input GP Output Enable input WP Write Enable input E2P Power-down input UBP Upper Byte Enable input LBP Lower Byte Enable input 1. A21 is an address input for the Flash memory component only. 7/22 Description Figure 2. M36W0R6050T1, M36W0R6050B1 TFBGA connections (top view through package) 1 2 3 4 5 A DU DU B A4 A18 A19 VSS VDDF C A5 LBP NC VSS D A3 A17 NC E A2 A7 F A1 G 6 7 8 DU DU NC A21 A11 NC KF NC A12 VPPF WP EP A9 A13 NC WPF LF A20 A10 A15 A6 UBP RPF WF A8 A14 A16 A0 DQ8 DQ2 DQ10 DQ5 DQ13 WAITF NC H GP DQ0 DQ1 DQ3 DQ12 DQ14 DQ7 NC J NC GF DQ9 DQ11 DQ4 DQ6 DQ15 VDDQF K EF NC NC NC VDDP NC VDDQF E2P L VSS VSS VDDQF VDDF VSS VSS VSS VSS M DU DU DU DU AI12037 8/22 M36W0R6050T1, M36W0R6050B1 2 Signal descriptions Signal descriptions See Figure 1: Logic diagram and Table 1: Signal names, for a brief overview of the signals connected to this device. 2.1 Address inputs (A0-A21) Addresses A0-A21 are common inputs for the Flash memory and PSRAM components, whereas A21 is an address input for the Flash memory component only. The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the Flash memory Program/Erase Controller, and they select the cells to access in the PSRAM. 2.2 Data inputs/outputs (DQ0-DQ15) For the Flash memory, the Data I/O outputs the data stored at the selected address during a Bus Read operation or inputs a command or the data to be programmed during a Write Bus operation. For the PSRAM, the Upper Byte Data Inputs/Outputs carry the data to or from the upper part of the selected address during a Write or Read operation, when Upper Byte Enable (UBP) is driven Low. Likewise, the Lower Byte Data Inputs/Outputs carry the data to or from the lower part of the selected address during a Write or Read operation, when Lower Byte Enable (LBP) is driven Low. 2.3 Flash Chip Enable (EF) The Chip Enable inputs activate the memory control logics, input buffers, decoders and sense amplifiers. When Chip Enable is Low, VIL, and Reset is High, VIH, the device is in active mode. When Chip Enable is at VIH the Flash memory is deselected, the outputs are high impedance and the power consumption is reduced to the standby level. 2.4 Flash Output Enable (GF) The Output Enable pins control data outputs during Flash memory Bus Read operations. 2.5 Flash Write Enable (WF) The Write Enable controls the Bus Write operation of the Flash memories’ Command Interface. The data and address inputs are latched on the rising edge of Chip Enable or Write Enable whichever occurs first. 9/22 Signal descriptions 2.6 M36W0R6050T1, M36W0R6050B1 Flash Write Protect (WPF) Write Protect is an input that gives an additional hardware protection for each block. When Write Protect is Low, VIL, Lock-Down is enabled and the protection status of the LockedDown blocks cannot be changed. When Write Protect is at High, VIH, Lock-Down is disabled and the Locked-Down blocks can be locked or unlocked. (Refer to Lock Status Table in M58WR064HT/B datasheet). 2.7 Flash Reset (RPF) The Reset input provides a hardware reset of the memory. When Reset is at VIL, the memory is in Reset mode: the outputs are high impedance and the current consumption is reduced to the Reset Supply Current IDD2. Refer to the M58WR064HT/B datasheet, for the value of IDD2. After Reset all blocks are in the Locked state and the Configuration Register is reset. When Reset is at VIH, the device is in normal operation. Exiting Reset mode the device enters Asynchronous Read mode, but a negative transition of Chip Enable or Latch Enable is required to ensure valid data outputs. The Reset pin can be interfaced with 3V logic without any additional circuitry. It can be tied to VRPH (refer to the M58WR064HT/B datasheet). 2.8 Flash Latch Enable (LF) Latch Enable latches the address bits on its rising edge. The address latch is transparent when Latch Enable is Low, VIL, and it is inhibited when Latch Enable is High, VIH. Latch Enable can be kept Low (also at board level) when the Latch Enable function is not required or supported. 2.9 Flash Clock (KF) The Clock input synchronizes the Flash memory to the microcontroller during synchronous read operations; the address is latched on a Clock edge (rising or falling, according to the configuration settings) when Latch Enable is at VIL. Clock is don't care during Asynchronous Read and in write operations. 2.10 Flash Wait (WAITF) WAIT is a Flash output signal used during Synchronous Read to indicate whether the data on the output bus are valid. This output is high impedance when Flash Chip Enable is at VIH or Flash Reset is at VIL. It can be configured to be active during the wait cycle or one clock cycle in advance. The WAITF signal is not gated by Output Enable. 2.11 PSRAM Chip Enable (E1P) When asserted (Low), the Chip Enable, E1P, activates the memory state machine, address buffers and decoders, allowing Read and Write operations to be performed. When deasserted (High), all other pins are ignored, and the device is automatically put in Standby mode. 10/22 M36W0R6050T1, M36W0R6050B1 2.12 Signal descriptions PSRAM Chip Enable (E2P) When de-asserted (Low), the Chip Enable input E2P, puts the device in Power-Down mode. This is the lowest power mode according to the Configuration Register settings (see M69KB048BD datasheet). 2.13 PSRAM Output Enable (GP) The Output Enable, GP, provides a high speed tri-state control, allowing fast read/write cycles to be achieved with the common I/O data bus. 2.14 PSRAM Write Enable (WP) The Write Enable, WP, controls the Bus Write operation of the memory’s Command Interface. 2.15 PSRAM Upper Byte Enable (UBP) The Upper Byte Enable, UBP, gates the data on the Upper Byte Data Inputs/Outputs (DQ8DQ15) to or from the upper part of the selected address during a Write or Read operation. 2.16 PSRAM Lower Byte Enable (LBP) The Lower Byte Enable, LBP, gates the data on the Lower Byte Data Inputs/Outputs (DQ0DQ7) to or from the lower part of the selected address during a Write or Read operation. 2.17 VDDF supply voltage VDDF provides the power supply to the internal core of the Flash memory component. It is the main power supplies for all Flash memory operations (Read, Program and Erase). 2.18 VDDP supply voltage The VDDP Supply Voltage supplies the power for all operations (Read or Write) and for driving the refresh logic, even when the device is not being accessed. 2.19 VDDQF supply voltage VDDQF provides the power supply for the Flash memory I/O pins. This allows all Outputs to be powered independently of the Flash memory core power supply, VDDF. 11/22 Signal descriptions 2.20 M36W0R6050T1, M36W0R6050B1 VPPF program supply voltage VPPF is both a Flash Memory control input and a Flash Memory power supply pin. The two functions are selected by the voltage range applied to the pin. If VPPF is kept in a low voltage range (0V to VDDQF) VPPF is seen as a control input. In this case a voltage lower than VPPLKF gives an absolute protection against Program or Erase, while VPPF > VPP1F enables these functions (see the M58WR064HT/B datasheet for the relevant values). VPPF is only sampled at the beginning of a Program or Erase; a change in its value after the operation has started does not have any effect and Program or Erase operations continue. If VPPF is in the range of VPPHF it acts as a power supply pin. In this condition VPPF must be stable until the Program/Erase algorithm is completed. 2.21 VSS ground VSS is the common ground reference for all voltage measurements in the Flash memory (core and I/O Buffers) and PSRAM components. Note: 12/22 Each Flash memory device in a system should have its supply voltages (VDDF, VDDQF) and the program supply voltage VPPF decoupled with a 0.1µF ceramic capacitor close to the pin (high frequency, inherently low inductance capacitors should be as close as possible to the package). See Figure 5: AC measurement load circuit. The PCB track widths should be sufficient to carry the required VPPF program and erase currents. M36W0R6050T1, M36W0R6050B1 3 Functional description Functional description The Flash memory and PSRAM components have separate power supplies but share the same grounds. They are distinguished by three Chip Enable inputs: EF for the Flash memory and E1P and E2P for the PSRAM. Recommended operating conditions do not allow more than one device to be active at a time. The most common example is simultaneous read operations on the Flash memory and the PSRAM which would result in a data bus contention. Therefore it is recommended to put the other devices in the high impedance state when reading the selected device. Figure 3. Functional block diagram VDDF VPPF VDDQF A21 EF 64 Mbit Flash Memory GF WF WAITF LF KF RPF A0-A20 WPF DQ0-DQ15 VDDP E1P GP WP 32 Mbit PSRAM E2P UBP LBP VSS AI12.36 13/22 Functional description Table 2. M36W0R6050T1, M36W0R6050B1 Main operating modes Operation RPF WAITF(4) EF GP WP LF Flash Read VIL VIL VIH VIL(2) VIH Flash Write VIL VIH VIL VIL(2) VIH Flash Address Latch VIL X VIH VIL VIH Flash Data Out or Hi-Z Flash Output Disable VIL VIH VIH X VIH Flash Hi-Z Flash Standby VIH X X X VIH Hi-Z X X X X VIL Hi-Z Flash Reset E1P E2P GP WP UBP LBP DQ15-DQ0 Flash Data Out Flash Data In PSRAM must be disabled (3) Any PSRAM mode is allowed Flash Hi-Z Flash Hi-Z VIL VIH VIL VIH VIL VIL PSRAM data out PSRAM Write VIL VIH VIH VIL VIL VIL PSRAM data in Output Disable VIL VIH VIH VIH X X PSRAM Hi-Z VIH VIH X X X X PSRAM Hi-Z X VIL X X X X PSRAM Hi-Z PSRAM Read Flash Memory must be disabled PSRAM Standby PSRAM Deep Power-Down Any Flash mode is allowed. 1. X = Don't care. 2. LF can be tied to VIH if the valid address has been previously latched. 3. Depends on GF. 4. WAIT signal polarity is configured using the Set Configuration Register command. Refer to M58WR064HT/B datasheet for details. 14/22 M36W0R6050T1, M36W0R6050B1 4 Maximum rating Maximum rating Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 3. Absolute maximum ratings Value Symbol Parameter Unit Min Max Ambient Operating Temperature –30 85 °C TBIAS Temperature Under Bias –40 125 °C TSTG Storage Temperature –55 125 °C Input or Output Voltage –0.5 VDDQF+0.6 V Flash Memory Core Supply Voltage –0.2 2.45 V VDDQF Input/Output Supply Voltage –0.2 2.45 V VDDP PSRAM Supply Voltage –0.5 3.6 V VPPF Flash Memory Program Voltage –0.2 14 V Output Short Circuit Current 100 mA Time for VPPF at VPPFH 100 hours TA VIO VDDF IO tVPPFH 15/22 DC and ac parameters 5 M36W0R6050T1, M36W0R6050B1 DC and ac parameters This section summarizes the operating measurement conditions, and the dc and ac characteristics of the device. The parameters in the dc and ac characteristics Tables that follow, are derived from tests performed under the Measurement Conditions summarized in Table 4: Operating and ac measurement conditions. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. Table 4. Operating and ac measurement conditions Flash memory PSRAM Parameter Unit Min Max Min Max VDDF Supply Voltage 1.7 1.95 – – V VDDP Supply Voltage – – 1.7 1.95 V VDDQF Supply Voltage 1.7 1.95 – – V 11.4 12.6 – – V –0.4 VDDQF +0.4 – – V –30 85 –30 85 °C VPPF Supply Voltage (Factory environment) VPPF Supply Voltage (Application environment) Ambient Operating Temperature Load Capacitance (CL) 30 Input Rise and Fall Times 5 Input Pulse Voltages Input and Output Timing Ref. Voltages Figure 4. 50 ns 0 to VDDQF 0 to VDDP V VDDQF/2 VDDP/2 V AC measurement I/O waveform VDDQF VDDQF/2 0V AI12057 16/22 pF M36W0R6050T1, M36W0R6050B1 Figure 5. DC and ac parameters AC measurement load circuit VDDQF VDDF VDDQF 16.7kΩ DEVICE UNDER TEST CL 0.1µF 16.7kΩ 0.1µF CL includes JIG capacitance AI12058 Table 5. Symbol CIN COUT Device capacitance Parameter Input Capacitance Output Capacitance Test condition Min Max Unit VIN = 0V 12 pF VOUT = 0V 15 pF 1. Sampled only, not 100% tested. Please refer to the M58WR064HT/B and M69KB048BD datasheets for further dc and ac characteristics values and illustrations. 17/22 Package mechanical 6 M36W0R6050T1, M36W0R6050B1 Package mechanical In order to meet environmental requirements, ST offers the M36W0R6050T1 and M36W0R6050B1 devices in ECOPACK® packages. These packages have a Lead-free second-level interconnect. The category of Second-Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 6. Stacked TFBGA88 8 × 10 mm - 8 × 10 active ball array, 0.8 mm pitch, package outline D D1 e SE E E2 E1 b BALL "A1" ddd FE FE1 FD SD A2 A A1 BGA-Z42 1. Drawing is not to scale. 18/22 M36W0R6050T1, M36W0R6050B1 Table 6. Package mechanical Stacked TFBGA88 8 × 10 mm - 8 × 10 ball array, 0.8 mm pitch, package mechanical data millimeters inches Symbol Typ Min A Max Typ Min 1.200 A1 Max 0.0472 0.200 0.0079 A2 0.850 0.0335 b 0.350 0.300 0.400 0.0138 0.0118 0.0157 D 8.000 7.900 8.100 0.3150 0.3110 0.3189 D1 5.600 0.2205 ddd 0.100 9.900 E 10.000 E1 7.200 0.2835 E2 8.800 0.3465 e 0.800 FD 1.200 0.0472 FE 1.400 0.0551 FE1 0.600 0.0236 SD 0.400 0.0157 SE 0.400 0.0157 – 10.100 0.0039 – 0.3937 0.0315 0.3898 0.3976 – – 19/22 Part numbering 7 M36W0R6050T1, M36W0R6050B1 Part numbering Table 7. Ordering information scheme Example: M36 W 0 R 6 0 5 0 T 1 ZAQ E Device Type M36 = Multiple Memory Product (Multiple Flash + RAM) Flash 1 Architecture W = Multiple Bank, Burst mode Flash 2 Architecture 0 = none present Operating Voltage R = VDDF = VDDQF = VDDP = 1.7 V to 1.95 V Flash 1 Density 6 = 64 Mbit Flash 2 Density 0 = none present RAM 1 Density 5 = 32 Mbit RAM 0 Density 0 = none present Parameter Blocks Location T = Top Boot Block Flash B = Bottom Boot Block Flash Product Version 1 = 90 nm Flash technology, 70 ns; 0.13 µm RAM, 70 ns speed Package ZAQ = Stacked TFBGA88 8 × 10 mm - 8 × 10 active ball array, 0.8 mm pitch Option E = ECOPACK® Package, Standard Packing F = ECOPACK® Package, Tape & Reel Packing Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you. 20/22 M36W0R6050T1, M36W0R6050B1 8 Revision history Revision history Table 8. Document revision history Date Revision 06-Dec-2005 0.1 12-Jan-2007 1 Changes Initial release. Document status promoted to Full Datasheet. Small text changes. 21/22 M36W0R6050T1, M36W0R6050B1 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. 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